1 /*-
2 * Copyright (c) 2015 Stanislav Galabov
3 * Copyright (c) 2015 Alexander Kabaev
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28
29 #include "opt_platform.h"
30
31 #include <sys/cdefs.h>
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/kernel.h>
36 #include <sys/ktr.h>
37 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/rman.h>
40 #include <sys/pcpu.h>
41 #include <sys/proc.h>
42 #include <sys/cpuset.h>
43 #include <sys/lock.h>
44 #include <sys/mutex.h>
45 #include <sys/smp.h>
46 #include <sys/sched.h>
47 #include <machine/bus.h>
48 #include <machine/intr.h>
49 #include <machine/smp.h>
50
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/openfirm.h>
53 #include <dev/ofw/ofw_bus.h>
54 #include <dev/ofw/ofw_bus_subr.h>
55
56 #include "pic_if.h"
57
58 #define MTK_NIRQS 32
59
60 #define MTK_IRQ0STAT 0x009c
61 #define MTK_IRQ1STAT 0x00a0
62 #define MTK_INTTYPE 0x0000
63 #define MTK_INTRAW 0x00a4
64 #define MTK_INTENA 0x0080
65 #define MTK_INTDIS 0x0078
66
67 static int mtk_pic_intr(void *);
68
69 struct mtk_pic_irqsrc {
70 struct intr_irqsrc isrc;
71 u_int irq;
72 };
73
74 struct mtk_pic_softc {
75 device_t pic_dev;
76 void * pic_intrhand;
77 struct resource * pic_res[2];
78 struct mtk_pic_irqsrc pic_irqs[MTK_NIRQS];
79 struct mtx mutex;
80 uint32_t nirqs;
81 };
82
83 #define PIC_INTR_ISRC(sc, irq) (&(sc)->pic_irqs[(irq)].isrc)
84
85 static struct resource_spec mtk_pic_spec[] = {
86 { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
87 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */
88 // { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Parent interrupt 2 */
89 { -1, 0 }
90 };
91
92 static struct ofw_compat_data compat_data[] = {
93 { "ralink,mt7628an-intc", 1 },
94 { NULL, 0 }
95 };
96
97 #define READ4(_sc, _reg) bus_read_4((_sc)->pic_res[0], _reg)
98 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->pic_res[0], _reg, _val)
99
100 static int
mtk_pic_probe(device_t dev)101 mtk_pic_probe(device_t dev)
102 {
103
104 if (!ofw_bus_status_okay(dev))
105 return (ENXIO);
106
107 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
108 return (ENXIO);
109
110 device_set_desc(dev, "MTK Interrupt Controller (v2)");
111 return (BUS_PROBE_DEFAULT);
112 }
113
114 static inline void
pic_irq_unmask(struct mtk_pic_softc * sc,u_int irq)115 pic_irq_unmask(struct mtk_pic_softc *sc, u_int irq)
116 {
117
118 WRITE4(sc, MTK_INTENA, (1u << (irq)));
119 }
120
121 static inline void
pic_irq_mask(struct mtk_pic_softc * sc,u_int irq)122 pic_irq_mask(struct mtk_pic_softc *sc, u_int irq)
123 {
124
125 WRITE4(sc, MTK_INTDIS, (1u << (irq)));
126 }
127
128 static inline intptr_t
pic_xref(device_t dev)129 pic_xref(device_t dev)
130 {
131 return (OF_xref_from_node(ofw_bus_get_node(dev)));
132 }
133
134 static int
mtk_pic_register_isrcs(struct mtk_pic_softc * sc)135 mtk_pic_register_isrcs(struct mtk_pic_softc *sc)
136 {
137 int error;
138 uint32_t irq;
139 struct intr_irqsrc *isrc;
140 const char *name;
141
142 name = device_get_nameunit(sc->pic_dev);
143 for (irq = 0; irq < sc->nirqs; irq++) {
144 sc->pic_irqs[irq].irq = irq;
145 isrc = PIC_INTR_ISRC(sc, irq);
146 error = intr_isrc_register(isrc, sc->pic_dev, 0, "%s", name);
147 if (error != 0) {
148 /* XXX call intr_isrc_deregister */
149 device_printf(sc->pic_dev, "%s failed", __func__);
150 return (error);
151 }
152 }
153
154 return (0);
155 }
156
157 static int
mtk_pic_attach(device_t dev)158 mtk_pic_attach(device_t dev)
159 {
160 struct mtk_pic_softc *sc;
161 intptr_t xref = pic_xref(dev);
162
163 sc = device_get_softc(dev);
164
165 if (bus_alloc_resources(dev, mtk_pic_spec, sc->pic_res)) {
166 device_printf(dev, "could not allocate resources\n");
167 return (ENXIO);
168 }
169
170 sc->pic_dev = dev;
171
172 /* Initialize mutex */
173 mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
174
175 /* Set the number of interrupts */
176 sc->nirqs = nitems(sc->pic_irqs);
177
178 /* Mask all interrupts */
179 WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
180
181 /* But enable interrupt generation/masking */
182 WRITE4(sc, MTK_INTENA, 0x00000000);
183
184 /* Set all interrupts to type 0 */
185 WRITE4(sc, MTK_INTTYPE, 0xFFFFFFFF);
186
187 /* Register the interrupts */
188 if (mtk_pic_register_isrcs(sc) != 0) {
189 device_printf(dev, "could not register PIC ISRCs\n");
190 goto cleanup;
191 }
192
193 /*
194 * Now, when everything is initialized, it's right time to
195 * register interrupt controller to interrupt framefork.
196 */
197 if (intr_pic_register(dev, xref) == NULL) {
198 device_printf(dev, "could not register PIC\n");
199 goto cleanup;
200 }
201
202 if (bus_setup_intr(dev, sc->pic_res[1], INTR_TYPE_CLK,
203 mtk_pic_intr, NULL, sc, &sc->pic_intrhand)) {
204 device_printf(dev, "could not setup irq handler\n");
205 intr_pic_deregister(dev, xref);
206 goto cleanup;
207 }
208 return (0);
209
210 cleanup:
211 bus_release_resources(dev, mtk_pic_spec, sc->pic_res);
212 return(ENXIO);
213 }
214
215 static int
mtk_pic_intr(void * arg)216 mtk_pic_intr(void *arg)
217 {
218 struct mtk_pic_softc *sc = arg;
219 struct thread *td;
220 uint32_t i, intr;
221
222 td = curthread;
223 /* Workaround: do not inflate intr nesting level */
224 td->td_intr_nesting_level--;
225
226 #ifdef _notyet_
227 intr = READ4(sc, MTK_IRQ1STAT);
228 while ((i = fls(intr)) != 0) {
229 i--;
230 intr &= ~(1u << i);
231
232 if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
233 curthread->td_intr_frame) != 0) {
234 device_printf(sc->pic_dev,
235 "Stray interrupt %u detected\n", i);
236 pic_irq_mask(sc, i);
237 continue;
238 }
239 }
240
241 KASSERT(i == 0, ("all interrupts handled"));
242 #endif
243
244 intr = READ4(sc, MTK_IRQ0STAT);
245
246 while ((i = fls(intr)) != 0) {
247 i--;
248 intr &= ~(1u << i);
249
250 if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
251 curthread->td_intr_frame) != 0) {
252 device_printf(sc->pic_dev,
253 "Stray interrupt %u detected\n", i);
254 pic_irq_mask(sc, i);
255 continue;
256 }
257 }
258
259 KASSERT(i == 0, ("all interrupts handled"));
260
261 td->td_intr_nesting_level++;
262
263 return (FILTER_HANDLED);
264 }
265
266 static int
mtk_pic_map_intr(device_t dev,struct intr_map_data * data,struct intr_irqsrc ** isrcp)267 mtk_pic_map_intr(device_t dev, struct intr_map_data *data,
268 struct intr_irqsrc **isrcp)
269 {
270 #ifdef FDT
271 struct intr_map_data_fdt *daf;
272 struct mtk_pic_softc *sc;
273
274 if (data->type != INTR_MAP_DATA_FDT)
275 return (ENOTSUP);
276
277 sc = device_get_softc(dev);
278 daf = (struct intr_map_data_fdt *)data;
279
280 if (daf->ncells != 1 || daf->cells[0] >= sc->nirqs)
281 return (EINVAL);
282
283 *isrcp = PIC_INTR_ISRC(sc, daf->cells[0]);
284 return (0);
285 #else
286 return (ENOTSUP);
287 #endif
288 }
289
290 static void
mtk_pic_enable_intr(device_t dev,struct intr_irqsrc * isrc)291 mtk_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
292 {
293 u_int irq;
294
295 irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
296 pic_irq_unmask(device_get_softc(dev), irq);
297 }
298
299 static void
mtk_pic_disable_intr(device_t dev,struct intr_irqsrc * isrc)300 mtk_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
301 {
302 u_int irq;
303
304 irq = ((struct mtk_pic_irqsrc *)isrc)->irq;
305 pic_irq_mask(device_get_softc(dev), irq);
306 }
307
308 static void
mtk_pic_pre_ithread(device_t dev,struct intr_irqsrc * isrc)309 mtk_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
310 {
311
312 mtk_pic_disable_intr(dev, isrc);
313 }
314
315 static void
mtk_pic_post_ithread(device_t dev,struct intr_irqsrc * isrc)316 mtk_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
317 {
318
319 mtk_pic_enable_intr(dev, isrc);
320 }
321
322 static void
mtk_pic_post_filter(device_t dev,struct intr_irqsrc * isrc)323 mtk_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
324 {
325 }
326
327 static device_method_t mtk_pic_methods[] = {
328 /* Device interface */
329 DEVMETHOD(device_probe, mtk_pic_probe),
330 DEVMETHOD(device_attach, mtk_pic_attach),
331 /* Interrupt controller interface */
332 DEVMETHOD(pic_disable_intr, mtk_pic_disable_intr),
333 DEVMETHOD(pic_enable_intr, mtk_pic_enable_intr),
334 DEVMETHOD(pic_map_intr, mtk_pic_map_intr),
335 DEVMETHOD(pic_post_filter, mtk_pic_post_filter),
336 DEVMETHOD(pic_post_ithread, mtk_pic_post_ithread),
337 DEVMETHOD(pic_pre_ithread, mtk_pic_pre_ithread),
338 { 0, 0 }
339 };
340
341 static driver_t mtk_pic_driver = {
342 "intc",
343 mtk_pic_methods,
344 sizeof(struct mtk_pic_softc),
345 };
346
347 static devclass_t mtk_pic_devclass;
348
349 EARLY_DRIVER_MODULE(intc_v2, simplebus, mtk_pic_driver, mtk_pic_devclass, 0, 0,
350 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
351