1 /*-
2 * Copyright (c) 2016 Stanislav Galabov.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25 #include <sys/cdefs.h>
26 #include <sys/param.h>
27 #include <sys/systm.h>
28
29 #include <sys/bus.h>
30 #include <sys/interrupt.h>
31 #include <sys/malloc.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/rman.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/endian.h>
38
39 #include <vm/vm.h>
40 #include <vm/pmap.h>
41 #include <vm/vm_extern.h>
42
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/intr.h>
46 #include <machine/pmap.h>
47
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50
51 #include <dev/pci/pcib_private.h>
52
53 #include <dev/fdt/fdt_common.h>
54 #include <dev/fdt/fdt_clock.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus.h>
57 #include <dev/ofw/ofw_bus_subr.h>
58
59 #include <mips/mediatek/mtk_pcie.h>
60 #include <mips/mediatek/mtk_soc.h>
61 #include <mips/mediatek/mtk_sysctl.h>
62 #include <mips/mediatek/fdt_reset.h>
63
64 #include "ofw_bus_if.h"
65 #include "pcib_if.h"
66 #include "pic_if.h"
67
68 /*
69 * Note: We only support PCIe at the moment.
70 * Most SoCs in the Ralink/Mediatek family that we target actually don't
71 * support PCI anyway, with the notable exceptions being RT3662/RT3883, which
72 * support both PCI and PCIe. If there exists a board based on one of them
73 * which is of interest in the future it shouldn't be too hard to enable PCI
74 * support for it.
75 */
76
77 /* Chip specific function declarations */
78 static int mtk_pcie_phy_init(device_t);
79 static int mtk_pcie_phy_start(device_t);
80 static int mtk_pcie_phy_stop(device_t);
81 static int mtk_pcie_phy_mt7621_init(device_t);
82 static int mtk_pcie_phy_mt7628_init(device_t);
83 static int mtk_pcie_phy_mt7620_init(device_t);
84 static int mtk_pcie_phy_rt3883_init(device_t);
85 static void mtk_pcie_phy_setup_slots(device_t);
86
87 /* Generic declarations */
88 struct mtx mtk_pci_mtx;
89 MTX_SYSINIT(mtk_pci_mtx, &mtk_pci_mtx, "MTK PCIe mutex", MTX_SPIN);
90
91 static int mtk_pci_intr(void *);
92
93 static struct mtk_pci_softc *mt_sc = NULL;
94
95 struct mtk_pci_range {
96 u_long base;
97 u_long len;
98 };
99
100 #define FDT_RANGES_CELLS ((1 + 2 + 3) * 2)
101
102 static void
mtk_pci_range_dump(struct mtk_pci_range * range)103 mtk_pci_range_dump(struct mtk_pci_range *range)
104 {
105 #ifdef DEBUG
106 printf("\n");
107 printf(" base = 0x%08lx\n", range->base);
108 printf(" len = 0x%08lx\n", range->len);
109 #endif
110 }
111
112 static int
mtk_pci_ranges_decode(phandle_t node,struct mtk_pci_range * io_space,struct mtk_pci_range * mem_space)113 mtk_pci_ranges_decode(phandle_t node, struct mtk_pci_range *io_space,
114 struct mtk_pci_range *mem_space)
115 {
116 struct mtk_pci_range *pci_space;
117 pcell_t ranges[FDT_RANGES_CELLS];
118 pcell_t addr_cells, size_cells, par_addr_cells;
119 pcell_t *rangesptr;
120 pcell_t cell0, cell1, cell2;
121 int tuple_size, tuples, i, rv, len;
122
123 /*
124 * Retrieve 'ranges' property.
125 */
126 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
127 return (EINVAL);
128 if (addr_cells != 3 || size_cells != 2)
129 return (ERANGE);
130
131 par_addr_cells = fdt_parent_addr_cells(node);
132 if (par_addr_cells != 1)
133 return (ERANGE);
134
135 len = OF_getproplen(node, "ranges");
136 if (len > sizeof(ranges))
137 return (ENOMEM);
138
139 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
140 return (EINVAL);
141
142 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
143 size_cells);
144 tuples = len / tuple_size;
145
146 /*
147 * Initialize the ranges so that we don't have to worry about
148 * having them all defined in the FDT. In particular, it is
149 * perfectly fine not to want I/O space on PCI busses.
150 */
151 bzero(io_space, sizeof(*io_space));
152 bzero(mem_space, sizeof(*mem_space));
153
154 rangesptr = &ranges[0];
155 for (i = 0; i < tuples; i++) {
156 cell0 = fdt_data_get((void *)rangesptr, 1);
157 rangesptr++;
158 cell1 = fdt_data_get((void *)rangesptr, 1);
159 rangesptr++;
160 cell2 = fdt_data_get((void *)rangesptr, 1);
161 rangesptr++;
162
163 if (cell0 & 0x02000000) {
164 pci_space = mem_space;
165 } else if (cell0 & 0x01000000) {
166 pci_space = io_space;
167 } else {
168 rv = ERANGE;
169 goto out;
170 }
171
172 pci_space->base = fdt_data_get((void *)rangesptr,
173 par_addr_cells);
174 rangesptr += par_addr_cells;
175
176 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
177 rangesptr += size_cells;
178 }
179
180 rv = 0;
181 out:
182 return (rv);
183 }
184
185 static int
mtk_pci_ranges(phandle_t node,struct mtk_pci_range * io_space,struct mtk_pci_range * mem_space)186 mtk_pci_ranges(phandle_t node, struct mtk_pci_range *io_space,
187 struct mtk_pci_range *mem_space)
188 {
189 int err;
190
191 if ((err = mtk_pci_ranges_decode(node, io_space, mem_space)) != 0) {
192 return (err);
193 }
194
195 mtk_pci_range_dump(io_space);
196 mtk_pci_range_dump(mem_space);
197
198 return (0);
199 }
200
201 static struct ofw_compat_data compat_data[] = {
202 { "ralink,rt3883-pci", MTK_SOC_RT3883 },
203 { "mediatek,mt7620-pci", MTK_SOC_MT7620A },
204 { "mediatek,mt7628-pci", MTK_SOC_MT7628 },
205 { "mediatek,mt7621-pci", MTK_SOC_MT7621 },
206 { NULL, MTK_SOC_UNKNOWN }
207 };
208
209 static int
mtk_pci_probe(device_t dev)210 mtk_pci_probe(device_t dev)
211 {
212 struct mtk_pci_softc *sc = device_get_softc(dev);
213
214 if (!ofw_bus_status_okay(dev))
215 return (ENXIO);
216
217 sc->socid = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
218 if (sc->socid == MTK_SOC_UNKNOWN)
219 return (ENXIO);
220
221 device_set_desc(dev, "MTK PCIe Controller");
222
223 return (0);
224 }
225
226 static int
mtk_pci_attach(device_t dev)227 mtk_pci_attach(device_t dev)
228 {
229 struct mtk_pci_softc *sc = device_get_softc(dev);
230 struct mtk_pci_range io_space, mem_space;
231 phandle_t node;
232 intptr_t xref;
233 int i, rid;
234
235 sc->sc_dev = dev;
236 mt_sc = sc;
237 sc->addr_mask = 0xffffffff;
238
239 /* Request our memory */
240 rid = 0;
241 sc->pci_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
242 RF_ACTIVE);
243 if (sc->pci_res[0] == NULL) {
244 device_printf(dev, "could not allocate memory resource\n");
245 return (ENXIO);
246 }
247
248 /* See how many interrupts we need */
249 if (sc->socid == MTK_SOC_MT7621)
250 sc->sc_num_irq = 3;
251 else {
252 sc->sc_num_irq = 1;
253 sc->pci_res[2] = sc->pci_res[3] = NULL;
254 sc->pci_intrhand[1] = sc->pci_intrhand[2] = NULL;
255 }
256
257 /* Request our interrupts */
258 for (i = 1; i <= sc->sc_num_irq ; i++) {
259 rid = i - 1;
260 sc->pci_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
261 RF_ACTIVE);
262 if (sc->pci_res[i] == NULL) {
263 device_printf(dev, "could not allocate interrupt "
264 "resource %d\n", rid);
265 goto cleanup_res;
266 }
267 }
268
269 /* Parse our PCI 'ranges' property */
270 node = ofw_bus_get_node(dev);
271 xref = OF_xref_from_node(node);
272 if (mtk_pci_ranges(node, &io_space, &mem_space)) {
273 device_printf(dev, "could not retrieve 'ranges' data\n");
274 goto cleanup_res;
275 }
276
277 /* Memory, I/O and IRQ resource limits */
278 sc->sc_io_base = io_space.base;
279 sc->sc_io_size = io_space.len;
280 sc->sc_mem_base = mem_space.base;
281 sc->sc_mem_size = mem_space.len;
282 sc->sc_irq_start = MTK_PCIE0_IRQ;
283 sc->sc_irq_end = MTK_PCIE2_IRQ;
284
285 /* Init resource managers for memory, I/O and IRQ */
286 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
287 sc->sc_mem_rman.rm_descr = "mtk pcie memory window";
288 if (rman_init(&sc->sc_mem_rman) != 0 ||
289 rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
290 sc->sc_mem_base + sc->sc_mem_size - 1) != 0) {
291 device_printf(dev, "failed to setup memory rman\n");
292 goto cleanup_res;
293 }
294
295 sc->sc_io_rman.rm_type = RMAN_ARRAY;
296 sc->sc_io_rman.rm_descr = "mtk pcie io window";
297 if (rman_init(&sc->sc_io_rman) != 0 ||
298 rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
299 sc->sc_io_base + sc->sc_io_size - 1) != 0) {
300 device_printf(dev, "failed to setup io rman\n");
301 goto cleanup_res;
302 }
303
304 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
305 sc->sc_irq_rman.rm_descr = "mtk pcie irqs";
306 if (rman_init(&sc->sc_irq_rman) != 0 ||
307 rman_manage_region(&sc->sc_irq_rman, sc->sc_irq_start,
308 sc->sc_irq_end) != 0) {
309 device_printf(dev, "failed to setup irq rman\n");
310 goto cleanup_res;
311 }
312
313 /* Do SoC-specific PCIe initialization */
314 if (mtk_pcie_phy_init(dev)) {
315 device_printf(dev, "pcie phy init failed\n");
316 goto cleanup_rman;
317 }
318
319 /* Register ourselves as an interrupt controller */
320 if (intr_pic_register(dev, xref) == NULL) {
321 device_printf(dev, "could not register PIC\n");
322 goto cleanup_rman;
323 }
324
325 /* Set up our interrupt handler */
326 for (i = 1; i <= sc->sc_num_irq; i++) {
327 sc->pci_intrhand[i - 1] = NULL;
328 if (bus_setup_intr(dev, sc->pci_res[i], INTR_TYPE_MISC,
329 mtk_pci_intr, NULL, sc, &sc->pci_intrhand[i - 1])) {
330 device_printf(dev, "could not setup intr handler %d\n",
331 i);
332 goto cleanup;
333 }
334 }
335
336 /* Attach our PCI child so bus enumeration can start */
337 if (device_add_child(dev, "pci", -1) == NULL) {
338 device_printf(dev, "could not attach pci bus\n");
339 goto cleanup;
340 }
341
342 /* And finally, attach ourselves to the bus */
343 if (bus_generic_attach(dev)) {
344 device_printf(dev, "could not attach to bus\n");
345 goto cleanup;
346 }
347
348 return (0);
349
350 cleanup:
351 #ifdef notyet
352 intr_pic_unregister(dev, xref);
353 #endif
354 for (i = 1; i <= sc->sc_num_irq; i++) {
355 if (sc->pci_intrhand[i - 1] != NULL)
356 bus_teardown_intr(dev, sc->pci_res[i],
357 sc->pci_intrhand[i - 1]);
358 }
359 cleanup_rman:
360 mtk_pcie_phy_stop(dev);
361 rman_fini(&sc->sc_irq_rman);
362 rman_fini(&sc->sc_io_rman);
363 rman_fini(&sc->sc_mem_rman);
364 cleanup_res:
365 mt_sc = NULL;
366 if (sc->pci_res[0] != NULL)
367 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->pci_res[0]);
368 if (sc->pci_res[1] != NULL)
369 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pci_res[1]);
370 if (sc->pci_res[2] != NULL)
371 bus_release_resource(dev, SYS_RES_IRQ, 1, sc->pci_res[2]);
372 if (sc->pci_res[3] != NULL)
373 bus_release_resource(dev, SYS_RES_IRQ, 2, sc->pci_res[3]);
374 return (ENXIO);
375 }
376
377 static int
mtk_pci_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)378 mtk_pci_read_ivar(device_t dev, device_t child, int which,
379 uintptr_t *result)
380 {
381 struct mtk_pci_softc *sc = device_get_softc(dev);
382
383 switch (which) {
384 case PCIB_IVAR_DOMAIN:
385 *result = device_get_unit(dev);
386 return (0);
387 case PCIB_IVAR_BUS:
388 *result = sc->sc_busno;
389 return (0);
390 }
391
392 return (ENOENT);
393 }
394
395 static int
mtk_pci_write_ivar(device_t dev,device_t child,int which,uintptr_t result)396 mtk_pci_write_ivar(device_t dev, device_t child, int which,
397 uintptr_t result)
398 {
399 struct mtk_pci_softc *sc = device_get_softc(dev);
400
401 switch (which) {
402 case PCIB_IVAR_BUS:
403 sc->sc_busno = result;
404 return (0);
405 }
406
407 return (ENOENT);
408 }
409
410 static struct resource *
mtk_pci_alloc_resource(device_t bus,device_t child,int type,int * rid,rman_res_t start,rman_res_t end,rman_res_t count,u_int flags)411 mtk_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
412 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
413 {
414 struct mtk_pci_softc *sc = device_get_softc(bus);
415 struct resource *rv;
416 struct rman *rm;
417
418 switch (type) {
419 case PCI_RES_BUS:
420 return pci_domain_alloc_bus(0, child, rid, start, end, count,
421 flags);
422 case SYS_RES_IRQ:
423 rm = &sc->sc_irq_rman;
424 break;
425 case SYS_RES_IOPORT:
426 rm = &sc->sc_io_rman;
427 break;
428 case SYS_RES_MEMORY:
429 rm = &sc->sc_mem_rman;
430 break;
431 default:
432 return (NULL);
433 }
434
435 rv = rman_reserve_resource(rm, start, end, count, flags, child);
436
437 if (rv == NULL)
438 return (NULL);
439
440 rman_set_rid(rv, *rid);
441
442 if ((flags & RF_ACTIVE) && type != SYS_RES_IRQ) {
443 if (bus_activate_resource(child, type, *rid, rv)) {
444 rman_release_resource(rv);
445 return (NULL);
446 }
447 }
448
449 return (rv);
450 }
451
452 static int
mtk_pci_release_resource(device_t bus,device_t child,int type,int rid,struct resource * res)453 mtk_pci_release_resource(device_t bus, device_t child, int type, int rid,
454 struct resource *res)
455 {
456
457 if (type == PCI_RES_BUS)
458 return (pci_domain_release_bus(0, child, rid, res));
459
460 return (bus_generic_release_resource(bus, child, type, rid, res));
461 }
462
463 static int
mtk_pci_adjust_resource(device_t bus,device_t child,int type,struct resource * res,rman_res_t start,rman_res_t end)464 mtk_pci_adjust_resource(device_t bus, device_t child, int type,
465 struct resource *res, rman_res_t start, rman_res_t end)
466 {
467 struct mtk_pci_softc *sc = device_get_softc(bus);
468 struct rman *rm;
469
470 switch (type) {
471 case PCI_RES_BUS:
472 return pci_domain_adjust_bus(0, child, res, start, end);
473 case SYS_RES_IRQ:
474 rm = &sc->sc_irq_rman;
475 break;
476 case SYS_RES_IOPORT:
477 rm = &sc->sc_io_rman;
478 break;
479 case SYS_RES_MEMORY:
480 rm = &sc->sc_mem_rman;
481 break;
482 default:
483 rm = NULL;
484 break;
485 }
486
487 if (rm != NULL)
488 return (rman_adjust_resource(res, start, end));
489
490 return (bus_generic_adjust_resource(bus, child, type, res, start, end));
491 }
492
493 static inline int
mtk_idx_to_irq(int idx)494 mtk_idx_to_irq(int idx)
495 {
496
497 return ((idx == 0) ? MTK_PCIE0_IRQ :
498 (idx == 1) ? MTK_PCIE1_IRQ :
499 (idx == 2) ? MTK_PCIE2_IRQ : -1);
500 }
501
502 static inline int
mtk_irq_to_idx(int irq)503 mtk_irq_to_idx(int irq)
504 {
505
506 return ((irq == MTK_PCIE0_IRQ) ? 0 :
507 (irq == MTK_PCIE1_IRQ) ? 1 :
508 (irq == MTK_PCIE2_IRQ) ? 2 : -1);
509 }
510
511 static void
mtk_pci_mask_irq(void * source)512 mtk_pci_mask_irq(void *source)
513 {
514 MT_WRITE32(mt_sc, MTK_PCI_PCIENA,
515 MT_READ32(mt_sc, MTK_PCI_PCIENA) & ~(1<<((int)source)));
516 }
517
518 static void
mtk_pci_unmask_irq(void * source)519 mtk_pci_unmask_irq(void *source)
520 {
521
522 MT_WRITE32(mt_sc, MTK_PCI_PCIENA,
523 MT_READ32(mt_sc, MTK_PCI_PCIENA) | (1<<((int)source)));
524 }
525
526 static int
mtk_pci_setup_intr(device_t bus,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * handler,void * arg,void ** cookiep)527 mtk_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
528 int flags, driver_filter_t *filt, driver_intr_t *handler,
529 void *arg, void **cookiep)
530 {
531 struct mtk_pci_softc *sc = device_get_softc(bus);
532 struct intr_event *event;
533 int irq, error, irqidx;
534
535 irq = rman_get_start(ires);
536
537 if (irq < sc->sc_irq_start || irq > sc->sc_irq_end)
538 return (EINVAL);
539
540 irqidx = irq - sc->sc_irq_start;
541
542 event = sc->sc_eventstab[irqidx];
543 if (event == NULL) {
544 error = intr_event_create(&event, (void *)irq, 0, irq,
545 mtk_pci_mask_irq, mtk_pci_unmask_irq, NULL, NULL,
546 "pci intr%d:", irq);
547
548 if (error == 0) {
549 sc->sc_eventstab[irqidx] = event;
550 }
551 else {
552 return (error);
553 }
554 }
555
556 intr_event_add_handler(event, device_get_nameunit(child), filt,
557 handler, arg, intr_priority(flags), flags, cookiep);
558
559 mtk_pci_unmask_irq((void*)irq);
560
561 return (0);
562 }
563
564 static int
mtk_pci_teardown_intr(device_t dev,device_t child,struct resource * ires,void * cookie)565 mtk_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
566 void *cookie)
567 {
568 struct mtk_pci_softc *sc = device_get_softc(dev);
569 int irq, result, irqidx;
570
571 irq = rman_get_start(ires);
572 if (irq < sc->sc_irq_start || irq > sc->sc_irq_end)
573 return (EINVAL);
574
575 irqidx = irq - sc->sc_irq_start;
576 if (sc->sc_eventstab[irqidx] == NULL)
577 panic("Trying to teardown unoccupied IRQ");
578
579 mtk_pci_mask_irq((void*)irq);
580
581 result = intr_event_remove_handler(cookie);
582 if (!result)
583 sc->sc_eventstab[irqidx] = NULL;
584
585 return (result);
586 }
587
588 static inline uint32_t
mtk_pci_make_addr(int bus,int slot,int func,int reg)589 mtk_pci_make_addr(int bus, int slot, int func, int reg)
590 {
591 uint32_t addr;
592
593 addr = ((((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
594 (func << 8) | (reg & 0xfc) | (1 << 31));
595
596 return (addr);
597 }
598
599 static int
mtk_pci_maxslots(device_t dev)600 mtk_pci_maxslots(device_t dev)
601 {
602
603 return (PCI_SLOTMAX);
604 }
605
606 static inline int
mtk_pci_slot_has_link(device_t dev,int slot)607 mtk_pci_slot_has_link(device_t dev, int slot)
608 {
609 struct mtk_pci_softc *sc = device_get_softc(dev);
610
611 return !!(sc->pcie_link_status & (1<<slot));
612 }
613
614 static uint32_t
mtk_pci_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)615 mtk_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
616 u_int reg, int bytes)
617 {
618 struct mtk_pci_softc *sc = device_get_softc(dev);
619 uint32_t addr = 0, data = 0;
620
621 /* Return ~0U if slot has no link */
622 if (bus == 0 && mtk_pci_slot_has_link(dev, slot) == 0) {
623 return (~0U);
624 }
625
626 mtx_lock_spin(&mtk_pci_mtx);
627 addr = mtk_pci_make_addr(bus, slot, func, (reg & ~3)) & sc->addr_mask;
628 MT_WRITE32(sc, MTK_PCI_CFGADDR, addr);
629 switch (bytes % 4) {
630 case 0:
631 data = MT_READ32(sc, MTK_PCI_CFGDATA);
632 break;
633 case 1:
634 data = MT_READ8(sc, MTK_PCI_CFGDATA + (reg & 0x3));
635 break;
636 case 2:
637 data = MT_READ16(sc, MTK_PCI_CFGDATA + (reg & 0x3));
638 break;
639 default:
640 panic("%s(): Wrong number of bytes (%d) requested!\n",
641 __FUNCTION__, bytes % 4);
642 }
643 mtx_unlock_spin(&mtk_pci_mtx);
644
645 return (data);
646 }
647
648 static void
mtk_pci_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)649 mtk_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
650 u_int reg, uint32_t val, int bytes)
651 {
652 struct mtk_pci_softc *sc = device_get_softc(dev);
653 uint32_t addr = 0, data = val;
654
655 /* Do not write if slot has no link */
656 if (bus == 0 && mtk_pci_slot_has_link(dev, slot) == 0)
657 return;
658
659 mtx_lock_spin(&mtk_pci_mtx);
660 addr = mtk_pci_make_addr(bus, slot, func, (reg & ~3)) & sc->addr_mask;
661 MT_WRITE32(sc, MTK_PCI_CFGADDR, addr);
662 switch (bytes % 4) {
663 case 0:
664 MT_WRITE32(sc, MTK_PCI_CFGDATA, data);
665 break;
666 case 1:
667 MT_WRITE8(sc, MTK_PCI_CFGDATA + (reg & 0x3), data);
668 break;
669 case 2:
670 MT_WRITE16(sc, MTK_PCI_CFGDATA + (reg & 0x3), data);
671 break;
672 default:
673 panic("%s(): Wrong number of bytes (%d) requested!\n",
674 __FUNCTION__, bytes % 4);
675 }
676 mtx_unlock_spin(&mtk_pci_mtx);
677 }
678
679 static int
mtk_pci_route_interrupt(device_t pcib,device_t device,int pin)680 mtk_pci_route_interrupt(device_t pcib, device_t device, int pin)
681 {
682 int bus, sl, dev;
683
684 bus = pci_get_bus(device);
685 sl = pci_get_slot(device);
686 dev = pci_get_device(device);
687
688 if (bus != 0)
689 panic("Unexpected bus number %d\n", bus);
690
691 /* PCIe only */
692 switch (sl) {
693 case 0: return MTK_PCIE0_IRQ;
694 case 1: return MTK_PCIE0_IRQ + 1;
695 case 2: return MTK_PCIE0_IRQ + 2;
696 default: return (-1);
697 }
698
699 return (-1);
700 }
701
702 static device_method_t mtk_pci_methods[] = {
703 /* Device interface */
704 DEVMETHOD(device_probe, mtk_pci_probe),
705 DEVMETHOD(device_attach, mtk_pci_attach),
706 DEVMETHOD(device_shutdown, bus_generic_shutdown),
707 DEVMETHOD(device_suspend, bus_generic_suspend),
708 DEVMETHOD(device_resume, bus_generic_resume),
709
710 /* Bus interface */
711 DEVMETHOD(bus_read_ivar, mtk_pci_read_ivar),
712 DEVMETHOD(bus_write_ivar, mtk_pci_write_ivar),
713 DEVMETHOD(bus_alloc_resource, mtk_pci_alloc_resource),
714 DEVMETHOD(bus_release_resource, mtk_pci_release_resource),
715 DEVMETHOD(bus_adjust_resource, mtk_pci_adjust_resource),
716 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
717 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
718 DEVMETHOD(bus_setup_intr, mtk_pci_setup_intr),
719 DEVMETHOD(bus_teardown_intr, mtk_pci_teardown_intr),
720
721 /* pcib interface */
722 DEVMETHOD(pcib_maxslots, mtk_pci_maxslots),
723 DEVMETHOD(pcib_read_config, mtk_pci_read_config),
724 DEVMETHOD(pcib_write_config, mtk_pci_write_config),
725 DEVMETHOD(pcib_route_interrupt, mtk_pci_route_interrupt),
726 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
727
728 /* OFW bus interface */
729 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
730 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
731 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
732 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
733 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
734
735 DEVMETHOD_END
736 };
737
738 static driver_t mtk_pci_driver = {
739 "pcib",
740 mtk_pci_methods,
741 sizeof(struct mtk_pci_softc),
742 };
743
744 static devclass_t mtk_pci_devclass;
745
746 DRIVER_MODULE(mtk_pci, simplebus, mtk_pci_driver, mtk_pci_devclass, 0, 0);
747
748 /* Our interrupt handler */
749 static int
mtk_pci_intr(void * arg)750 mtk_pci_intr(void *arg)
751 {
752 struct mtk_pci_softc *sc = arg;
753 struct intr_event *event;
754 uint32_t reg, irq, irqidx;
755
756 reg = MT_READ32(sc, MTK_PCI_PCIINT);
757
758 for (irq = sc->sc_irq_start; irq <= sc->sc_irq_end; irq++) {
759 if (reg & (1u<<irq)) {
760 irqidx = irq - sc->sc_irq_start;
761 event = sc->sc_eventstab[irqidx];
762 if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {
763 if (irq != 0)
764 printf("Stray PCI IRQ %d\n", irq);
765 continue;
766 }
767
768 intr_event_handle(event, NULL);
769 }
770 }
771
772 return (FILTER_HANDLED);
773 }
774
775 /* PCIe SoC-specific initialization */
776 static int
mtk_pcie_phy_init(device_t dev)777 mtk_pcie_phy_init(device_t dev)
778 {
779 struct mtk_pci_softc *sc;
780
781 /* Get our softc */
782 sc = device_get_softc(dev);
783
784 /* We don't know how many slots we have yet */
785 sc->num_slots = 0;
786
787 /* Handle SoC specific PCIe init */
788 switch (sc->socid) {
789 case MTK_SOC_MT7628: /* Fallthrough */
790 case MTK_SOC_MT7688:
791 if (mtk_pcie_phy_mt7628_init(dev))
792 return (ENXIO);
793 break;
794 case MTK_SOC_MT7621:
795 if (mtk_pcie_phy_mt7621_init(dev))
796 return (ENXIO);
797 break;
798 case MTK_SOC_MT7620A:
799 if (mtk_pcie_phy_mt7620_init(dev))
800 return (ENXIO);
801 break;
802 case MTK_SOC_RT3662: /* Fallthrough */
803 case MTK_SOC_RT3883:
804 if (mtk_pcie_phy_rt3883_init(dev))
805 return (ENXIO);
806 break;
807 default:
808 device_printf(dev, "unsupported device %x\n", sc->socid);
809 return (ENXIO);
810 }
811
812 /*
813 * If we were successful so far go and set up the PCIe slots, so we
814 * may allocate mem/io/irq resources and enumerate busses later.
815 */
816 mtk_pcie_phy_setup_slots(dev);
817
818 return (0);
819 }
820
821 static int
mtk_pcie_phy_start(device_t dev)822 mtk_pcie_phy_start(device_t dev)
823 {
824 struct mtk_pci_softc *sc = device_get_softc(dev);
825
826 if (sc->socid == MTK_SOC_MT7621 &&
827 (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) !=
828 SYSCTL_MT7621_REV_E) {
829 if (fdt_reset_assert_all(dev))
830 return (ENXIO);
831 } else {
832 if (fdt_reset_deassert_all(dev))
833 return (ENXIO);
834 }
835
836 if (fdt_clock_enable_all(dev))
837 return (ENXIO);
838
839 return (0);
840 }
841
842 static int
mtk_pcie_phy_stop(device_t dev)843 mtk_pcie_phy_stop(device_t dev)
844 {
845 struct mtk_pci_softc *sc = device_get_softc(dev);
846
847 if (sc->socid == MTK_SOC_MT7621 &&
848 (mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) !=
849 SYSCTL_MT7621_REV_E) {
850 if (fdt_reset_deassert_all(dev))
851 return (ENXIO);
852 } else {
853 if (fdt_reset_assert_all(dev))
854 return (ENXIO);
855 }
856
857 if (fdt_clock_disable_all(dev))
858 return (ENXIO);
859
860 return (0);
861 }
862
863 #define mtk_pcie_phy_set(_sc, _reg, _s, _n, _v) \
864 MT_WRITE32((_sc), (_reg), ((MT_READ32((_sc), (_reg)) & \
865 (~(((1ull << (_n)) - 1) << (_s)))) | ((_v) << (_s))))
866
867 static void
mtk_pcie_phy_mt7621_bypass_pipe_rst(struct mtk_pci_softc * sc,uint32_t off)868 mtk_pcie_phy_mt7621_bypass_pipe_rst(struct mtk_pci_softc *sc, uint32_t off)
869 {
870
871 mtk_pcie_phy_set(sc, off + 0x002c, 12, 1, 1);
872 mtk_pcie_phy_set(sc, off + 0x002c, 4, 1, 1);
873 mtk_pcie_phy_set(sc, off + 0x012c, 12, 1, 1);
874 mtk_pcie_phy_set(sc, off + 0x012c, 4, 1, 1);
875 mtk_pcie_phy_set(sc, off + 0x102c, 12, 1, 1);
876 mtk_pcie_phy_set(sc, off + 0x102c, 4, 1, 1);
877 }
878
879 static void
mtk_pcie_phy_mt7621_setup_ssc(struct mtk_pci_softc * sc,uint32_t off)880 mtk_pcie_phy_mt7621_setup_ssc(struct mtk_pci_softc *sc, uint32_t off)
881 {
882 uint32_t xtal_sel;
883
884 xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6;
885 xtal_sel &= 0x7;
886
887 mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1);
888 mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0);
889 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1);
890 mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 1);
891 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0);
892 mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 0);
893
894 if (xtal_sel <= 5 && xtal_sel >= 3) {
895 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 1);
896 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a);
897 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a);
898 } else {
899 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0);
900 if (xtal_sel >= 6) {
901 mtk_pcie_phy_set(sc, off + 0x4bc, 4, 2, 0x01);
902 mtk_pcie_phy_set(sc, off + 0x49c, 0, 31, 0x18000000);
903 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x18d);
904 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x4a);
905 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x4a);
906 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x11);
907 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x11);
908 } else {
909 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 12, 0x1a);
910 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 12, 0x1a);
911 }
912 }
913
914 mtk_pcie_phy_set(sc, off + 0x4a0, 5, 1, 1);
915 mtk_pcie_phy_set(sc, off + 0x490, 22, 2, 2);
916 mtk_pcie_phy_set(sc, off + 0x490, 18, 4, 6);
917 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 2);
918 mtk_pcie_phy_set(sc, off + 0x490, 8, 4, 1);
919 mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 0);
920 mtk_pcie_phy_set(sc, off + 0x490, 1, 3, 2);
921
922 if (xtal_sel <= 5 && xtal_sel >= 3) {
923 mtk_pcie_phy_set(sc, off + 0x414, 6, 2, 1);
924 mtk_pcie_phy_set(sc, off + 0x414, 5, 1, 1);
925 }
926
927 mtk_pcie_phy_set(sc, off + 0x414, 28, 2, 1);
928 mtk_pcie_phy_set(sc, off + 0x040, 17, 4, 7);
929 mtk_pcie_phy_set(sc, off + 0x040, 16, 1, 1);
930 mtk_pcie_phy_set(sc, off + 0x140, 17, 4, 7);
931 mtk_pcie_phy_set(sc, off + 0x140, 16, 1, 1);
932
933 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1);
934 mtk_pcie_phy_set(sc, off + 0x100, 5, 1, 1);
935 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0);
936 mtk_pcie_phy_set(sc, off + 0x100, 4, 1, 0);
937 }
938
939 /* XXX: ugly, we need to fix this at some point */
940 #define MT7621_GPIO_CTRL0 *((volatile uint32_t *)0xbe000600)
941 #define MT7621_GPIO_DATA0 *((volatile uint32_t *)0xbe000620)
942
943 #define mtk_gpio_clr_set(_reg, _clr, _set) \
944 do { \
945 (_reg) = ((_reg) & (_clr)) | (_set); \
946 } while (0)
947
948 static int
mtk_pcie_phy_mt7621_init(device_t dev)949 mtk_pcie_phy_mt7621_init(device_t dev)
950 {
951 struct mtk_pci_softc *sc = device_get_softc(dev);
952
953 /* First off, stop the PHY */
954 if (mtk_pcie_phy_stop(dev))
955 return (ENXIO);
956
957 /* PCIe resets are GPIO pins */
958 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7621_PERST_GPIO_MODE |
959 MT7621_UARTL3_GPIO_MODE, MT7621_PERST_GPIO | MT7621_UARTL3_GPIO);
960
961 /* Set GPIO pins as outputs */
962 mtk_gpio_clr_set(MT7621_GPIO_CTRL0, 0, MT7621_PCIE_RST);
963
964 /* Assert resets to PCIe devices */
965 mtk_gpio_clr_set(MT7621_GPIO_DATA0, MT7621_PCIE_RST, 0);
966
967 /* Give everything a chance to sink in */
968 DELAY(100000);
969
970 /* Now start the PHY again */
971 if (mtk_pcie_phy_start(dev))
972 return (ENXIO);
973
974 /* Wait for things to settle */
975 DELAY(100000);
976
977 /* Only apply below to REV-E hardware */
978 if ((mtk_sysctl_get(SYSCTL_REVID) & SYSCTL_REVID_MASK) ==
979 SYSCTL_MT7621_REV_E)
980 mtk_pcie_phy_mt7621_bypass_pipe_rst(sc, 0x9000);
981
982 /* Setup PCIe ports 0 and 1 */
983 mtk_pcie_phy_mt7621_setup_ssc(sc, 0x9000);
984 /* Setup PCIe port 2 */
985 mtk_pcie_phy_mt7621_setup_ssc(sc, 0xa000);
986
987 /* Deassert resets to PCIe devices */
988 mtk_gpio_clr_set(MT7621_GPIO_DATA0, 0, MT7621_PCIE_RST);
989
990 /* Set number of slots supported */
991 sc->num_slots = 3;
992
993 /* Give it a chance to sink in */
994 DELAY(100000);
995
996 return (0);
997 }
998
999 static void
mtk_pcie_phy_mt7628_setup(struct mtk_pci_softc * sc,uint32_t off)1000 mtk_pcie_phy_mt7628_setup(struct mtk_pci_softc *sc, uint32_t off)
1001 {
1002 uint32_t xtal_sel;
1003
1004 xtal_sel = mtk_sysctl_get(SYSCTL_SYSCFG) >> 6;
1005 xtal_sel &= 0x1;
1006
1007 mtk_pcie_phy_set(sc, off + 0x400, 8, 1, 1);
1008 mtk_pcie_phy_set(sc, off + 0x400, 9, 2, 0);
1009 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 1);
1010 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 0);
1011 mtk_pcie_phy_set(sc, off + 0x4ac, 16, 3, 3);
1012
1013 if (xtal_sel == 1) {
1014 mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x7d);
1015 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x08);
1016 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x01);
1017 mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x1f400000);
1018 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x013d);
1019 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x74);
1020 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x74);
1021 } else {
1022 mtk_pcie_phy_set(sc, off + 0x4bc, 24, 8, 0x64);
1023 mtk_pcie_phy_set(sc, off + 0x490, 12, 4, 0x0a);
1024 mtk_pcie_phy_set(sc, off + 0x490, 6, 2, 0x00);
1025 mtk_pcie_phy_set(sc, off + 0x4c0, 0, 32, 0x19000000);
1026 mtk_pcie_phy_set(sc, off + 0x4a4, 0, 16, 0x018d);
1027 mtk_pcie_phy_set(sc, off + 0x4a8, 16, 16, 0x4a);
1028 mtk_pcie_phy_set(sc, off + 0x4a8, 0, 16, 0x4a);
1029 }
1030
1031 mtk_pcie_phy_set(sc, off + 0x498, 0, 8, 5);
1032 mtk_pcie_phy_set(sc, off + 0x000, 5, 1, 1);
1033 mtk_pcie_phy_set(sc, off + 0x000, 4, 1, 0);
1034 }
1035
1036 static int
mtk_pcie_phy_mt7628_init(device_t dev)1037 mtk_pcie_phy_mt7628_init(device_t dev)
1038 {
1039 struct mtk_pci_softc *sc = device_get_softc(dev);
1040
1041 /* Set PCIe reset to normal mode */
1042 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7628_PERST_GPIO_MODE,
1043 MT7628_PERST);
1044
1045 /* Start the PHY */
1046 if (mtk_pcie_phy_start(dev))
1047 return (ENXIO);
1048
1049 /* Give it a chance to sink in */
1050 DELAY(100000);
1051
1052 /* Setup the PHY */
1053 mtk_pcie_phy_mt7628_setup(sc, 0x9000);
1054
1055 /* Deassert PCIe device reset */
1056 MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0);
1057
1058 /* Set number of slots supported */
1059 sc->num_slots = 1;
1060
1061 return (0);
1062 }
1063
1064 static int
mtk_pcie_phy_mt7620_wait_busy(struct mtk_pci_softc * sc)1065 mtk_pcie_phy_mt7620_wait_busy(struct mtk_pci_softc *sc)
1066 {
1067 uint32_t reg_value, retry;
1068
1069 reg_value = retry = 0;
1070
1071 while (retry++ < MT7620_MAX_RETRIES) {
1072 reg_value = MT_READ32(sc, MT7620_PCIE_PHY_CFG);
1073 if (reg_value & PHY_BUSY)
1074 DELAY(100000);
1075 else
1076 break;
1077 }
1078
1079 if (retry >= MT7620_MAX_RETRIES)
1080 return (ENXIO);
1081
1082 return (0);
1083 }
1084
1085 static int
mtk_pcie_phy_mt7620_set(struct mtk_pci_softc * sc,uint32_t reg,uint32_t val)1086 mtk_pcie_phy_mt7620_set(struct mtk_pci_softc *sc, uint32_t reg,
1087 uint32_t val)
1088 {
1089 uint32_t reg_val;
1090
1091 if (mtk_pcie_phy_mt7620_wait_busy(sc))
1092 return (ENXIO);
1093
1094 reg_val = PHY_MODE_WRITE | ((reg & 0xff) << PHY_ADDR_OFFSET) |
1095 (val & 0xff);
1096 MT_WRITE32(sc, MT7620_PCIE_PHY_CFG, reg_val);
1097 DELAY(1000);
1098
1099 if (mtk_pcie_phy_mt7620_wait_busy(sc))
1100 return (ENXIO);
1101
1102 return (0);
1103 }
1104
1105 static int
mtk_pcie_phy_mt7620_init(device_t dev)1106 mtk_pcie_phy_mt7620_init(device_t dev)
1107 {
1108 struct mtk_pci_softc *sc = device_get_softc(dev);
1109
1110 /*
1111 * The below sets the PCIe PHY to bypass the PCIe DLL and enables
1112 * "elastic buffer control", whatever that may be...
1113 */
1114 if (mtk_pcie_phy_mt7620_set(sc, 0x00, 0x80) ||
1115 mtk_pcie_phy_mt7620_set(sc, 0x01, 0x04) ||
1116 mtk_pcie_phy_mt7620_set(sc, 0x68, 0x84))
1117 return (ENXIO);
1118
1119 /* Stop PCIe */
1120 if (mtk_pcie_phy_stop(dev))
1121 return (ENXIO);
1122
1123 /* Restore PPLL to a sane state before going on */
1124 mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVPD, PDRV_SW_SET);
1125
1126 /* No PCIe on the MT7620N */
1127 if (!(mtk_sysctl_get(SYSCTL_REVID) & MT7620_PKG_BGA)) {
1128 device_printf(dev, "PCIe disabled for MT7620N\n");
1129 mtk_sysctl_clr_set(MT7620_PPLL_CFG0, 0, PPLL_SW_SET);
1130 mtk_sysctl_clr_set(MT7620_PPLL_CFG1, 0, PPLL_PD);
1131 return (ENXIO);
1132 }
1133
1134 /* PCIe device reset pin is in normal mode */
1135 mtk_sysctl_clr_set(SYSCTL_GPIOMODE, MT7620_PERST_GPIO_MODE,
1136 MT7620_PERST);
1137
1138 /* Enable PCIe now */
1139 if (mtk_pcie_phy_start(dev))
1140 return (ENXIO);
1141
1142 /* Give it a chance to sink in */
1143 DELAY(100000);
1144
1145 /* If PLL is not locked - bail */
1146 if (!(mtk_sysctl_get(MT7620_PPLL_CFG1) & PPLL_LOCKED)) {
1147 device_printf(dev, "no PPLL not lock\n");
1148 mtk_pcie_phy_stop(dev);
1149 return (ENXIO);
1150 }
1151
1152 /* Configure PCIe PLL */
1153 mtk_sysctl_clr_set(MT7620_PPLL_DRV, LC_CKDRVOHZ | LC_CKDRVHZ,
1154 LC_CKDRVPD | PDRV_SW_SET);
1155
1156 /* and give it a chance to settle */
1157 DELAY(100000);
1158
1159 /* Deassert PCIe device reset */
1160 MT_CLR_SET32(sc, MTK_PCI_PCICFG, MTK_PCI_RESET, 0);
1161
1162 /* MT7620 supports one PCIe slot */
1163 sc->num_slots = 1;
1164
1165 return (0);
1166 }
1167
1168 static int
mtk_pcie_phy_rt3883_init(device_t dev)1169 mtk_pcie_phy_rt3883_init(device_t dev)
1170 {
1171 struct mtk_pci_softc *sc = device_get_softc(dev);
1172
1173 /* Enable PCI host mode and PCIe RC mode */
1174 mtk_sysctl_clr_set(SYSCTL_SYSCFG1, 0, RT3883_PCI_HOST_MODE |
1175 RT3883_PCIE_RC_MODE);
1176
1177 /* Enable PCIe PHY */
1178 if (mtk_pcie_phy_start(dev))
1179 return (ENXIO);
1180
1181 /* Disable PCI, we only support PCIe for now */
1182 mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, RT3883_PCI_RST);
1183 mtk_sysctl_clr_set(SYSCTL_CLKCFG1, RT3883_PCI_CLK, 0);
1184
1185 /* Give things a chance to sink in */
1186 DELAY(500000);
1187
1188 /* Set PCIe port number to 0 and lift PCIe reset */
1189 MT_WRITE32(sc, MTK_PCI_PCICFG, 0);
1190
1191 /* Configure PCI Arbiter */
1192 MT_WRITE32(sc, MTK_PCI_ARBCTL, 0x79);
1193
1194 /* We have a single PCIe slot */
1195 sc->num_slots = 1;
1196
1197 return (0);
1198 }
1199
1200 static void
mtk_pcie_phy_setup_slots(device_t dev)1201 mtk_pcie_phy_setup_slots(device_t dev)
1202 {
1203 struct mtk_pci_softc *sc = device_get_softc(dev);
1204 uint32_t bar0_val, val;
1205 int i;
1206
1207 /* Disable all PCIe interrupts */
1208 MT_WRITE32(sc, MTK_PCI_PCIENA, 0);
1209
1210 /* Default bar0_val is 64M, enabled */
1211 bar0_val = 0x03FF0001;
1212
1213 /* But we override it to 2G, enabled for some SoCs */
1214 if (sc->socid == MTK_SOC_MT7620A || sc->socid == MTK_SOC_MT7628 ||
1215 sc->socid == MTK_SOC_MT7688 || sc->socid == MTK_SOC_MT7621)
1216 bar0_val = 0x7FFF0001;
1217
1218 /* We still don't know which slots have linked up */
1219 sc->pcie_link_status = 0;
1220
1221 /* XXX: I am not sure if this delay is really necessary */
1222 DELAY(500000);
1223
1224 /*
1225 * See which slots have links and mark them.
1226 * Set up all slots' BARs and make them look like PCIe bridges.
1227 */
1228 for (i = 0; i < sc->num_slots; i++) {
1229 /* If slot has link - mark it */
1230 if (MT_READ32(sc, MTK_PCIE_STATUS(i)) & 1)
1231 sc->pcie_link_status |= (1<<i);
1232 else
1233 continue;
1234
1235 /* Generic slot configuration follows */
1236
1237 /* We enable BAR0 */
1238 MT_WRITE32(sc, MTK_PCIE_BAR0SETUP(i), bar0_val);
1239 /* and disable BAR1 */
1240 MT_WRITE32(sc, MTK_PCIE_BAR1SETUP(i), 0);
1241 /* Internal memory base has no offset */
1242 MT_WRITE32(sc, MTK_PCIE_IMBASEBAR0(i), 0);
1243 /* We're a PCIe bridge */
1244 MT_WRITE32(sc, MTK_PCIE_CLASS(i), 0x06040001);
1245
1246 val = mtk_pci_read_config(dev, 0, i, 0, 0x4, 4);
1247 mtk_pci_write_config(dev, 0, i, 0, 0x4, val | 0x4, 4);
1248 val = mtk_pci_read_config(dev, 0, i, 0, 0x70c, 4);
1249 val &= ~(0xff << 8);
1250 val |= (0x50 << 8);
1251 mtk_pci_write_config(dev, 0, i, 0, 0x70c, val, 4);
1252
1253 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEL_1, 0xff, 1);
1254 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOBASEH_1, 0xffff, 2);
1255 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITL_1, 0, 1);
1256 mtk_pci_write_config(dev, 0, i, 0, PCIR_IOLIMITH_1, 0, 2);
1257 mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMBASE_1, 0xffff, 2);
1258 mtk_pci_write_config(dev, 0, i, 0, PCIR_MEMLIMIT_1, 0, 2);
1259 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEL_1, 0xffff, 2);
1260 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMBASEH_1, 0xffffffff,
1261 4);
1262 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITL_1, 0, 2);
1263 mtk_pci_write_config(dev, 0, i, 0, PCIR_PMLIMITH_1, 0, 4);
1264 }
1265 }
1266