1 /*- 2 * Copyright (c) 2016 Stanislav Galabov. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 #ifndef __MTK_PCIE_H__ 27 #define __MTK_PCIE_H__ 28 29 #define MTK_PCI_NIRQS 3 30 #define MTK_PCI_BASESLOT 0 31 32 struct mtk_pci_softc { 33 device_t sc_dev; 34 35 struct resource * pci_res[MTK_PCI_NIRQS + 1]; 36 void * pci_intrhand[MTK_PCI_NIRQS]; 37 38 int sc_busno; 39 int sc_cur_secbus; 40 41 struct rman sc_mem_rman; 42 struct rman sc_io_rman; 43 struct rman sc_irq_rman; 44 45 uint32_t sc_num_irq; 46 uint32_t sc_irq_start; 47 uint32_t sc_irq_end; 48 49 bus_addr_t sc_mem_base; 50 bus_addr_t sc_mem_size; 51 52 bus_addr_t sc_io_base; 53 bus_addr_t sc_io_size; 54 55 struct intr_event *sc_eventstab[MTK_PCI_NIRQS]; 56 57 uint32_t pcie_link_status; 58 uint32_t num_slots; 59 uint32_t socid; 60 uint32_t addr_mask; 61 }; 62 63 #define MTK_PCI_PCICFG 0x0000 64 #define MTK_PCI_RESET (1<<1) 65 #define MTK_PCI_PCIINT 0x0008 66 #define MTK_PCI_PCIENA 0x000C 67 #define MTK_PCI_CFGADDR 0x0020 68 #define MTK_PCI_CFGDATA 0x0024 69 #define MTK_PCI_MEMBASE 0x0028 70 #define MTK_PCI_IOBASE 0x002C 71 #define MTK_PCI_ARBCTL 0x0080 72 #define MTK_PCI_PHY0_CFG 0x0090 73 74 #define MTK_PCI_PCIE0_BAR0SETUP 0x2010 75 #define MTK_PCI_PCIE0_BAR1SETUP 0x2014 76 #define MTK_PCI_PCIE0_IMBASEBAR0 0x2018 77 #define MTK_PCI_PCIE0_ID 0x2030 78 #define MTK_PCI_PCIE0_CLASS 0x2034 79 #define MTK_PCI_PCIE0_SUBID 0x2038 80 #define MTK_PCI_PCIE0_STATUS 0x2050 81 #define MTK_PCI_PCIE0_DLECR 0x2060 82 #define MTK_PCI_PCIE0_ECRC 0x2064 83 84 #define MTK_PCIE_BAR0SETUP(_s) (MTK_PCI_PCIE0_BAR0SETUP + (_s)*0x1000) 85 #define MTK_PCIE_BAR1SETUP(_s) (MTK_PCI_PCIE0_BAR1SETUP + (_s)*0x1000) 86 #define MTK_PCIE_IMBASEBAR0(_s) (MTK_PCI_PCIE0_IMBASEBAR0 + (_s)*0x1000) 87 #define MTK_PCIE_ID(_s) (MTK_PCI_PCIE0_ID + (_s)*0x1000) 88 #define MTK_PCIE_CLASS(_s) (MTK_PCI_PCIE0_CLASS + (_s)*0x1000) 89 #define MTK_PCIE_SUBID(_s) (MTK_PCI_PCIE0_SUBID + (_s)*0x1000) 90 #define MTK_PCIE_STATUS(_s) (MTK_PCI_PCIE0_STATUS + (_s)*0x1000) 91 92 #define MTK_PCIE0_IRQ 20 93 #define MTK_PCIE1_IRQ 21 94 #define MTK_PCIE2_IRQ 22 95 96 #define MTK_PCI_INTR_PIN 2 97 98 /* Chip specific defines */ 99 #define MT7620_MAX_RETRIES 10 100 #define MT7620_PCIE_PHY_CFG 0x90 101 #define PHY_BUSY (1<<31) 102 #define PHY_MODE_WRITE (1<<23) 103 #define PHY_ADDR_OFFSET 8 104 #define MT7620_PPLL_CFG0 0x98 105 #define PPLL_SW_SET (1<<31) 106 #define MT7620_PPLL_CFG1 0x9c 107 #define PPLL_PD (1<<26) 108 #define PPLL_LOCKED (1<<23) 109 #define MT7620_PPLL_DRV 0xa0 110 #define PDRV_SW_SET (1<<31) 111 #define LC_CKDRVPD (1<<19) 112 #define LC_CKDRVOHZ (1<<18) 113 #define LC_CKDRVHZ (1<<17) 114 #define MT7620_PERST_GPIO_MODE (3<<16) 115 #define MT7620_PERST (0<<16) 116 #define MT7620_GPIO (2<<16) 117 #define MT7620_PKG_BGA (1<<16) 118 119 #define MT7628_PERST_GPIO_MODE (1<<16) 120 #define MT7628_PERST (0<<16) 121 122 #define MT7621_PERST_GPIO_MODE (3<<10) 123 #define MT7621_PERST_GPIO (1<<10) 124 #define MT7621_UARTL3_GPIO_MODE (3<<3) 125 #define MT7621_UARTL3_GPIO (1<<3) 126 #define MT7621_PCIE0_RST (1<<19) 127 #define MT7621_PCIE1_RST (1<<8) 128 #define MT7621_PCIE2_RST (1<<7) 129 #define MT7621_PCIE_RST (MT7621_PCIE0_RST | MT7621_PCIE1_RST | \ 130 MT7621_PCIE2_RST) 131 132 #define RT3883_PCI_RST (1<<24) 133 #define RT3883_PCI_CLK (1<<19) 134 #define RT3883_PCI_HOST_MODE (1<<7) 135 #define RT3883_PCIE_RC_MODE (1<<8) 136 /* End of chip specific defines */ 137 138 #define MT_WRITE32(sc, off, val) \ 139 bus_write_4((sc)->pci_res[0], (off), (val)) 140 #define MT_WRITE16(sc, off, val) \ 141 bus_write_2((sc)->pci_res[0], (off), (val)) 142 #define MT_WRITE8(sc, off, val) \ 143 bus_write_1((sc)->pci_res[0], (off), (val)) 144 #define MT_READ32(sc, off) \ 145 bus_read_4((sc)->pci_res[0], (off)) 146 #define MT_READ16(sc, off) \ 147 bus_read_2((sc)->pci_res[0], (off)) 148 #define MT_READ8(sc, off) \ 149 bus_read_1((sc)->pci_res[0], (off)) 150 151 #define MT_CLR_SET32(sc, off, clr, set) \ 152 MT_WRITE32((sc), (off), ((MT_READ32((sc), (off)) & ~(clr)) | (off))) 153 154 #endif /* __MTK_PCIE_H__ */ 155