1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * NETLOGIC_BSD */
31
32 /*
33 * Simple driver for the 32-bit interval counter built in to all
34 * MIPS32 CPUs.
35 */
36
37 #include <sys/cdefs.h>
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/sysctl.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/rman.h>
45 #include <sys/power.h>
46 #include <sys/smp.h>
47 #include <sys/time.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
50
51 #include <machine/hwfunc.h>
52 #include <machine/clock.h>
53 #include <machine/locore.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
56
57 #include <mips/nlm/interrupt.h>
58
59 uint64_t counter_freq;
60
61 struct timecounter *platform_timecounter;
62
63 DPCPU_DEFINE_STATIC(uint32_t, cycles_per_tick);
64 static uint32_t cycles_per_usec;
65
66 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_upper);
67 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_lower_last);
68 DPCPU_DEFINE_STATIC(uint32_t, compare_ticks);
69 DPCPU_DEFINE_STATIC(uint32_t, lost_ticks);
70
71 struct clock_softc {
72 int intr_rid;
73 struct resource *intr_res;
74 void *intr_handler;
75 struct timecounter tc;
76 struct eventtimer et;
77 };
78 static struct clock_softc *softc;
79
80 /*
81 * Device methods
82 */
83 static int clock_probe(device_t);
84 static void clock_identify(driver_t *, device_t);
85 static int clock_attach(device_t);
86 static unsigned counter_get_timecount(struct timecounter *tc);
87
88 void
mips_timer_early_init(uint64_t clock_hz)89 mips_timer_early_init(uint64_t clock_hz)
90 {
91 /* Initialize clock early so that we can use DELAY sooner */
92 counter_freq = clock_hz;
93 cycles_per_usec = (clock_hz / (1000 * 1000));
94 }
95
96 void
platform_initclocks(void)97 platform_initclocks(void)
98 {
99
100 if (platform_timecounter != NULL)
101 tc_init(platform_timecounter);
102 }
103
104 static uint64_t
tick_ticker(void)105 tick_ticker(void)
106 {
107 uint64_t ret;
108 uint32_t ticktock;
109 uint32_t t_lower_last, t_upper;
110
111 /*
112 * Disable preemption because we are working with cpu specific data.
113 */
114 critical_enter();
115
116 /*
117 * Note that even though preemption is disabled, interrupts are
118 * still enabled. In particular there is a race with clock_intr()
119 * reading the values of 'counter_upper' and 'counter_lower_last'.
120 *
121 * XXX this depends on clock_intr() being executed periodically
122 * so that 'counter_upper' and 'counter_lower_last' are not stale.
123 */
124 do {
125 t_upper = DPCPU_GET(counter_upper);
126 t_lower_last = DPCPU_GET(counter_lower_last);
127 } while (t_upper != DPCPU_GET(counter_upper));
128
129 ticktock = mips_rd_count();
130
131 critical_exit();
132
133 /* COUNT register wrapped around */
134 if (ticktock < t_lower_last)
135 t_upper++;
136
137 ret = ((uint64_t)t_upper << 32) | ticktock;
138 return (ret);
139 }
140
141 void
mips_timer_init_params(uint64_t platform_counter_freq,int double_count)142 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
143 {
144
145 /*
146 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
147 * function should be called before cninit.
148 */
149 counter_freq = platform_counter_freq;
150 /*
151 * XXX: Some MIPS32 cores update the Count register only every two
152 * pipeline cycles.
153 * We know this because of status registers in CP0, make it automatic.
154 */
155 if (double_count != 0)
156 counter_freq /= 2;
157
158 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
159 set_cputicker(tick_ticker, counter_freq, 1);
160 }
161
162 static int
sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)163 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
164 {
165 int error;
166 uint64_t freq;
167
168 if (softc == NULL)
169 return (EOPNOTSUPP);
170 freq = counter_freq;
171 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
172 if (error == 0 && req->newptr != NULL) {
173 counter_freq = freq;
174 softc->et.et_frequency = counter_freq;
175 softc->tc.tc_frequency = counter_freq;
176 }
177 return (error);
178 }
179
180 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq,
181 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, NULL, 0,
182 sysctl_machdep_counter_freq, "QU",
183 "Timecounter frequency in Hz");
184
185 static unsigned
counter_get_timecount(struct timecounter * tc)186 counter_get_timecount(struct timecounter *tc)
187 {
188
189 return (mips_rd_count());
190 }
191
192 /*
193 * Wait for about n microseconds (at least!).
194 */
195 void
DELAY(int n)196 DELAY(int n)
197 {
198 uint32_t cur, last, delta, usecs;
199
200 TSENTER();
201 /*
202 * This works by polling the timer and counting the number of
203 * microseconds that go by.
204 */
205 last = mips_rd_count();
206 delta = usecs = 0;
207
208 while (n > usecs) {
209 cur = mips_rd_count();
210
211 /* Check to see if the timer has wrapped around. */
212 if (cur < last)
213 delta += cur + (0xffffffff - last) + 1;
214 else
215 delta += cur - last;
216
217 last = cur;
218
219 if (delta >= cycles_per_usec) {
220 usecs += delta / cycles_per_usec;
221 delta %= cycles_per_usec;
222 }
223 }
224 TSEXIT();
225 }
226
227 static int
clock_start(struct eventtimer * et,sbintime_t first,sbintime_t period)228 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
229 {
230 uint32_t fdiv, div, next;
231
232 if (period != 0)
233 div = (et->et_frequency * period) >> 32;
234 else
235 div = 0;
236 if (first != 0)
237 fdiv = (et->et_frequency * first) >> 32;
238 else
239 fdiv = div;
240 DPCPU_SET(cycles_per_tick, div);
241 next = mips_rd_count() + fdiv;
242 DPCPU_SET(compare_ticks, next);
243 mips_wr_compare(next);
244 return (0);
245 }
246
247 static int
clock_stop(struct eventtimer * et)248 clock_stop(struct eventtimer *et)
249 {
250
251 DPCPU_SET(cycles_per_tick, 0);
252 mips_wr_compare(0xffffffff);
253 return (0);
254 }
255
256 /*
257 * Device section of file below
258 */
259 static int
clock_intr(void * arg)260 clock_intr(void *arg)
261 {
262 struct clock_softc *sc = (struct clock_softc *)arg;
263 uint32_t cycles_per_tick;
264 uint32_t count, compare_last, compare_next, lost_ticks;
265
266 cycles_per_tick = DPCPU_GET(cycles_per_tick);
267 /*
268 * Set next clock edge.
269 */
270 count = mips_rd_count();
271 compare_last = DPCPU_GET(compare_ticks);
272 if (cycles_per_tick > 0) {
273 compare_next = count + cycles_per_tick;
274 DPCPU_SET(compare_ticks, compare_next);
275 mips_wr_compare(compare_next);
276 } else /* In one-shot mode timer should be stopped after the event. */
277 mips_wr_compare(0xffffffff);
278
279 /* COUNT register wrapped around */
280 if (count < DPCPU_GET(counter_lower_last)) {
281 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
282 }
283 DPCPU_SET(counter_lower_last, count);
284
285 if (cycles_per_tick > 0) {
286 /*
287 * Account for the "lost time" between when the timer interrupt
288 * fired and when 'clock_intr' actually started executing.
289 */
290 lost_ticks = DPCPU_GET(lost_ticks);
291 lost_ticks += count - compare_last;
292
293 /*
294 * If the COUNT and COMPARE registers are no longer in sync
295 * then make up some reasonable value for the 'lost_ticks'.
296 *
297 * This could happen, for e.g., after we resume normal
298 * operations after exiting the debugger.
299 */
300 if (lost_ticks > 2 * cycles_per_tick)
301 lost_ticks = cycles_per_tick;
302
303 while (lost_ticks >= cycles_per_tick) {
304 if (sc->et.et_active)
305 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
306 lost_ticks -= cycles_per_tick;
307 }
308 DPCPU_SET(lost_ticks, lost_ticks);
309 }
310 if (sc->et.et_active)
311 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
312 return (FILTER_HANDLED);
313 }
314
315 static int
clock_probe(device_t dev)316 clock_probe(device_t dev)
317 {
318
319 device_set_desc(dev, "Generic MIPS32 ticker");
320 return (BUS_PROBE_NOWILDCARD);
321 }
322
323 static void
clock_identify(driver_t * drv,device_t parent)324 clock_identify(driver_t * drv, device_t parent)
325 {
326
327 BUS_ADD_CHILD(parent, 0, "clock", 0);
328 }
329
330 static int
clock_attach(device_t dev)331 clock_attach(device_t dev)
332 {
333 struct clock_softc *sc;
334
335 if (device_get_unit(dev) != 0)
336 panic("can't attach more clocks");
337
338 softc = sc = device_get_softc(dev);
339 cpu_establish_hardintr("compare", clock_intr, NULL,
340 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
341
342 sc->tc.tc_get_timecount = counter_get_timecount;
343 sc->tc.tc_counter_mask = 0xffffffff;
344 sc->tc.tc_frequency = counter_freq;
345 sc->tc.tc_name = "MIPS32";
346 sc->tc.tc_quality = 800;
347 sc->tc.tc_priv = sc;
348 tc_init(&sc->tc);
349 sc->et.et_name = "MIPS32";
350 #if 0
351 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
352 ET_FLAGS_PERCPU;
353 #endif
354 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
355 sc->et.et_quality = 800;
356 sc->et.et_frequency = counter_freq;
357 sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
358 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
359 sc->et.et_start = clock_start;
360 sc->et.et_stop = clock_stop;
361 sc->et.et_priv = sc;
362 et_register(&sc->et);
363 return (0);
364 }
365
366 static device_method_t clock_methods[] = {
367 /* Device interface */
368 DEVMETHOD(device_probe, clock_probe),
369 DEVMETHOD(device_identify, clock_identify),
370 DEVMETHOD(device_attach, clock_attach),
371 DEVMETHOD(device_detach, bus_generic_detach),
372 DEVMETHOD(device_shutdown, bus_generic_shutdown),
373 {0, 0}
374 };
375
376 static driver_t clock_driver = {
377 "clock",
378 clock_methods,
379 sizeof(struct clock_softc),
380 };
381
382 static devclass_t clock_devclass;
383
384 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);
385