1 /*-
2 * Copyright (c) 2017 Justin Hibbits
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/cpu.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/smp.h>
35
36 #include <dev/ofw/ofw_bus.h>
37 #include <dev/ofw/ofw_bus_subr.h>
38
39 #include <machine/cpu.h>
40
41 #include <powerpc/mpc85xx/mpc85xx.h>
42
43 #include "cpufreq_if.h"
44
45 /* No worries about uint32_t math overflow in here, because the highest
46 * multiplier supported is 4, and the highest speed part is still well below
47 * 2GHz.
48 */
49
50 #define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000)
51 #define GUTS_PMJCR (CCSRBAR_VA + 0xe007c)
52 #define PMJCR_RATIO_M 0x3f
53 #define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8)))
54 #define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f)
55 #define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080)
56 #define POWMGTCSR_JOG 0x00200000
57 #define POWMGTCSR_INT_MASK 0x00000f00
58
59 #define MHZ 1000000
60
61 struct mpc85xx_jog_softc {
62 device_t dev;
63 int cpu;
64 int low;
65 int high;
66 int min_freq;
67 };
68
69 static struct ofw_compat_data *mpc85xx_jog_devcompat(void);
70 static void mpc85xx_jog_identify(driver_t *driver, device_t parent);
71 static int mpc85xx_jog_probe(device_t dev);
72 static int mpc85xx_jog_attach(device_t dev);
73 static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count);
74 static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set);
75 static int mpc85xx_jog_get(device_t dev, struct cf_setting *set);
76 static int mpc85xx_jog_type(device_t dev, int *type);
77
78 static device_method_t mpc85xx_jog_methods[] = {
79 /* Device interface */
80 DEVMETHOD(device_identify, mpc85xx_jog_identify),
81 DEVMETHOD(device_probe, mpc85xx_jog_probe),
82 DEVMETHOD(device_attach, mpc85xx_jog_attach),
83
84 /* cpufreq interface */
85 DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set),
86 DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get),
87 DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type),
88 DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings),
89 {0, 0}
90 };
91
92 static driver_t mpc85xx_jog_driver = {
93 "jog",
94 mpc85xx_jog_methods,
95 sizeof(struct mpc85xx_jog_softc)
96 };
97
98 static devclass_t mpc85xx_jog_devclass;
99 DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, mpc85xx_jog_devclass, 0, 0);
100
101 struct mpc85xx_constraints {
102 int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */
103 int min_mult; /* Minimum PLL multiplier. */
104 };
105
106 static struct mpc85xx_constraints mpc8536_constraints = {
107 800,
108 3
109 };
110
111 static struct mpc85xx_constraints p1022_constraints = {
112 500,
113 2
114 };
115
116 static struct ofw_compat_data jog_compat[] = {
117 {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints},
118 {"fsl,p1022-guts", (uintptr_t)&p1022_constraints},
119 {NULL, 0}
120 };
121
122 static struct ofw_compat_data *
mpc85xx_jog_devcompat()123 mpc85xx_jog_devcompat()
124 {
125 phandle_t node;
126 int i;
127
128 node = OF_finddevice("/soc");
129 if (node == -1)
130 return (NULL);
131
132 for (i = 0; jog_compat[i].ocd_str != NULL; i++)
133 if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0)
134 break;
135
136 if (jog_compat[i].ocd_str == NULL)
137 return (NULL);
138
139 return (&jog_compat[i]);
140 }
141
142 static void
mpc85xx_jog_identify(driver_t * driver,device_t parent)143 mpc85xx_jog_identify(driver_t *driver, device_t parent)
144 {
145 struct ofw_compat_data *compat;
146
147 /* Make sure we're not being doubly invoked. */
148 if (device_find_child(parent, "mpc85xx_jog", -1) != NULL)
149 return;
150
151 compat = mpc85xx_jog_devcompat();
152 if (compat == NULL)
153 return;
154
155 /*
156 * We attach a child for every CPU since settings need to
157 * be performed on every CPU in the SMP case.
158 */
159 if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL)
160 device_printf(parent, "add jog child failed\n");
161 }
162
163 static int
mpc85xx_jog_probe(device_t dev)164 mpc85xx_jog_probe(device_t dev)
165 {
166 struct ofw_compat_data *compat;
167
168 compat = mpc85xx_jog_devcompat();
169 if (compat == NULL || compat->ocd_str == NULL)
170 return (ENXIO);
171
172 device_set_desc(dev, "Freescale CPU Jogger");
173 return (0);
174 }
175
176 static int
mpc85xx_jog_attach(device_t dev)177 mpc85xx_jog_attach(device_t dev)
178 {
179 struct ofw_compat_data *compat;
180 struct mpc85xx_jog_softc *sc;
181 struct mpc85xx_constraints *constraints;
182 phandle_t cpu;
183 uint32_t reg;
184
185 sc = device_get_softc(dev);
186 sc->dev = dev;
187
188 compat = mpc85xx_jog_devcompat();
189 constraints = (struct mpc85xx_constraints *)compat->ocd_data;
190 cpu = ofw_bus_get_node(device_get_parent(dev));
191
192 if (cpu <= 0) {
193 device_printf(dev,"No CPU device tree node!\n");
194 return (ENXIO);
195 }
196
197 OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu));
198
199 reg = ccsr_read4(GUTS_PORPLLSR);
200
201 /*
202 * Assume power-on PLL is the highest PLL config supported on the
203 * board.
204 */
205 sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu);
206 sc->min_freq = constraints->threshold;
207 sc->low = constraints->min_mult;
208
209 cpufreq_register(dev);
210 return (0);
211 }
212
213 static int
mpc85xx_jog_settings(device_t dev,struct cf_setting * sets,int * count)214 mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count)
215 {
216 struct mpc85xx_jog_softc *sc;
217 uint32_t sysclk;
218 int i;
219
220 sc = device_get_softc(dev);
221 if (sets == NULL || count == NULL)
222 return (EINVAL);
223 if (*count < sc->high - 1)
224 return (E2BIG);
225
226 sysclk = mpc85xx_get_system_clock();
227 /* Return a list of valid settings for this driver. */
228 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high);
229
230 for (i = sc->high; i >= sc->low; --i) {
231 sets[sc->high - i].freq = sysclk * i / MHZ;
232 sets[sc->high - i].dev = dev;
233 sets[sc->high - i].spec[0] = i;
234 }
235 *count = sc->high - sc->low + 1;
236
237 return (0);
238 }
239
240 struct jog_rv_args {
241 int cpu;
242 int mult;
243 int slow;
244 volatile int inprogress;
245 };
246
247 static void
mpc85xx_jog_set_int(void * arg)248 mpc85xx_jog_set_int(void *arg)
249 {
250 struct jog_rv_args *args = arg;
251 uint32_t reg;
252
253 if (PCPU_GET(cpuid) == args->cpu) {
254 reg = ccsr_read4(GUTS_PMJCR);
255 reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu);
256 reg |= PMJCR_CORE_MULT(args->mult, args->cpu);
257 if (args->slow)
258 reg &= ~(1 << (12 + args->cpu));
259 else
260 reg |= (1 << (12 + args->cpu));
261
262 ccsr_write4(GUTS_PMJCR, reg);
263
264 reg = ccsr_read4(GUTS_POWMGTCSR);
265 reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK;
266 ccsr_write4(GUTS_POWMGTCSR, reg);
267
268 /* Wait for completion */
269 do {
270 DELAY(100);
271 reg = ccsr_read4(GUTS_POWMGTCSR);
272 } while (reg & POWMGTCSR_JOG);
273
274 reg = ccsr_read4(GUTS_POWMGTCSR);
275 ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK);
276 ccsr_read4(GUTS_POWMGTCSR);
277
278 args->inprogress = 0;
279 } else {
280 while (args->inprogress)
281 cpu_spinwait();
282 }
283 }
284
285 static int
mpc85xx_jog_set(device_t dev,const struct cf_setting * set)286 mpc85xx_jog_set(device_t dev, const struct cf_setting *set)
287 {
288 struct mpc85xx_jog_softc *sc;
289 struct jog_rv_args args;
290
291 if (set == NULL)
292 return (EINVAL);
293
294 sc = device_get_softc(dev);
295
296 args.slow = (set->freq <= sc->min_freq);
297 args.mult = set->spec[0];
298 args.cpu = PCPU_GET(cpuid);
299 args.inprogress = 1;
300 smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int,
301 smp_no_rendezvous_barrier, &args);
302
303 return (0);
304 }
305
306 static int
mpc85xx_jog_get(device_t dev,struct cf_setting * set)307 mpc85xx_jog_get(device_t dev, struct cf_setting *set)
308 {
309 struct mpc85xx_jog_softc *sc;
310 uint32_t pmjcr;
311 uint32_t freq;
312
313 if (set == NULL)
314 return (EINVAL);
315
316 sc = device_get_softc(dev);
317 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
318
319 pmjcr = ccsr_read4(GUTS_PORPLLSR);
320 freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu);
321 freq *= mpc85xx_get_system_clock();
322 freq /= MHZ;
323
324 set->freq = freq;
325 set->dev = dev;
326
327 return (0);
328 }
329
330 static int
mpc85xx_jog_type(device_t dev,int * type)331 mpc85xx_jog_type(device_t dev, int *type)
332 {
333
334 if (type == NULL)
335 return (EINVAL);
336
337 *type = CPUFREQ_TYPE_ABSOLUTE;
338 return (0);
339 }
340