1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright 2006-2007 by Juniper Networks.
5 * Copyright 2008 Semihalf.
6 * Copyright 2010 The FreeBSD Foundation
7 * All rights reserved.
8 *
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel
36 */
37
38 #include <sys/cdefs.h>
39 #include <sys/param.h>
40 #include <sys/systm.h>
41 #include <sys/ktr.h>
42 #include <sys/sockio.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/module.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
49 #include <sys/bus.h>
50 #include <sys/lock.h>
51 #include <sys/mutex.h>
52 #include <sys/queue.h>
53 #include <sys/rman.h>
54 #include <sys/endian.h>
55 #include <sys/vmem.h>
56
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59
60 #include <dev/ofw/ofw_pci.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63 #include <dev/ofw/ofwpci.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcib_private.h>
67
68 #include "ofw_bus_if.h"
69 #include "pcib_if.h"
70 #include "pic_if.h"
71
72 #include <machine/resource.h>
73 #include <machine/bus.h>
74 #include <machine/intr_machdep.h>
75
76 #include <powerpc/mpc85xx/mpc85xx.h>
77
78 #define REG_CFG_ADDR 0x0000
79 #define CONFIG_ACCESS_ENABLE 0x80000000
80
81 #define REG_CFG_DATA 0x0004
82 #define REG_INT_ACK 0x0008
83
84 #define REG_PEX_IP_BLK_REV1 0x0bf8
85 #define IP_MJ_M 0x0000ff00
86 #define IP_MJ_S 8
87 #define IP_MN_M 0x000000ff
88 #define IP_MN_S 0
89
90 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
91 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
92 #define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
93 #define REG_POWAR(n) (0x0c10 + 0x20 * (n))
94
95 #define REG_PITAR(n) (0x0e00 - 0x20 * (n))
96 #define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
97 #define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
98 #define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
99 #define PIWAR_EN 0x80000000
100 #define PIWAR_PF 0x40000000
101 #define PIWAR_TRGT_M 0x00f00000
102 #define PIWAR_TRGT_S 20
103 #define PIWAR_TRGT_CCSR 0xe
104 #define PIWAR_TRGT_LOCAL 0xf
105
106 #define REG_PEX_MES_DR 0x0020
107 #define REG_PEX_MES_IER 0x0028
108 #define REG_PEX_ERR_DR 0x0e00
109 #define REG_PEX_ERR_EN 0x0e08
110
111 #define REG_PEX_ERR_DR 0x0e00
112 #define REG_PEX_ERR_DR_ME 0x80000000
113 #define REG_PEX_ERR_DR_PCT 0x800000
114 #define REG_PEX_ERR_DR_PAT 0x400000
115 #define REG_PEX_ERR_DR_PCAC 0x200000
116 #define REG_PEX_ERR_DR_PNM 0x100000
117 #define REG_PEX_ERR_DR_CDNSC 0x80000
118 #define REG_PEX_ERR_DR_CRSNC 0x40000
119 #define REG_PEX_ERR_DR_ICCA 0x20000
120 #define REG_PEX_ERR_DR_IACA 0x10000
121 #define REG_PEX_ERR_DR_CRST 0x8000
122 #define REG_PEX_ERR_DR_MIS 0x4000
123 #define REG_PEX_ERR_DR_IOIS 0x2000
124 #define REG_PEX_ERR_DR_CIS 0x1000
125 #define REG_PEX_ERR_DR_CIEP 0x800
126 #define REG_PEX_ERR_DR_IOIEP 0x400
127 #define REG_PEX_ERR_DR_OAC 0x200
128 #define REG_PEX_ERR_DR_IOIA 0x100
129 #define REG_PEX_ERR_DR_IMBA 0x80
130 #define REG_PEX_ERR_DR_IIOBA 0x40
131 #define REG_PEX_ERR_DR_LDDE 0x20
132 #define REG_PEX_ERR_EN 0x0e08
133
134 #define PCIR_LTSSM 0x404
135 #define LTSSM_STAT_L0 0x16
136
137 #define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
138
139 #define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */
140 #define PCI_SLOT_FIRST 0x1 /* used to be 0x11 but qemu-ppce500 starts from 0x1 */
141
142 struct fsl_pcib_softc {
143 struct ofw_pci_softc pci_sc;
144 device_t sc_dev;
145 struct mtx sc_cfg_mtx;
146 int sc_ip_maj;
147 int sc_ip_min;
148
149 int sc_iomem_target;
150 bus_addr_t sc_iomem_start, sc_iomem_end;
151 int sc_ioport_target;
152 bus_addr_t sc_ioport_start, sc_ioport_end;
153
154 struct resource *sc_res;
155 bus_space_handle_t sc_bsh;
156 bus_space_tag_t sc_bst;
157 int sc_rid;
158
159 struct resource *sc_irq_res;
160 void *sc_ih;
161
162 int sc_busnr;
163 int sc_pcie;
164 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */
165 };
166
167 struct fsl_pcib_err_dr {
168 const char *msg;
169 uint32_t err_dr_mask;
170 };
171
172 struct fsl_msi_map {
173 SLIST_ENTRY(fsl_msi_map) slist;
174 uint32_t irq_base;
175 bus_addr_t target;
176 };
177
178 SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head);
179
180 static const struct fsl_pcib_err_dr pci_err[] = {
181 {"ME", REG_PEX_ERR_DR_ME},
182 {"PCT", REG_PEX_ERR_DR_PCT},
183 {"PAT", REG_PEX_ERR_DR_PAT},
184 {"PCAC", REG_PEX_ERR_DR_PCAC},
185 {"PNM", REG_PEX_ERR_DR_PNM},
186 {"CDNSC", REG_PEX_ERR_DR_CDNSC},
187 {"CRSNC", REG_PEX_ERR_DR_CRSNC},
188 {"ICCA", REG_PEX_ERR_DR_ICCA},
189 {"IACA", REG_PEX_ERR_DR_IACA},
190 {"CRST", REG_PEX_ERR_DR_CRST},
191 {"MIS", REG_PEX_ERR_DR_MIS},
192 {"IOIS", REG_PEX_ERR_DR_IOIS},
193 {"CIS", REG_PEX_ERR_DR_CIS},
194 {"CIEP", REG_PEX_ERR_DR_CIEP},
195 {"IOIEP", REG_PEX_ERR_DR_IOIEP},
196 {"OAC", REG_PEX_ERR_DR_OAC},
197 {"IOIA", REG_PEX_ERR_DR_IOIA},
198 {"IMBA", REG_PEX_ERR_DR_IMBA},
199 {"IIOBA", REG_PEX_ERR_DR_IIOBA},
200 {"LDDE", REG_PEX_ERR_DR_LDDE}
201 };
202
203 /* Local forward declerations. */
204 static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int,
205 u_int, int);
206 static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int,
207 u_int, uint32_t, int);
208 static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *);
209 static void fsl_pcib_err_init(device_t);
210 static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, uint64_t,
211 uint64_t, uint64_t);
212 static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, uint64_t,
213 uint64_t, uint64_t);
214
215 /* Forward declerations. */
216 static int fsl_pcib_attach(device_t);
217 static int fsl_pcib_detach(device_t);
218 static int fsl_pcib_probe(device_t);
219
220 static int fsl_pcib_maxslots(device_t);
221 static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
222 static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
223 uint32_t, int);
224 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
225 int count, int maxcount, int *irqs);
226 static int fsl_pcib_release_msi(device_t dev, device_t child,
227 int count, int *irqs);
228 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq);
229 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq);
230 static int fsl_pcib_map_msi(device_t dev, device_t child,
231 int irq, uint64_t *addr, uint32_t *data);
232
233 static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */
234
235 /*
236 * Bus interface definitions.
237 */
238 static device_method_t fsl_pcib_methods[] = {
239 /* Device interface */
240 DEVMETHOD(device_probe, fsl_pcib_probe),
241 DEVMETHOD(device_attach, fsl_pcib_attach),
242 DEVMETHOD(device_detach, fsl_pcib_detach),
243
244 /* pcib interface */
245 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
246 DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
247 DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
248 DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi),
249 DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi),
250 DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix),
251 DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix),
252 DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi),
253
254 DEVMETHOD_END
255 };
256
257 static devclass_t fsl_pcib_devclass;
258
259 DEFINE_CLASS_1(pcib, fsl_pcib_driver, fsl_pcib_methods,
260 sizeof(struct fsl_pcib_softc), ofw_pci_driver);
261 EARLY_DRIVER_MODULE(pcib, ofwbus, fsl_pcib_driver, fsl_pcib_devclass, 0, 0,
262 BUS_PASS_BUS);
263
264 static void
fsl_pcib_err_intr(void * v)265 fsl_pcib_err_intr(void *v)
266 {
267 struct fsl_pcib_softc *sc;
268 device_t dev;
269 uint32_t err_reg, clear_reg;
270 uint8_t i;
271
272 dev = (device_t)v;
273 sc = device_get_softc(dev);
274
275 clear_reg = 0;
276 err_reg = bus_space_read_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR);
277
278 /* Check which one error occurred */
279 for (i = 0; i < sizeof(pci_err)/sizeof(struct fsl_pcib_err_dr); i++) {
280 if (err_reg & pci_err[i].err_dr_mask) {
281 device_printf(dev, "PCI %d: report %s error\n",
282 device_get_unit(dev), pci_err[i].msg);
283 clear_reg |= pci_err[i].err_dr_mask;
284 }
285 }
286
287 /* Clear pending errors */
288 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, clear_reg);
289 }
290
291 static int
fsl_pcib_probe(device_t dev)292 fsl_pcib_probe(device_t dev)
293 {
294
295 if (ofw_bus_get_type(dev) == NULL ||
296 strcmp(ofw_bus_get_type(dev), "pci") != 0)
297 return (ENXIO);
298
299 if (!(ofw_bus_is_compatible(dev, "fsl,mpc8540-pci") ||
300 ofw_bus_is_compatible(dev, "fsl,mpc8540-pcie") ||
301 ofw_bus_is_compatible(dev, "fsl,mpc8548-pcie") ||
302 ofw_bus_is_compatible(dev, "fsl,p5020-pcie") ||
303 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie-v2.2") ||
304 ofw_bus_is_compatible(dev, "fsl,qoriq-pcie")))
305 return (ENXIO);
306
307 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller");
308 return (BUS_PROBE_DEFAULT);
309 }
310
311 static int
fsl_pcib_attach(device_t dev)312 fsl_pcib_attach(device_t dev)
313 {
314 struct fsl_pcib_softc *sc;
315 phandle_t node;
316 uint32_t cfgreg, brctl, ipreg;
317 int error, rid;
318 uint8_t ltssm, capptr;
319
320 sc = device_get_softc(dev);
321 sc->sc_dev = dev;
322
323 sc->sc_rid = 0;
324 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
325 RF_ACTIVE);
326 if (sc->sc_res == NULL) {
327 device_printf(dev, "could not map I/O memory\n");
328 return (ENXIO);
329 }
330 sc->sc_bst = rman_get_bustag(sc->sc_res);
331 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
332 sc->sc_busnr = 0;
333
334 ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);
335 sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;
336 sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;
337 mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
338
339 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
340 if (cfgreg != 0x1057 && cfgreg != 0x1957)
341 goto err;
342
343 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1);
344 while (capptr != 0) {
345 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2);
346 switch (cfgreg & 0xff) {
347 case PCIY_PCIX:
348 break;
349 case PCIY_EXPRESS:
350 sc->sc_pcie = 1;
351 sc->sc_pcie_capreg = capptr;
352 break;
353 }
354 capptr = (cfgreg >> 8) & 0xff;
355 }
356
357 node = ofw_bus_get_node(dev);
358
359 /*
360 * Initialize generic OF PCI interface (ranges, etc.)
361 */
362
363 error = ofw_pci_init(dev);
364 if (error)
365 return (error);
366
367 /*
368 * Configure decode windows for PCI(E) access.
369 */
370 if (fsl_pcib_decode_win(node, sc) != 0)
371 goto err;
372
373 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2);
374 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
375 PCIM_CMD_PORTEN;
376 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2);
377
378 /* Reset the bus. Needed for Radeon video cards. */
379 brctl = fsl_pcib_read_config(sc->sc_dev, 0, 0, 0,
380 PCIR_BRIDGECTL_1, 1);
381 brctl |= PCIB_BCR_SECBUS_RESET;
382 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
383 PCIR_BRIDGECTL_1, brctl, 1);
384 DELAY(100000);
385 brctl &= ~PCIB_BCR_SECBUS_RESET;
386 fsl_pcib_write_config(sc->sc_dev, 0, 0, 0,
387 PCIR_BRIDGECTL_1, brctl, 1);
388 DELAY(100000);
389
390 if (sc->sc_pcie) {
391 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1);
392 if (ltssm < LTSSM_STAT_L0) {
393 if (bootverbose)
394 printf("PCI %d: no PCIE link, skipping\n",
395 device_get_unit(dev));
396 return (0);
397 }
398 }
399
400 /* Allocate irq */
401 rid = 0;
402 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
403 RF_ACTIVE | RF_SHAREABLE);
404 if (sc->sc_irq_res == NULL) {
405 error = fsl_pcib_detach(dev);
406 if (error != 0) {
407 device_printf(dev,
408 "Detach of the driver failed with error %d\n",
409 error);
410 }
411 return (ENXIO);
412 }
413
414 /* Setup interrupt handler */
415 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
416 NULL, fsl_pcib_err_intr, dev, &sc->sc_ih);
417 if (error != 0) {
418 device_printf(dev, "Could not setup irq, %d\n", error);
419 sc->sc_ih = NULL;
420 error = fsl_pcib_detach(dev);
421 if (error != 0) {
422 device_printf(dev,
423 "Detach of the driver failed with error %d\n",
424 error);
425 }
426 return (ENXIO);
427 }
428
429 fsl_pcib_err_init(dev);
430
431 return (ofw_pci_attach(dev));
432
433 err:
434 return (ENXIO);
435 }
436
437 static uint32_t
fsl_pcib_cfgread(struct fsl_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,int bytes)438 fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
439 u_int reg, int bytes)
440 {
441 uint32_t addr, data;
442
443 addr = CONFIG_ACCESS_ENABLE;
444 addr |= (bus & 0xff) << 16;
445 addr |= (slot & 0x1f) << 11;
446 addr |= (func & 0x7) << 8;
447 addr |= reg & 0xfc;
448 if (sc->sc_pcie)
449 addr |= (reg & 0xf00) << 16;
450
451 mtx_lock_spin(&sc->sc_cfg_mtx);
452 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
453
454 switch (bytes) {
455 case 1:
456 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
457 REG_CFG_DATA + (reg & 3));
458 break;
459 case 2:
460 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
461 REG_CFG_DATA + (reg & 2)));
462 break;
463 case 4:
464 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
465 REG_CFG_DATA));
466 break;
467 default:
468 data = ~0;
469 break;
470 }
471 mtx_unlock_spin(&sc->sc_cfg_mtx);
472 return (data);
473 }
474
475 static void
fsl_pcib_cfgwrite(struct fsl_pcib_softc * sc,u_int bus,u_int slot,u_int func,u_int reg,uint32_t data,int bytes)476 fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func,
477 u_int reg, uint32_t data, int bytes)
478 {
479 uint32_t addr;
480
481 addr = CONFIG_ACCESS_ENABLE;
482 addr |= (bus & 0xff) << 16;
483 addr |= (slot & 0x1f) << 11;
484 addr |= (func & 0x7) << 8;
485 addr |= reg & 0xfc;
486 if (sc->sc_pcie)
487 addr |= (reg & 0xf00) << 16;
488
489 mtx_lock_spin(&sc->sc_cfg_mtx);
490 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr);
491
492 switch (bytes) {
493 case 1:
494 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
495 REG_CFG_DATA + (reg & 3), data);
496 break;
497 case 2:
498 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
499 REG_CFG_DATA + (reg & 2), htole16(data));
500 break;
501 case 4:
502 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
503 REG_CFG_DATA, htole32(data));
504 break;
505 }
506 mtx_unlock_spin(&sc->sc_cfg_mtx);
507 }
508
509 #if 0
510 static void
511 dump(struct fsl_pcib_softc *sc)
512 {
513 unsigned int i;
514
515 #define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o)
516 for (i = 0; i < 5; i++) {
517 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i)));
518 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i)));
519 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i)));
520 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i)));
521 }
522 printf("\n");
523 for (i = 1; i < 4; i++) {
524 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i)));
525 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i)));
526 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i)));
527 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i)));
528 }
529 printf("\n");
530 #undef RD
531
532 for (i = 0; i < 0x48; i += 4) {
533 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0,
534 i, 4));
535 }
536 }
537 #endif
538
539 static int
fsl_pcib_maxslots(device_t dev)540 fsl_pcib_maxslots(device_t dev)
541 {
542 struct fsl_pcib_softc *sc = device_get_softc(dev);
543
544 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX);
545 }
546
547 static uint32_t
fsl_pcib_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int bytes)548 fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
549 u_int reg, int bytes)
550 {
551 struct fsl_pcib_softc *sc = device_get_softc(dev);
552 u_int devfn;
553
554 if (bus == sc->sc_busnr && !sc->sc_pcie &&
555 slot < PCI_SLOT_FIRST)
556 return (~0);
557 devfn = DEVFN(bus, slot, func);
558
559 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes));
560 }
561
562 static void
fsl_pcib_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int bytes)563 fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
564 u_int reg, uint32_t val, int bytes)
565 {
566 struct fsl_pcib_softc *sc = device_get_softc(dev);
567
568 if (bus == sc->sc_busnr && !sc->sc_pcie &&
569 slot < PCI_SLOT_FIRST)
570 return;
571 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes);
572 }
573
574 static void
fsl_pcib_inbound(struct fsl_pcib_softc * sc,int wnd,int tgt,uint64_t start,uint64_t size,uint64_t pci_start)575 fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
576 uint64_t size, uint64_t pci_start)
577 {
578 uint32_t attr, bar, tar;
579
580 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
581
582 attr = PIWAR_EN;
583
584 switch (tgt) {
585 case -1:
586 attr &= ~PIWAR_EN;
587 break;
588 case PIWAR_TRGT_LOCAL:
589 attr |= (ffsl(size) - 2);
590 default:
591 attr |= (tgt << PIWAR_TRGT_S);
592 break;
593 }
594 tar = start >> 12;
595 bar = pci_start >> 12;
596
597 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar);
598 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0);
599 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar);
600 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr);
601 }
602
603 static void
fsl_pcib_outbound(struct fsl_pcib_softc * sc,int wnd,int res,uint64_t start,uint64_t size,uint64_t pci_start)604 fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, uint64_t start,
605 uint64_t size, uint64_t pci_start)
606 {
607 uint32_t attr, bar, tar;
608
609 switch (res) {
610 case SYS_RES_MEMORY:
611 attr = 0x80044000 | (ffsll(size) - 2);
612 break;
613 case SYS_RES_IOPORT:
614 attr = 0x80088000 | (ffsll(size) - 2);
615 break;
616 default:
617 attr = 0x0004401f;
618 break;
619 }
620 bar = start >> 12;
621 tar = pci_start >> 12;
622
623 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar);
624 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0);
625 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar);
626 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr);
627 }
628
629 static void
fsl_pcib_err_init(device_t dev)630 fsl_pcib_err_init(device_t dev)
631 {
632 struct fsl_pcib_softc *sc;
633 uint16_t sec_stat, dsr;
634 uint32_t dcr, err_en;
635
636 sc = device_get_softc(dev);
637
638 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2);
639 if (sec_stat)
640 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2);
641 if (sc->sc_pcie) {
642 /* Clear error bits */
643 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER,
644 0xffffffff);
645 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR,
646 0xffffffff);
647 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR,
648 0xffffffff);
649
650 dsr = fsl_pcib_cfgread(sc, 0, 0, 0,
651 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2);
652 if (dsr)
653 fsl_pcib_cfgwrite(sc, 0, 0, 0,
654 sc->sc_pcie_capreg + PCIER_DEVICE_STA,
655 0xffff, 2);
656
657 /* Enable all errors reporting */
658 err_en = 0x00bfff00;
659 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN,
660 err_en);
661
662 /* Enable error reporting: URR, FER, NFER */
663 dcr = fsl_pcib_cfgread(sc, 0, 0, 0,
664 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4);
665 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE |
666 PCIEM_CTL_NFER_ENABLE;
667 fsl_pcib_cfgwrite(sc, 0, 0, 0,
668 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4);
669 }
670 }
671
672 static int
fsl_pcib_detach(device_t dev)673 fsl_pcib_detach(device_t dev)
674 {
675 struct fsl_pcib_softc *sc;
676
677 sc = device_get_softc(dev);
678
679 mtx_destroy(&sc->sc_cfg_mtx);
680
681 return (bus_generic_detach(dev));
682 }
683
684 static int
fsl_pcib_decode_win(phandle_t node,struct fsl_pcib_softc * sc)685 fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
686 {
687 device_t dev;
688 int error, i, trgt;
689
690 dev = sc->sc_dev;
691
692 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0);
693
694 /*
695 * Configure LAW decode windows.
696 */
697 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target,
698 &sc->sc_ioport_target);
699 if (error != 0) {
700 device_printf(dev, "could not retrieve PCI LAW target info\n");
701 return (error);
702 }
703
704 for (i = 0; i < sc->pci_sc.sc_nrange; i++) {
705 switch (sc->pci_sc.sc_range[i].pci_hi &
706 OFW_PCI_PHYS_HI_SPACEMASK) {
707 case OFW_PCI_PHYS_HI_SPACE_CONFIG:
708 continue;
709 case OFW_PCI_PHYS_HI_SPACE_IO:
710 trgt = sc->sc_ioport_target;
711 fsl_pcib_outbound(sc, 2, SYS_RES_IOPORT,
712 sc->pci_sc.sc_range[i].host,
713 sc->pci_sc.sc_range[i].size,
714 sc->pci_sc.sc_range[i].pci);
715 sc->sc_ioport_start = sc->pci_sc.sc_range[i].pci;
716 sc->sc_ioport_end = sc->pci_sc.sc_range[i].pci +
717 sc->pci_sc.sc_range[i].size - 1;
718 break;
719 case OFW_PCI_PHYS_HI_SPACE_MEM32:
720 case OFW_PCI_PHYS_HI_SPACE_MEM64:
721 trgt = sc->sc_iomem_target;
722 fsl_pcib_outbound(sc, 1, SYS_RES_MEMORY,
723 sc->pci_sc.sc_range[i].host,
724 sc->pci_sc.sc_range[i].size,
725 sc->pci_sc.sc_range[i].pci);
726 sc->sc_iomem_start = sc->pci_sc.sc_range[i].pci;
727 sc->sc_iomem_end = sc->pci_sc.sc_range[i].pci +
728 sc->pci_sc.sc_range[i].size - 1;
729 break;
730 default:
731 panic("Unknown range type %#x\n",
732 sc->pci_sc.sc_range[i].pci_hi &
733 OFW_PCI_PHYS_HI_SPACEMASK);
734 }
735 error = law_enable(trgt, sc->pci_sc.sc_range[i].host,
736 sc->pci_sc.sc_range[i].size);
737 if (error != 0) {
738 device_printf(dev, "could not program LAW for range "
739 "%d\n", i);
740 return (error);
741 }
742 }
743
744 /*
745 * Set outbout and inbound windows.
746 */
747 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0);
748 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0);
749
750 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
751 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
752 fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0,
753 ptoa(Maxmem), 0);
754
755 /* Direct-map the CCSR for MSIs. */
756 /* Freescale PCIe 2.x has a dedicated MSI window. */
757 /* inbound window 8 makes it hit 0xD00 offset, the MSI window. */
758 if (sc->sc_ip_maj >= 2)
759 fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa,
760 ccsrbar_size, ccsrbar_pa);
761 else
762 fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa,
763 ccsrbar_size, ccsrbar_pa);
764
765 return (0);
766 }
767
fsl_pcib_alloc_msi(device_t dev,device_t child,int count,int maxcount,int * irqs)768 static int fsl_pcib_alloc_msi(device_t dev, device_t child,
769 int count, int maxcount, int *irqs)
770 {
771 struct fsl_pcib_softc *sc;
772 vmem_addr_t start;
773 int err, i;
774
775 sc = device_get_softc(dev);
776 if (msi_vmem == NULL)
777 return (ENODEV);
778
779 err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0,
780 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
781
782 if (err)
783 return (err);
784
785 for (i = 0; i < count; i++)
786 irqs[i] = start + i;
787
788 return (0);
789 }
790
fsl_pcib_release_msi(device_t dev,device_t child,int count,int * irqs)791 static int fsl_pcib_release_msi(device_t dev, device_t child,
792 int count, int *irqs)
793 {
794 if (msi_vmem == NULL)
795 return (ENODEV);
796
797 vmem_xfree(msi_vmem, irqs[0], count);
798 return (0);
799 }
800
fsl_pcib_alloc_msix(device_t dev,device_t child,int * irq)801 static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq)
802 {
803 return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq));
804 }
805
fsl_pcib_release_msix(device_t dev,device_t child,int irq)806 static int fsl_pcib_release_msix(device_t dev, device_t child, int irq)
807 {
808 return (fsl_pcib_release_msi(dev, child, 1, &irq));
809 }
810
fsl_pcib_map_msi(device_t dev,device_t child,int irq,uint64_t * addr,uint32_t * data)811 static int fsl_pcib_map_msi(device_t dev, device_t child,
812 int irq, uint64_t *addr, uint32_t *data)
813 {
814 struct fsl_msi_map *mp;
815
816 SLIST_FOREACH(mp, &fsl_msis, slist) {
817 if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)
818 break;
819 }
820
821 if (mp == NULL)
822 return (ENODEV);
823
824 *data = (irq & 255);
825 *addr = ccsrbar_pa + mp->target;
826
827 return (0);
828 }
829
830 /*
831 * Linux device trees put the msi@<x> as children of the SoC, with ranges based
832 * on the CCSR. Since rman doesn't permit overlapping or sub-ranges between
833 * devices (bus_space_subregion(9) could do it, but let's not touch the PIC
834 * driver just to allocate a subregion for a sibling driver). This driver will
835 * use ccsr_write() and ccsr_read() instead.
836 */
837
838 #define FSL_NUM_IRQS 8
839 #define FSL_NUM_MSI_PER_IRQ 32
840 #define FSL_MSI_TARGET 0x140
841
842 struct fsl_msi_softc {
843 vm_offset_t sc_base;
844 vm_offset_t sc_target;
845 int sc_msi_base_irq;
846 struct fsl_msi_map sc_map;
847 struct fsl_msi_irq {
848 /* This struct gets passed as the filter private data. */
849 struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */
850 struct resource *res;
851 int irq;
852 void *cookie;
853 int vectors[FSL_NUM_MSI_PER_IRQ];
854 vm_offset_t reg;
855 } sc_msi_irq[FSL_NUM_IRQS];
856 };
857
858 static int
fsl_msi_intr_filter(void * priv)859 fsl_msi_intr_filter(void *priv)
860 {
861 struct fsl_msi_irq *data = priv;
862 uint32_t reg;
863 int i;
864
865 reg = ccsr_read4(ccsrbar_va + data->reg);
866 i = 0;
867 while (reg != 0) {
868 if (reg & 1)
869 powerpc_dispatch_intr(data->vectors[i], NULL);
870 reg >>= 1;
871 i++;
872 }
873
874 return (FILTER_HANDLED);
875 }
876
877 static int
fsl_msi_probe(device_t dev)878 fsl_msi_probe(device_t dev)
879 {
880 if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))
881 return (ENXIO);
882
883 device_set_desc(dev, "Freescale MSI");
884
885 return (BUS_PROBE_DEFAULT);
886 }
887
888 static int
fsl_msi_attach(device_t dev)889 fsl_msi_attach(device_t dev)
890 {
891 struct fsl_msi_softc *sc;
892 struct fsl_msi_irq *irq;
893 int i;
894
895 sc = device_get_softc(dev);
896
897 if (msi_vmem == NULL)
898 msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 0, M_BESTFIT | M_WAITOK);
899
900 /* Manually play with resource entries. */
901 sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
902 sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);
903
904 if (sc->sc_map.target == 0)
905 sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;
906
907 for (i = 0; i < FSL_NUM_IRQS; i++) {
908 irq = &sc->sc_msi_irq[i];
909 irq->irq = i;
910 irq->reg = sc->sc_base + 16 * i;
911 irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
912 &irq->irq, RF_ACTIVE);
913 bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,
914 fsl_msi_intr_filter, NULL, irq, &irq->cookie);
915 }
916 sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),
917 FSL_NUM_MSIS, 0, 0);
918
919 /* Let vmem and the IRQ subsystem work their magic for allocations. */
920 vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);
921
922 SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);
923
924 return (0);
925 }
926
927 static void
fsl_msi_enable(device_t dev,u_int irq,u_int vector,void ** priv)928 fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv)
929 {
930 struct fsl_msi_softc *sc;
931 struct fsl_msi_irq *irqd;
932
933 sc = device_get_softc(dev);
934
935 irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];
936 irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;
937 }
938
939 static device_method_t fsl_msi_methods[] = {
940 DEVMETHOD(device_probe, fsl_msi_probe),
941 DEVMETHOD(device_attach, fsl_msi_attach),
942
943 DEVMETHOD(pic_enable, fsl_msi_enable),
944 DEVMETHOD_END
945 };
946
947 static devclass_t fsl_msi_devclass;
948
949 static driver_t fsl_msi_driver = {
950 "fsl_msi",
951 fsl_msi_methods,
952 sizeof(struct fsl_msi_softc)
953 };
954
955 EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, fsl_msi_devclass, 0, 0,
956 BUS_PASS_INTERRUPT + 1);
957