1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2002 Benno Rice.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/rman.h>
38
39 #include <dev/ofw/openfirm.h>
40 #include <dev/ofw/ofw_pci.h>
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43 #include <dev/ofw/ofwpci.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/pio.h>
52 #include <machine/resource.h>
53
54 #include <powerpc/powermac/uninorthvar.h>
55
56 #include <vm/vm.h>
57 #include <vm/pmap.h>
58
59 #include "pcib_if.h"
60
61 #define UNINORTH_DEBUG 0
62
63 /*
64 * Device interface.
65 */
66 static int uninorth_probe(device_t);
67 static int uninorth_attach(device_t);
68
69 /*
70 * pcib interface.
71 */
72 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
73 u_int, int);
74 static void uninorth_write_config(device_t, u_int, u_int, u_int,
75 u_int, u_int32_t, int);
76
77 /*
78 * Local routines.
79 */
80 static int uninorth_enable_config(struct uninorth_softc *, u_int,
81 u_int, u_int, u_int);
82
83 /*
84 * Driver methods.
85 */
86 static device_method_t uninorth_methods[] = {
87 /* Device interface */
88 DEVMETHOD(device_probe, uninorth_probe),
89 DEVMETHOD(device_attach, uninorth_attach),
90
91 /* pcib interface */
92 DEVMETHOD(pcib_read_config, uninorth_read_config),
93 DEVMETHOD(pcib_write_config, uninorth_write_config),
94
95 DEVMETHOD_END
96 };
97
98 static devclass_t uninorth_devclass;
99
100 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
101 sizeof(struct uninorth_softc), ofw_pci_driver);
102 EARLY_DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0,
103 BUS_PASS_BUS);
104
105 static int
uninorth_probe(device_t dev)106 uninorth_probe(device_t dev)
107 {
108 const char *type, *compatible;
109
110 type = ofw_bus_get_type(dev);
111 compatible = ofw_bus_get_compat(dev);
112
113 if (type == NULL || compatible == NULL)
114 return (ENXIO);
115
116 if (strcmp(type, "pci") != 0)
117 return (ENXIO);
118
119 if (strcmp(compatible, "uni-north") == 0) {
120 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
121 return (0);
122 } else if (strcmp(compatible, "u3-agp") == 0) {
123 device_set_desc(dev, "Apple U3 Host-AGP bridge");
124 return (0);
125 } else if (strcmp(compatible, "u4-pcie") == 0) {
126 device_set_desc(dev, "IBM CPC945 PCI Express Root");
127 return (0);
128 }
129
130 return (ENXIO);
131 }
132
133 static int
uninorth_attach(device_t dev)134 uninorth_attach(device_t dev)
135 {
136 struct uninorth_softc *sc;
137 const char *compatible;
138 const char *name;
139 phandle_t node;
140 uint32_t reg[3];
141 uint64_t regbase;
142 cell_t acells;
143 int unit;
144
145 node = ofw_bus_get_node(dev);
146 sc = device_get_softc(dev);
147 name = device_get_name(dev);
148 unit = device_get_unit(dev);
149
150 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
151 return (ENXIO);
152
153 sc->sc_ver = 0;
154 compatible = ofw_bus_get_compat(dev);
155 if (strcmp(compatible, "u3-agp") == 0)
156 sc->sc_ver = 3;
157 if (strcmp(compatible, "u4-pcie") == 0)
158 sc->sc_ver = 4;
159
160 acells = 1;
161 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells));
162
163 regbase = reg[0];
164 if (acells == 2) {
165 regbase <<= 32;
166 regbase |= reg[1];
167 }
168
169 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE);
170 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE);
171
172 if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0)
173 sc->sc_skipslot = -1;
174
175 mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN);
176
177 return (ofw_pci_attach(dev));
178 }
179
180 static u_int32_t
uninorth_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)181 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
182 int width)
183 {
184 struct uninorth_softc *sc;
185 vm_offset_t caoff;
186 u_int32_t val;
187
188 sc = device_get_softc(dev);
189 caoff = sc->sc_data + (reg & 0x07);
190 val = 0xffffffff;
191
192 mtx_lock_spin(&sc->sc_cfg_mtx);
193 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
194 switch (width) {
195 case 1:
196 val = in8rb(caoff);
197 break;
198 case 2:
199 val = in16rb(caoff);
200 break;
201 case 4:
202 val = in32rb(caoff);
203 break;
204 }
205 }
206 mtx_unlock_spin(&sc->sc_cfg_mtx);
207
208 return (val);
209 }
210
211 static void
uninorth_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,u_int32_t val,int width)212 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
213 u_int reg, u_int32_t val, int width)
214 {
215 struct uninorth_softc *sc;
216 vm_offset_t caoff;
217
218 sc = device_get_softc(dev);
219 caoff = sc->sc_data + (reg & 0x07);
220
221 mtx_lock_spin(&sc->sc_cfg_mtx);
222 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
223 switch (width) {
224 case 1:
225 out8rb(caoff, val);
226 break;
227 case 2:
228 out16rb(caoff, val);
229 break;
230 case 4:
231 out32rb(caoff, val);
232 break;
233 }
234 }
235 mtx_unlock_spin(&sc->sc_cfg_mtx);
236 }
237
238 static int
uninorth_enable_config(struct uninorth_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)239 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
240 u_int func, u_int reg)
241 {
242 uint32_t cfgval;
243
244 mtx_assert(&sc->sc_cfg_mtx, MA_OWNED);
245
246 if (sc->sc_skipslot == slot)
247 return (0);
248
249 /*
250 * Issue type 0 configuration space accesses for the root bus.
251 *
252 * NOTE: On U4, issue only type 1 accesses. There is a secret
253 * PCI Express <-> PCI Express bridge not present in the device tree,
254 * and we need to route all of our configuration space through it.
255 */
256 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
257 /*
258 * No slots less than 11 on the primary bus on U3 and lower
259 */
260 if (slot < 11)
261 return (0);
262
263 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
264 } else {
265 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
266 (reg & 0xfc) | 1;
267 }
268
269 /* Set extended register bits on U4 */
270 if (sc->sc_ver == 4)
271 cfgval |= (reg >> 8) << 28;
272
273 do {
274 out32rb(sc->sc_addr, cfgval);
275 } while (in32rb(sc->sc_addr) != cfgval);
276
277 return (1);
278 }
279