1 /*-
2 * Copyright (c) 2015-2016 Nathan Whitehorn
3 * Copyright (c) 2017-2018 Semihalf
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35 #include <sys/pciio.h>
36 #include <sys/endian.h>
37 #include <sys/rman.h>
38 #include <sys/vmem.h>
39
40 #include <dev/ofw/openfirm.h>
41 #include <dev/ofw/ofw_pci.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44 #include <dev/ofw/ofwpci.h>
45
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48
49 #include <machine/bus.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52
53 #include <vm/vm.h>
54 #include <vm/pmap.h>
55
56 #include "pcib_if.h"
57 #include "pic_if.h"
58 #include "iommu_if.h"
59 #include "opal.h"
60
61 #define OPAL_PCI_TCE_MAX_ENTRIES (1024*1024UL)
62 #define OPAL_PCI_TCE_DEFAULT_SEG_SIZE (16*1024*1024UL)
63 #define OPAL_PCI_TCE_R (1UL << 0)
64 #define OPAL_PCI_TCE_W (1UL << 1)
65 #define PHB3_TCE_KILL_INVAL_ALL (1UL << 63)
66
67 /*
68 * Device interface.
69 */
70 static int opalpci_probe(device_t);
71 static int opalpci_attach(device_t);
72
73 /*
74 * pcib interface.
75 */
76 static uint32_t opalpci_read_config(device_t, u_int, u_int, u_int,
77 u_int, int);
78 static void opalpci_write_config(device_t, u_int, u_int, u_int,
79 u_int, u_int32_t, int);
80 static int opalpci_alloc_msi(device_t dev, device_t child,
81 int count, int maxcount, int *irqs);
82 static int opalpci_release_msi(device_t dev, device_t child,
83 int count, int *irqs);
84 static int opalpci_alloc_msix(device_t dev, device_t child,
85 int *irq);
86 static int opalpci_release_msix(device_t dev, device_t child,
87 int irq);
88 static int opalpci_map_msi(device_t dev, device_t child,
89 int irq, uint64_t *addr, uint32_t *data);
90 static int opalpci_route_interrupt(device_t bus, device_t dev, int pin);
91
92 /*
93 * MSI PIC interface.
94 */
95 static void opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **);
96 static void opalpic_pic_eoi(device_t dev, u_int irq, void *);
97
98 /* Bus interface */
99 static bus_dma_tag_t opalpci_get_dma_tag(device_t dev, device_t child);
100
101 /*
102 * Commands
103 */
104 #define OPAL_M32_WINDOW_TYPE 1
105 #define OPAL_M64_WINDOW_TYPE 2
106 #define OPAL_IO_WINDOW_TYPE 3
107
108 #define OPAL_RESET_PHB_COMPLETE 1
109 #define OPAL_RESET_PCI_IODA_TABLE 6
110
111 #define OPAL_DISABLE_M64 0
112 #define OPAL_ENABLE_M64_SPLIT 1
113 #define OPAL_ENABLE_M64_NON_SPLIT 2
114
115 #define OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO 1
116 #define OPAL_EEH_ACTION_CLEAR_FREEZE_DMA 2
117 #define OPAL_EEH_ACTION_CLEAR_FREEZE_ALL 3
118
119 #define OPAL_EEH_STOPPED_NOT_FROZEN 0
120
121 /*
122 * Constants
123 */
124 #define OPAL_PCI_DEFAULT_PE 1
125
126 #define OPAL_PCI_BUS_SPACE_LOWADDR_32BIT 0x7FFFFFFFUL
127
128 /*
129 * Driver methods.
130 */
131 static device_method_t opalpci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, opalpci_probe),
134 DEVMETHOD(device_attach, opalpci_attach),
135
136 /* pcib interface */
137 DEVMETHOD(pcib_read_config, opalpci_read_config),
138 DEVMETHOD(pcib_write_config, opalpci_write_config),
139
140 DEVMETHOD(pcib_alloc_msi, opalpci_alloc_msi),
141 DEVMETHOD(pcib_release_msi, opalpci_release_msi),
142 DEVMETHOD(pcib_alloc_msix, opalpci_alloc_msix),
143 DEVMETHOD(pcib_release_msix, opalpci_release_msix),
144 DEVMETHOD(pcib_map_msi, opalpci_map_msi),
145 DEVMETHOD(pcib_route_interrupt, opalpci_route_interrupt),
146
147 /* PIC interface for MSIs */
148 DEVMETHOD(pic_enable, opalpic_pic_enable),
149 DEVMETHOD(pic_eoi, opalpic_pic_eoi),
150
151 /* Bus interface */
152 DEVMETHOD(bus_get_dma_tag, opalpci_get_dma_tag),
153 DEVMETHOD(bus_get_cpus, ofw_pcibus_get_cpus),
154 DEVMETHOD(bus_get_domain, ofw_pcibus_get_domain),
155
156 DEVMETHOD_END
157 };
158
159 struct opalpci_softc {
160 struct ofw_pci_softc ofw_sc;
161 uint64_t phb_id;
162 vmem_t *msi_vmem;
163 int msi_base; /* Base XIVE number */
164 int base_msi_irq; /* Base IRQ assigned by FreeBSD to this PIC */
165 uint64_t *tce; /* TCE table for 1:1 mapping */
166 struct resource *r_reg;
167 };
168
169 static devclass_t opalpci_devclass;
170 DEFINE_CLASS_1(pcib, opalpci_driver, opalpci_methods,
171 sizeof(struct opalpci_softc), ofw_pci_driver);
172 EARLY_DRIVER_MODULE(opalpci, ofwbus, opalpci_driver, opalpci_devclass, 0, 0,
173 BUS_PASS_BUS);
174
175 static int
opalpci_probe(device_t dev)176 opalpci_probe(device_t dev)
177 {
178 const char *type;
179
180 if (opal_check() != 0)
181 return (ENXIO);
182
183 type = ofw_bus_get_type(dev);
184
185 if (type == NULL || (strcmp(type, "pci") != 0 &&
186 strcmp(type, "pciex") != 0))
187 return (ENXIO);
188
189 if (!OF_hasprop(ofw_bus_get_node(dev), "ibm,opal-phbid"))
190 return (ENXIO);
191
192 device_set_desc(dev, "OPAL Host-PCI bridge");
193 return (BUS_PROBE_GENERIC);
194 }
195
196 static void
pci_phb3_tce_invalidate_entire(struct opalpci_softc * sc)197 pci_phb3_tce_invalidate_entire(struct opalpci_softc *sc)
198 {
199
200 mb();
201 bus_write_8(sc->r_reg, 0x210, PHB3_TCE_KILL_INVAL_ALL);
202 mb();
203 }
204
205 /* Simple function to round to a power of 2 */
206 static uint64_t
round_pow2(uint64_t val)207 round_pow2(uint64_t val)
208 {
209
210 return (1 << (flsl(val + (val - 1)) - 1));
211 }
212
213 /*
214 * Starting with skiboot 5.10 PCIe nodes have a new property,
215 * "ibm,supported-tce-sizes", to denote the TCE sizes available. This allows us
216 * to avoid hard-coding the maximum TCE size allowed, and instead provide a sane
217 * default (however, the "sane" default, which works for all targets, is 64k,
218 * limiting us to 64GB if we have 1M entries.
219 */
220 static uint64_t
max_tce_size(device_t dev)221 max_tce_size(device_t dev)
222 {
223 phandle_t node;
224 cell_t sizes[64]; /* Property is a list of bit-widths, up to 64-bits */
225 int count;
226
227 node = ofw_bus_get_node(dev);
228
229 count = OF_getencprop(node, "ibm,supported-tce-sizes",
230 sizes, sizeof(sizes));
231 if (count < (int) sizeof(cell_t))
232 return OPAL_PCI_TCE_DEFAULT_SEG_SIZE;
233
234 count /= sizeof(cell_t);
235
236 return (1ULL << sizes[count - 1]);
237 }
238
239 static int
opalpci_attach(device_t dev)240 opalpci_attach(device_t dev)
241 {
242 struct opalpci_softc *sc;
243 cell_t id[2], m64ranges[2], m64window[6], npe;
244 phandle_t node;
245 int i, err;
246 uint64_t maxmem;
247 uint64_t entries;
248 uint64_t tce_size;
249 uint64_t tce_tbl_size;
250 int m64bar;
251 int rid;
252
253 sc = device_get_softc(dev);
254 node = ofw_bus_get_node(dev);
255
256 switch (OF_getproplen(node, "ibm,opal-phbid")) {
257 case 8:
258 OF_getencprop(node, "ibm,opal-phbid", id, 8);
259 sc->phb_id = ((uint64_t)id[0] << 32) | id[1];
260 break;
261 case 4:
262 OF_getencprop(node, "ibm,opal-phbid", id, 4);
263 sc->phb_id = id[0];
264 break;
265 default:
266 device_printf(dev, "PHB ID property had wrong length (%zd)\n",
267 OF_getproplen(node, "ibm,opal-phbid"));
268 return (ENXIO);
269 }
270
271 if (bootverbose)
272 device_printf(dev, "OPAL ID %#lx\n", sc->phb_id);
273
274 rid = 0;
275 sc->r_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
276 &rid, RF_ACTIVE | RF_SHAREABLE);
277 if (sc->r_reg == NULL) {
278 device_printf(dev, "Failed to allocate PHB[%jd] registers\n",
279 (uintmax_t)sc->phb_id);
280 return (ENXIO);
281 }
282
283 #if 0
284 /*
285 * Reset PCI IODA table
286 */
287 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PCI_IODA_TABLE,
288 1);
289 if (err != 0) {
290 device_printf(dev, "IODA table reset failed: %d\n", err);
291 return (ENXIO);
292 }
293 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
294 1);
295 if (err < 0) {
296 device_printf(dev, "PHB reset failed: %d\n", err);
297 return (ENXIO);
298 }
299 if (err > 0) {
300 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
301 DELAY(1000*(err + 1)); /* Returns expected delay in ms */
302 }
303 }
304 if (err < 0) {
305 device_printf(dev, "WARNING: PHB IODA reset poll failed: %d\n", err);
306 }
307 err = opal_call(OPAL_PCI_RESET, sc->phb_id, OPAL_RESET_PHB_COMPLETE,
308 0);
309 if (err < 0) {
310 device_printf(dev, "PHB reset failed: %d\n", err);
311 return (ENXIO);
312 }
313 if (err > 0) {
314 while ((err = opal_call(OPAL_PCI_POLL, sc->phb_id)) > 0) {
315 DELAY(1000*(err + 1)); /* Returns expected delay in ms */
316 }
317 }
318 #endif
319
320 /*
321 * Map all devices on the bus to partitionable endpoint one until
322 * such time as we start wanting to do things like bhyve.
323 */
324 err = opal_call(OPAL_PCI_SET_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE,
325 0, OPAL_PCI_BUS_ANY, OPAL_IGNORE_RID_DEVICE_NUMBER,
326 OPAL_IGNORE_RID_FUNC_NUMBER, OPAL_MAP_PE);
327 if (err != 0) {
328 device_printf(dev, "PE mapping failed: %d\n", err);
329 return (ENXIO);
330 }
331
332 /*
333 * Turn on MMIO, mapped to PE 1
334 */
335 if (OF_getencprop(node, "ibm,opal-num-pes", &npe, 4) != 4)
336 npe = 1;
337 for (i = 0; i < npe; i++) {
338 err = opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
339 OPAL_PCI_DEFAULT_PE, OPAL_M32_WINDOW_TYPE, 0, i);
340 if (err != 0)
341 device_printf(dev, "MMIO %d map failed: %d\n", i, err);
342 }
343
344 if (OF_getencprop(node, "ibm,opal-available-m64-ranges",
345 m64ranges, sizeof(m64ranges)) == sizeof(m64ranges))
346 m64bar = m64ranges[0];
347 else
348 m64bar = 0;
349
350 /* XXX: multiple M64 windows? */
351 if (OF_getencprop(node, "ibm,opal-m64-window",
352 m64window, sizeof(m64window)) == sizeof(m64window)) {
353 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
354 OPAL_M64_WINDOW_TYPE, m64bar, 0);
355 opal_call(OPAL_PCI_SET_PHB_MEM_WINDOW, sc->phb_id,
356 OPAL_M64_WINDOW_TYPE, m64bar /* index */,
357 ((uint64_t)m64window[2] << 32) | m64window[3], 0,
358 ((uint64_t)m64window[4] << 32) | m64window[5]);
359 opal_call(OPAL_PCI_MAP_PE_MMIO_WINDOW, sc->phb_id,
360 OPAL_PCI_DEFAULT_PE, OPAL_M64_WINDOW_TYPE,
361 m64bar /* index */, 0);
362 opal_call(OPAL_PCI_PHB_MMIO_ENABLE, sc->phb_id,
363 OPAL_M64_WINDOW_TYPE, m64bar, OPAL_ENABLE_M64_NON_SPLIT);
364 }
365
366 /*
367 * Enable IOMMU for PE1 - map everything 1:1 using
368 * segments of max_tce_size size
369 */
370 tce_size = max_tce_size(dev);
371 maxmem = roundup2(powerpc_ptob(Maxmem), tce_size);
372 entries = round_pow2(maxmem / tce_size);
373 tce_tbl_size = MAX(entries * sizeof(uint64_t), 4096);
374 if (entries > OPAL_PCI_TCE_MAX_ENTRIES)
375 panic("POWERNV supports only %jdGB of memory space\n",
376 (uintmax_t)((OPAL_PCI_TCE_MAX_ENTRIES * tce_size) >> 30));
377 if (bootverbose)
378 device_printf(dev, "Mapping 0-%#jx for DMA\n", (uintmax_t)maxmem);
379 sc->tce = contigmalloc(tce_tbl_size,
380 M_DEVBUF, M_NOWAIT | M_ZERO, 0,
381 BUS_SPACE_MAXADDR, tce_tbl_size, 0);
382 if (sc->tce == NULL)
383 panic("Failed to allocate TCE memory for PHB %jd\n",
384 (uintmax_t)sc->phb_id);
385
386 for (i = 0; i < entries; i++)
387 sc->tce[i] = htobe64((i * tce_size) | OPAL_PCI_TCE_R | OPAL_PCI_TCE_W);
388
389 /* Map TCE for every PE. It seems necessary for Power8 */
390 for (i = 0; i < npe; i++) {
391 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW, sc->phb_id,
392 i, (i << 1),
393 1, pmap_kextract((uint64_t)&sc->tce[0]),
394 tce_tbl_size, tce_size);
395 if (err != 0) {
396 device_printf(dev, "DMA IOMMU mapping failed: %d\n", err);
397 return (ENXIO);
398 }
399
400 err = opal_call(OPAL_PCI_MAP_PE_DMA_WINDOW_REAL, sc->phb_id,
401 i, (i << 1) + 1,
402 (1UL << 59), maxmem);
403 if (err != 0) {
404 device_printf(dev, "DMA 64b bypass mapping failed: %d\n", err);
405 return (ENXIO);
406 }
407 }
408
409 /*
410 * Invalidate all previous TCE entries.
411 */
412 if (ofw_bus_is_compatible(dev, "power8-pciex"))
413 pci_phb3_tce_invalidate_entire(sc);
414 else
415 opal_call(OPAL_PCI_TCE_KILL, sc->phb_id, OPAL_PCI_TCE_KILL_ALL,
416 OPAL_PCI_DEFAULT_PE, 0, 0, 0);
417
418 /*
419 * Get MSI properties
420 */
421 sc->msi_vmem = NULL;
422 if (OF_getproplen(node, "ibm,opal-msi-ranges") > 0) {
423 cell_t msi_ranges[2];
424 OF_getencprop(node, "ibm,opal-msi-ranges",
425 msi_ranges, sizeof(msi_ranges));
426 sc->msi_base = msi_ranges[0];
427
428 sc->msi_vmem = vmem_create("OPAL MSI", msi_ranges[0],
429 msi_ranges[1], 1, 0, M_BESTFIT | M_WAITOK);
430
431 sc->base_msi_irq = powerpc_register_pic(dev,
432 OF_xref_from_node(node),
433 msi_ranges[0] + msi_ranges[1], 0, FALSE);
434
435 if (bootverbose)
436 device_printf(dev, "Supports %d MSIs starting at %d\n",
437 msi_ranges[1], msi_ranges[0]);
438 }
439
440 /* Create the parent DMA tag */
441 /*
442 * Constrain it to POWER8 PHB (ioda2) for now. It seems to mess up on
443 * POWER9 systems.
444 */
445 if (ofw_bus_is_compatible(dev, "ibm,ioda2-phb")) {
446 err = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
447 1, 0, /* alignment, bounds */
448 OPAL_PCI_BUS_SPACE_LOWADDR_32BIT, /* lowaddr */
449 BUS_SPACE_MAXADDR_32BIT, /* highaddr */
450 NULL, NULL, /* filter, filterarg */
451 BUS_SPACE_MAXSIZE, /* maxsize */
452 BUS_SPACE_UNRESTRICTED, /* nsegments */
453 BUS_SPACE_MAXSIZE, /* maxsegsize */
454 0, /* flags */
455 NULL, NULL, /* lockfunc, lockarg */
456 &sc->ofw_sc.sc_dmat);
457 if (err != 0) {
458 device_printf(dev, "Failed to create DMA tag\n");
459 return (err);
460 }
461 }
462
463 /*
464 * General OFW PCI attach
465 */
466 err = ofw_pci_init(dev);
467 if (err != 0)
468 return (err);
469
470 /*
471 * Unfreeze non-config-space PCI operations. Let this fail silently
472 * if e.g. there is no current freeze.
473 */
474 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR, sc->phb_id, OPAL_PCI_DEFAULT_PE,
475 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
476
477 /*
478 * OPAL stores 64-bit BARs in a special property rather than "ranges"
479 */
480 if (OF_getencprop(node, "ibm,opal-m64-window",
481 m64window, sizeof(m64window)) == sizeof(m64window)) {
482 struct ofw_pci_range *rp;
483
484 sc->ofw_sc.sc_nrange++;
485 sc->ofw_sc.sc_range = realloc(sc->ofw_sc.sc_range,
486 sc->ofw_sc.sc_nrange * sizeof(sc->ofw_sc.sc_range[0]),
487 M_DEVBUF, M_WAITOK);
488 rp = &sc->ofw_sc.sc_range[sc->ofw_sc.sc_nrange-1];
489 rp->pci_hi = OFW_PCI_PHYS_HI_SPACE_MEM64 |
490 OFW_PCI_PHYS_HI_PREFETCHABLE;
491 rp->pci = ((uint64_t)m64window[0] << 32) | m64window[1];
492 rp->host = ((uint64_t)m64window[2] << 32) | m64window[3];
493 rp->size = ((uint64_t)m64window[4] << 32) | m64window[5];
494 rman_manage_region(&sc->ofw_sc.sc_mem_rman, rp->pci,
495 rp->pci + rp->size - 1);
496 }
497
498 return (ofw_pci_attach(dev));
499 }
500
501 static uint32_t
opalpci_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)502 opalpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
503 int width)
504 {
505 struct opalpci_softc *sc;
506 uint64_t config_addr;
507 uint8_t byte, eeh_state;
508 uint16_t half;
509 uint32_t word;
510 int error;
511 uint16_t err_type;
512
513 sc = device_get_softc(dev);
514
515 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
516
517 switch (width) {
518 case 1:
519 error = opal_call(OPAL_PCI_CONFIG_READ_BYTE, sc->phb_id,
520 config_addr, reg, vtophys(&byte));
521 word = byte;
522 break;
523 case 2:
524 error = opal_call(OPAL_PCI_CONFIG_READ_HALF_WORD, sc->phb_id,
525 config_addr, reg, vtophys(&half));
526 word = be16toh(half);
527 break;
528 case 4:
529 error = opal_call(OPAL_PCI_CONFIG_READ_WORD, sc->phb_id,
530 config_addr, reg, vtophys(&word));
531 word = be32toh(word);
532 break;
533 default:
534 error = OPAL_SUCCESS;
535 word = 0xffffffff;
536 width = 4;
537 }
538
539 /*
540 * Poking config state for non-existant devices can make
541 * the host bridge hang up. Clear any errors.
542 */
543
544 if (error != OPAL_SUCCESS ||
545 (word == ((1UL << (8 * width)) - 1))) {
546 if (error != OPAL_HARDWARE) {
547 opal_call(OPAL_PCI_EEH_FREEZE_STATUS, sc->phb_id,
548 OPAL_PCI_DEFAULT_PE, vtophys(&eeh_state),
549 vtophys(&err_type), NULL);
550 err_type = be16toh(err_type); /* XXX unused */
551 if (eeh_state != OPAL_EEH_STOPPED_NOT_FROZEN)
552 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
553 sc->phb_id, OPAL_PCI_DEFAULT_PE,
554 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
555 }
556 if (error != OPAL_SUCCESS)
557 word = 0xffffffff;
558 }
559
560 return (word);
561 }
562
563 static void
opalpci_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int width)564 opalpci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
565 u_int reg, uint32_t val, int width)
566 {
567 struct opalpci_softc *sc;
568 uint64_t config_addr;
569 int error = OPAL_SUCCESS;
570
571 sc = device_get_softc(dev);
572
573 config_addr = (bus << 8) | ((slot & 0x1f) << 3) | (func & 0x7);
574
575 switch (width) {
576 case 1:
577 error = opal_call(OPAL_PCI_CONFIG_WRITE_BYTE, sc->phb_id,
578 config_addr, reg, val);
579 break;
580 case 2:
581 error = opal_call(OPAL_PCI_CONFIG_WRITE_HALF_WORD, sc->phb_id,
582 config_addr, reg, val);
583 break;
584 case 4:
585 error = opal_call(OPAL_PCI_CONFIG_WRITE_WORD, sc->phb_id,
586 config_addr, reg, val);
587 break;
588 }
589
590 if (error != OPAL_SUCCESS) {
591 /*
592 * Poking config state for non-existant devices can make
593 * the host bridge hang up. Clear any errors.
594 */
595 if (error != OPAL_HARDWARE) {
596 opal_call(OPAL_PCI_EEH_FREEZE_CLEAR,
597 sc->phb_id, OPAL_PCI_DEFAULT_PE,
598 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
599 }
600 }
601 }
602
603 static int
opalpci_route_interrupt(device_t bus,device_t dev,int pin)604 opalpci_route_interrupt(device_t bus, device_t dev, int pin)
605 {
606
607 return (pin);
608 }
609
610 static int
opalpci_alloc_msi(device_t dev,device_t child,int count,int maxcount,int * irqs)611 opalpci_alloc_msi(device_t dev, device_t child, int count, int maxcount,
612 int *irqs)
613 {
614 struct opalpci_softc *sc;
615 vmem_addr_t start;
616 phandle_t xref;
617 int err, i;
618
619 sc = device_get_softc(dev);
620 if (sc->msi_vmem == NULL)
621 return (ENODEV);
622
623 err = vmem_xalloc(sc->msi_vmem, count, powerof2(count), 0, 0,
624 VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
625
626 if (err)
627 return (err);
628
629 xref = OF_xref_from_node(ofw_bus_get_node(dev));
630 for (i = 0; i < count; i++)
631 irqs[i] = MAP_IRQ(xref, start + i);
632
633 return (0);
634 }
635
636 static int
opalpci_release_msi(device_t dev,device_t child,int count,int * irqs)637 opalpci_release_msi(device_t dev, device_t child, int count, int *irqs)
638 {
639 struct opalpci_softc *sc;
640
641 sc = device_get_softc(dev);
642 if (sc->msi_vmem == NULL)
643 return (ENODEV);
644
645 vmem_xfree(sc->msi_vmem, irqs[0] - sc->base_msi_irq, count);
646 return (0);
647 }
648
649 static int
opalpci_alloc_msix(device_t dev,device_t child,int * irq)650 opalpci_alloc_msix(device_t dev, device_t child, int *irq)
651 {
652 return (opalpci_alloc_msi(dev, child, 1, 1, irq));
653 }
654
655 static int
opalpci_release_msix(device_t dev,device_t child,int irq)656 opalpci_release_msix(device_t dev, device_t child, int irq)
657 {
658 return (opalpci_release_msi(dev, child, 1, &irq));
659 }
660
661 static int
opalpci_map_msi(device_t dev,device_t child,int irq,uint64_t * addr,uint32_t * data)662 opalpci_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
663 uint32_t *data)
664 {
665 struct opalpci_softc *sc;
666 struct pci_devinfo *dinfo;
667 int err, xive;
668
669 sc = device_get_softc(dev);
670 if (sc->msi_vmem == NULL)
671 return (ENODEV);
672
673 xive = irq - sc->base_msi_irq - sc->msi_base;
674 opal_call(OPAL_PCI_SET_XIVE_PE, sc->phb_id, OPAL_PCI_DEFAULT_PE, xive);
675
676 dinfo = device_get_ivars(child);
677 if (dinfo->cfg.msi.msi_alloc > 0 &&
678 (dinfo->cfg.msi.msi_ctrl & PCIM_MSICTRL_64BIT) == 0) {
679 uint32_t msi32;
680 err = opal_call(OPAL_GET_MSI_32, sc->phb_id,
681 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(&msi32),
682 vtophys(data));
683 *addr = be32toh(msi32);
684 } else {
685 err = opal_call(OPAL_GET_MSI_64, sc->phb_id,
686 OPAL_PCI_DEFAULT_PE, xive, 1, vtophys(addr), vtophys(data));
687 *addr = be64toh(*addr);
688 }
689 *data = be32toh(*data);
690
691 if (bootverbose && err != 0)
692 device_printf(child, "OPAL MSI mapping error: %d\n", err);
693
694 return ((err == 0) ? 0 : ENXIO);
695 }
696
697 static void
opalpic_pic_enable(device_t dev,u_int irq,u_int vector,void ** priv)698 opalpic_pic_enable(device_t dev, u_int irq, u_int vector, void **priv)
699 {
700 struct opalpci_softc *sc = device_get_softc(dev);
701
702 PIC_ENABLE(root_pic, irq, vector, priv);
703 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq, priv);
704 }
705
opalpic_pic_eoi(device_t dev,u_int irq,void * priv)706 static void opalpic_pic_eoi(device_t dev, u_int irq, void *priv)
707 {
708 struct opalpci_softc *sc;
709
710 sc = device_get_softc(dev);
711 opal_call(OPAL_PCI_MSI_EOI, sc->phb_id, irq);
712
713 PIC_EOI(root_pic, irq, priv);
714 }
715
716 static bus_dma_tag_t
opalpci_get_dma_tag(device_t dev,device_t child)717 opalpci_get_dma_tag(device_t dev, device_t child)
718 {
719 struct opalpci_softc *sc;
720
721 sc = device_get_softc(dev);
722 return (sc->ofw_sc.sc_dmat);
723 }
724