1#! /usr/bin/env perl 2# Copyright 1998-2020 The OpenSSL Project Authors. All Rights Reserved. 3# 4# Licensed under the Apache License 2.0 (the "License"). You may not use 5# this file except in compliance with the License. You can obtain a copy 6# in the file LICENSE in the source distribution or at 7# https://www.openssl.org/source/license.html 8 9 10# ==================================================================== 11# [Re]written by Andy Polyakov <appro@openssl.org> for the OpenSSL 12# project. The module is, however, dual licensed under OpenSSL and 13# CRYPTOGAMS licenses depending on where you obtain it. For further 14# details see http://www.openssl.org/~appro/cryptogams/. 15# ==================================================================== 16 17# At some point it became apparent that the original SSLeay RC4 18# assembler implementation performs suboptimally on latest IA-32 19# microarchitectures. After re-tuning performance has changed as 20# following: 21# 22# Pentium -10% 23# Pentium III +12% 24# AMD +50%(*) 25# P4 +250%(**) 26# 27# (*) This number is actually a trade-off:-) It's possible to 28# achieve +72%, but at the cost of -48% off PIII performance. 29# In other words code performing further 13% faster on AMD 30# would perform almost 2 times slower on Intel PIII... 31# For reference! This code delivers ~80% of rc4-amd64.pl 32# performance on the same Opteron machine. 33# (**) This number requires compressed key schedule set up by 34# RC4_set_key [see commentary below for further details]. 35 36# May 2011 37# 38# Optimize for Core2 and Westmere [and incidentally Opteron]. Current 39# performance in cycles per processed byte (less is better) and 40# improvement relative to previous version of this module is: 41# 42# Pentium 10.2 # original numbers 43# Pentium III 7.8(*) 44# Intel P4 7.5 45# 46# Opteron 6.1/+20% # new MMX numbers 47# Core2 5.3/+67%(**) 48# Westmere 5.1/+94%(**) 49# Sandy Bridge 5.0/+8% 50# Atom 12.6/+6% 51# VIA Nano 6.4/+9% 52# Ivy Bridge 4.9/±0% 53# Bulldozer 4.9/+15% 54# 55# (*) PIII can actually deliver 6.6 cycles per byte with MMX code, 56# but this specific code performs poorly on Core2. And vice 57# versa, below MMX/SSE code delivering 5.8/7.1 on Core2 performs 58# poorly on PIII, at 8.0/14.5:-( As PIII is not a "hot" CPU 59# [anymore], I chose to discard PIII-specific code path and opt 60# for original IALU-only code, which is why MMX/SSE code path 61# is guarded by SSE2 bit (see below), not MMX/SSE. 62# (**) Performance vs. block size on Core2 and Westmere had a maximum 63# at ... 64 bytes block size. And it was quite a maximum, 40-60% 64# in comparison to largest 8KB block size. Above improvement 65# coefficients are for the largest block size. 66 67$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 68push(@INC,"${dir}","${dir}../../perlasm"); 69require "x86asm.pl"; 70 71$output = pop and open STDOUT,">$output"; 72 73&asm_init($ARGV[0],$x86only = $ARGV[$#ARGV] eq "386"); 74 75$xx="eax"; 76$yy="ebx"; 77$tx="ecx"; 78$ty="edx"; 79$inp="esi"; 80$out="ebp"; 81$dat="edi"; 82 83sub RC4_loop { 84 my $i=shift; 85 my $func = ($i==0)?*mov:*or; 86 87 &add (&LB($yy),&LB($tx)); 88 &mov ($ty,&DWP(0,$dat,$yy,4)); 89 &mov (&DWP(0,$dat,$yy,4),$tx); 90 &mov (&DWP(0,$dat,$xx,4),$ty); 91 &add ($ty,$tx); 92 &inc (&LB($xx)); 93 &and ($ty,0xff); 94 &ror ($out,8) if ($i!=0); 95 if ($i<3) { 96 &mov ($tx,&DWP(0,$dat,$xx,4)); 97 } else { 98 &mov ($tx,&wparam(3)); # reload [re-biased] out 99 } 100 &$func ($out,&DWP(0,$dat,$ty,4)); 101} 102 103if ($alt=0) { 104 # >20% faster on Atom and Sandy Bridge[!], 8% faster on Opteron, 105 # but ~40% slower on Core2 and Westmere... Attempt to add movz 106 # brings down Opteron by 25%, Atom and Sandy Bridge by 15%, yet 107 # on Core2 with movz it's almost 20% slower than below alternative 108 # code... Yes, it's a total mess... 109 my @XX=($xx,$out); 110 $RC4_loop_mmx = sub { # SSE actually... 111 my $i=shift; 112 my $j=$i<=0?0:$i>>1; 113 my $mm=$i<=0?"mm0":"mm".($i&1); 114 115 &add (&LB($yy),&LB($tx)); 116 &lea (@XX[1],&DWP(1,@XX[0])); 117 &pxor ("mm2","mm0") if ($i==0); 118 &psllq ("mm1",8) if ($i==0); 119 &and (@XX[1],0xff); 120 &pxor ("mm0","mm0") if ($i<=0); 121 &mov ($ty,&DWP(0,$dat,$yy,4)); 122 &mov (&DWP(0,$dat,$yy,4),$tx); 123 &pxor ("mm1","mm2") if ($i==0); 124 &mov (&DWP(0,$dat,$XX[0],4),$ty); 125 &add (&LB($ty),&LB($tx)); 126 &movd (@XX[0],"mm7") if ($i==0); 127 &mov ($tx,&DWP(0,$dat,@XX[1],4)); 128 &pxor ("mm1","mm1") if ($i==1); 129 &movq ("mm2",&QWP(0,$inp)) if ($i==1); 130 &movq (&QWP(-8,(@XX[0],$inp)),"mm1") if ($i==0); 131 &pinsrw ($mm,&DWP(0,$dat,$ty,4),$j); 132 133 push (@XX,shift(@XX)) if ($i>=0); 134 } 135} else { 136 # Using pinsrw here improves performance on Intel CPUs by 2-3%, but 137 # brings down AMD by 7%... 138 $RC4_loop_mmx = sub { 139 my $i=shift; 140 141 &add (&LB($yy),&LB($tx)); 142 &psllq ("mm1",8*(($i-1)&7)) if (abs($i)!=1); 143 &mov ($ty,&DWP(0,$dat,$yy,4)); 144 &mov (&DWP(0,$dat,$yy,4),$tx); 145 &mov (&DWP(0,$dat,$xx,4),$ty); 146 &inc ($xx); 147 &add ($ty,$tx); 148 &movz ($xx,&LB($xx)); # (*) 149 &movz ($ty,&LB($ty)); # (*) 150 &pxor ("mm2",$i==1?"mm0":"mm1") if ($i>=0); 151 &movq ("mm0",&QWP(0,$inp)) if ($i<=0); 152 &movq (&QWP(-8,($out,$inp)),"mm2") if ($i==0); 153 &mov ($tx,&DWP(0,$dat,$xx,4)); 154 &movd ($i>0?"mm1":"mm2",&DWP(0,$dat,$ty,4)); 155 156 # (*) This is the key to Core2 and Westmere performance. 157 # Without movz out-of-order execution logic confuses 158 # itself and fails to reorder loads and stores. Problem 159 # appears to be fixed in Sandy Bridge... 160 } 161} 162 163&external_label("OPENSSL_ia32cap_P"); 164 165# void RC4(RC4_KEY *key,size_t len,const unsigned char *inp,unsigned char *out); 166&function_begin("RC4"); 167 &mov ($dat,&wparam(0)); # load key schedule pointer 168 &mov ($ty, &wparam(1)); # load len 169 &mov ($inp,&wparam(2)); # load inp 170 &mov ($out,&wparam(3)); # load out 171 172 &xor ($xx,$xx); # avoid partial register stalls 173 &xor ($yy,$yy); 174 175 &cmp ($ty,0); # safety net 176 &je (&label("abort")); 177 178 &mov (&LB($xx),&BP(0,$dat)); # load key->x 179 &mov (&LB($yy),&BP(4,$dat)); # load key->y 180 &add ($dat,8); 181 182 &lea ($tx,&DWP(0,$inp,$ty)); 183 &sub ($out,$inp); # re-bias out 184 &mov (&wparam(1),$tx); # save input+len 185 186 &inc (&LB($xx)); 187 188 # detect compressed key schedule... 189 &cmp (&DWP(256,$dat),-1); 190 &je (&label("RC4_CHAR")); 191 192 &mov ($tx,&DWP(0,$dat,$xx,4)); 193 194 &and ($ty,-4); # how many 4-byte chunks? 195 &jz (&label("loop1")); 196 197 &mov (&wparam(3),$out); # $out as accumulator in these loops 198 if ($x86only) { 199 &jmp (&label("go4loop4")); 200 } else { 201 &test ($ty,-8); 202 &jz (&label("go4loop4")); 203 204 &picmeup($out,"OPENSSL_ia32cap_P"); 205 &bt (&DWP(0,$out),26); # check SSE2 bit [could have been MMX] 206 &jnc (&label("go4loop4")); 207 208 &mov ($out,&wparam(3)) if (!$alt); 209 &movd ("mm7",&wparam(3)) if ($alt); 210 &and ($ty,-8); 211 &lea ($ty,&DWP(-8,$inp,$ty)); 212 &mov (&DWP(-4,$dat),$ty); # save input+(len/8)*8-8 213 214 &$RC4_loop_mmx(-1); 215 &jmp(&label("loop_mmx_enter")); 216 217 &set_label("loop_mmx",16); 218 &$RC4_loop_mmx(0); 219 &set_label("loop_mmx_enter"); 220 for ($i=1;$i<8;$i++) { &$RC4_loop_mmx($i); } 221 &mov ($ty,$yy); 222 &xor ($yy,$yy); # this is second key to Core2 223 &mov (&LB($yy),&LB($ty)); # and Westmere performance... 224 &cmp ($inp,&DWP(-4,$dat)); 225 &lea ($inp,&DWP(8,$inp)); 226 &jb (&label("loop_mmx")); 227 228 if ($alt) { 229 &movd ($out,"mm7"); 230 &pxor ("mm2","mm0"); 231 &psllq ("mm1",8); 232 &pxor ("mm1","mm2"); 233 &movq (&QWP(-8,$out,$inp),"mm1"); 234 } else { 235 &psllq ("mm1",56); 236 &pxor ("mm2","mm1"); 237 &movq (&QWP(-8,$out,$inp),"mm2"); 238 } 239 &emms (); 240 241 &cmp ($inp,&wparam(1)); # compare to input+len 242 &je (&label("done")); 243 &jmp (&label("loop1")); 244 } 245 246&set_label("go4loop4",16); 247 &lea ($ty,&DWP(-4,$inp,$ty)); 248 &mov (&wparam(2),$ty); # save input+(len/4)*4-4 249 250 &set_label("loop4"); 251 for ($i=0;$i<4;$i++) { RC4_loop($i); } 252 &ror ($out,8); 253 &xor ($out,&DWP(0,$inp)); 254 &cmp ($inp,&wparam(2)); # compare to input+(len/4)*4-4 255 &mov (&DWP(0,$tx,$inp),$out);# $tx holds re-biased out here 256 &lea ($inp,&DWP(4,$inp)); 257 &mov ($tx,&DWP(0,$dat,$xx,4)); 258 &jb (&label("loop4")); 259 260 &cmp ($inp,&wparam(1)); # compare to input+len 261 &je (&label("done")); 262 &mov ($out,&wparam(3)); # restore $out 263 264 &set_label("loop1",16); 265 &add (&LB($yy),&LB($tx)); 266 &mov ($ty,&DWP(0,$dat,$yy,4)); 267 &mov (&DWP(0,$dat,$yy,4),$tx); 268 &mov (&DWP(0,$dat,$xx,4),$ty); 269 &add ($ty,$tx); 270 &inc (&LB($xx)); 271 &and ($ty,0xff); 272 &mov ($ty,&DWP(0,$dat,$ty,4)); 273 &xor (&LB($ty),&BP(0,$inp)); 274 &lea ($inp,&DWP(1,$inp)); 275 &mov ($tx,&DWP(0,$dat,$xx,4)); 276 &cmp ($inp,&wparam(1)); # compare to input+len 277 &mov (&BP(-1,$out,$inp),&LB($ty)); 278 &jb (&label("loop1")); 279 280 &jmp (&label("done")); 281 282# this is essentially Intel P4 specific codepath... 283&set_label("RC4_CHAR",16); 284 &movz ($tx,&BP(0,$dat,$xx)); 285 # strangely enough unrolled loop performs over 20% slower... 286 &set_label("cloop1"); 287 &add (&LB($yy),&LB($tx)); 288 &movz ($ty,&BP(0,$dat,$yy)); 289 &mov (&BP(0,$dat,$yy),&LB($tx)); 290 &mov (&BP(0,$dat,$xx),&LB($ty)); 291 &add (&LB($ty),&LB($tx)); 292 &movz ($ty,&BP(0,$dat,$ty)); 293 &add (&LB($xx),1); 294 &xor (&LB($ty),&BP(0,$inp)); 295 &lea ($inp,&DWP(1,$inp)); 296 &movz ($tx,&BP(0,$dat,$xx)); 297 &cmp ($inp,&wparam(1)); 298 &mov (&BP(-1,$out,$inp),&LB($ty)); 299 &jb (&label("cloop1")); 300 301&set_label("done"); 302 &dec (&LB($xx)); 303 &mov (&DWP(-4,$dat),$yy); # save key->y 304 &mov (&BP(-8,$dat),&LB($xx)); # save key->x 305&set_label("abort"); 306&function_end("RC4"); 307 308######################################################################## 309 310$inp="esi"; 311$out="edi"; 312$idi="ebp"; 313$ido="ecx"; 314$idx="edx"; 315 316# void RC4_set_key(RC4_KEY *key,int len,const unsigned char *data); 317&function_begin("RC4_set_key"); 318 &mov ($out,&wparam(0)); # load key 319 &mov ($idi,&wparam(1)); # load len 320 &mov ($inp,&wparam(2)); # load data 321 &picmeup($idx,"OPENSSL_ia32cap_P"); 322 323 &lea ($out,&DWP(2*4,$out)); # &key->data 324 &lea ($inp,&DWP(0,$inp,$idi)); # $inp to point at the end 325 &neg ($idi); 326 &xor ("eax","eax"); 327 &mov (&DWP(-4,$out),$idi); # borrow key->y 328 329 &bt (&DWP(0,$idx),20); # check for bit#20 330 &jc (&label("c1stloop")); 331 332&set_label("w1stloop",16); 333 &mov (&DWP(0,$out,"eax",4),"eax"); # key->data[i]=i; 334 &add (&LB("eax"),1); # i++; 335 &jnc (&label("w1stloop")); 336 337 &xor ($ido,$ido); 338 &xor ($idx,$idx); 339 340&set_label("w2ndloop",16); 341 &mov ("eax",&DWP(0,$out,$ido,4)); 342 &add (&LB($idx),&BP(0,$inp,$idi)); 343 &add (&LB($idx),&LB("eax")); 344 &add ($idi,1); 345 &mov ("ebx",&DWP(0,$out,$idx,4)); 346 &jnz (&label("wnowrap")); 347 &mov ($idi,&DWP(-4,$out)); 348 &set_label("wnowrap"); 349 &mov (&DWP(0,$out,$idx,4),"eax"); 350 &mov (&DWP(0,$out,$ido,4),"ebx"); 351 &add (&LB($ido),1); 352 &jnc (&label("w2ndloop")); 353&jmp (&label("exit")); 354 355# Unlike all other x86 [and x86_64] implementations, Intel P4 core 356# [including EM64T] was found to perform poorly with above "32-bit" key 357# schedule, a.k.a. RC4_INT. Performance improvement for IA-32 hand-coded 358# assembler turned out to be 3.5x if re-coded for compressed 8-bit one, 359# a.k.a. RC4_CHAR! It's however inappropriate to just switch to 8-bit 360# schedule for x86[_64], because non-P4 implementations suffer from 361# significant performance losses then, e.g. PIII exhibits >2x 362# deterioration, and so does Opteron. In order to assure optimal 363# all-round performance, we detect P4 at run-time and set up compressed 364# key schedule, which is recognized by RC4 procedure. 365 366&set_label("c1stloop",16); 367 &mov (&BP(0,$out,"eax"),&LB("eax")); # key->data[i]=i; 368 &add (&LB("eax"),1); # i++; 369 &jnc (&label("c1stloop")); 370 371 &xor ($ido,$ido); 372 &xor ($idx,$idx); 373 &xor ("ebx","ebx"); 374 375&set_label("c2ndloop",16); 376 &mov (&LB("eax"),&BP(0,$out,$ido)); 377 &add (&LB($idx),&BP(0,$inp,$idi)); 378 &add (&LB($idx),&LB("eax")); 379 &add ($idi,1); 380 &mov (&LB("ebx"),&BP(0,$out,$idx)); 381 &jnz (&label("cnowrap")); 382 &mov ($idi,&DWP(-4,$out)); 383 &set_label("cnowrap"); 384 &mov (&BP(0,$out,$idx),&LB("eax")); 385 &mov (&BP(0,$out,$ido),&LB("ebx")); 386 &add (&LB($ido),1); 387 &jnc (&label("c2ndloop")); 388 389 &mov (&DWP(256,$out),-1); # mark schedule as compressed 390 391&set_label("exit"); 392 &xor ("eax","eax"); 393 &mov (&DWP(-8,$out),"eax"); # key->x=0; 394 &mov (&DWP(-4,$out),"eax"); # key->y=0; 395&function_end("RC4_set_key"); 396 397# const char *RC4_options(void); 398&function_begin_B("RC4_options"); 399 &call (&label("pic_point")); 400&set_label("pic_point"); 401 &blindpop("eax"); 402 &lea ("eax",&DWP(&label("opts")."-".&label("pic_point"),"eax")); 403 &picmeup("edx","OPENSSL_ia32cap_P"); 404 &mov ("edx",&DWP(0,"edx")); 405 &bt ("edx",20); 406 &jc (&label("1xchar")); 407 &bt ("edx",26); 408 &jnc (&label("ret")); 409 &add ("eax",25); 410 &ret (); 411&set_label("1xchar"); 412 &add ("eax",12); 413&set_label("ret"); 414 &ret (); 415&set_label("opts",64); 416&asciz ("rc4(4x,int)"); 417&asciz ("rc4(1x,char)"); 418&asciz ("rc4(8x,mmx)"); 419&asciz ("RC4 for x86, CRYPTOGAMS by <appro\@openssl.org>"); 420&align (64); 421&function_end_B("RC4_options"); 422 423&asm_finish(); 424 425close STDOUT or die "error closing STDOUT: $!"; 426