1 /* tc-m68k.c -- Assemble for the m68k family
2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30 #include "elf/m68k.h"
31
32 static void m68k_elf_cons (int);
33 static void m68k_elf_gnu_attribute (int);
34
35 /* This string holds the chars that always start a comment. If the
36 pre-processor is disabled, these aren't very useful. The macro
37 tc_comment_chars points to this. We use this, rather than the
38 usual comment_chars, so that the --bitwise-or option will work. */
39 #if defined (TE_SVR4) || defined (TE_DELTA)
40 const char *m68k_comment_chars = "|#";
41 #else
42 const char *m68k_comment_chars = "|";
43 #endif
44
45 /* This array holds the chars that only start a comment at the beginning of
46 a line. If the line seems to have the form '# 123 filename'
47 .line and .file directives will appear in the pre-processed output */
48 /* Note that input_file.c hand checks for '#' at the beginning of the
49 first line of the input file. This is because the compiler outputs
50 #NO_APP at the beginning of its output. */
51 /* Also note that comments like this one will always work. */
52 const char line_comment_chars[] = "#*";
53
54 const char line_separator_chars[] = ";";
55
56 /* Chars that can be used to separate mant from exp in floating point nums. */
57 const char EXP_CHARS[] = "eE";
58
59 /* Chars that mean this number is a floating point constant, as
60 in "0f12.456" or "0d1.2345e12". */
61
62 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
63
64 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
65 changed in read.c . Ideally it shouldn't have to know about it at all,
66 but nothing is ideal around here. */
67
68 /* Are we trying to generate PIC code? If so, absolute references
69 ought to be made into linkage table references or pc-relative
70 references. Not implemented. For ELF there are other means
71 to denote pic relocations. */
72 int flag_want_pic;
73
74 static int flag_short_refs; /* -l option. */
75 static int flag_long_jumps; /* -S option. */
76 static int flag_keep_pcrel; /* --pcrel option. */
77 static bool lcfix = false;
78
79 #ifdef REGISTER_PREFIX_OPTIONAL
80 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81 #else
82 int flag_reg_prefix_optional;
83 #endif
84
85 /* Whether --register-prefix-optional was used on the command line. */
86 static int reg_prefix_optional_seen;
87
88 /* The floating point coprocessor to use by default. */
89 static enum m68k_register m68k_float_copnum = COP1;
90
91 /* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93 static int m68k_abspcadd;
94
95 /* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97 static int m68k_quick = 1;
98
99 /* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102 static int m68k_rel32 = 1;
103
104 /* This is non-zero if m68k_rel32 was set from the command line. */
105 static int m68k_rel32_from_cmdline;
106
107 /* The default width to use for an index register when using a base
108 displacement. */
109 static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111 /* The current label. */
112
113 static struct m68k_tc_sy *current_label;
114
115 /* Pointer to list holding the opcodes sorted by name. */
116 static struct m68k_opcode const ** m68k_sorted_opcodes;
117
118 /* It's an arbitrary name: This means I don't approve of it.
119 See flames below. */
120 static struct obstack robyn;
121
122 struct m68k_incant
123 {
124 const char *m_operands;
125 unsigned long m_opcode;
126 short m_opnum;
127 short m_codenum;
128 int m_arch;
129 struct m68k_incant *m_next;
130 };
131
132 #define getone(x) ((((x)->m_opcode)>>16)&0xffff)
133 #define gettwo(x) (((x)->m_opcode)&0xffff)
134
135 static const enum m68k_register m68000_ctrl[] = { 0 };
136 static const enum m68k_register m68010_ctrl[] = {
137 SFC, DFC, USP, VBR,
138 0
139 };
140 static const enum m68k_register m68020_ctrl[] = {
141 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
142 0
143 };
144 static const enum m68k_register m68040_ctrl[] = {
145 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
146 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
147 0
148 };
149 static const enum m68k_register m68060_ctrl[] = {
150 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
151 USP, VBR, URP, SRP, PCR,
152 0
153 };
154 static const enum m68k_register mcf_ctrl[] = {
155 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
156 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
157 0
158 };
159 static const enum m68k_register mcf51_ctrl[] = {
160 VBR, CPUCR,
161 0
162 };
163 static const enum m68k_register mcf5206_ctrl[] = {
164 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
165 0
166 };
167 static const enum m68k_register mcf5208_ctrl[] = {
168 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
169 0
170 };
171 static const enum m68k_register mcf5210a_ctrl[] = {
172 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
173 0
174 };
175 static const enum m68k_register mcf5213_ctrl[] = {
176 VBR, RAMBAR, RAMBAR1, FLASHBAR,
177 0
178 };
179 static const enum m68k_register mcf5216_ctrl[] = {
180 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
181 0
182 };
183 static const enum m68k_register mcf5221x_ctrl[] = {
184 VBR, FLASHBAR, RAMBAR, RAMBAR1,
185 0
186 };
187 static const enum m68k_register mcf52223_ctrl[] = {
188 VBR, FLASHBAR, RAMBAR, RAMBAR1,
189 0
190 };
191 static const enum m68k_register mcf52235_ctrl[] = {
192 VBR, FLASHBAR, RAMBAR, RAMBAR1,
193 0
194 };
195 static const enum m68k_register mcf5225_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
197 0
198 };
199 static const enum m68k_register mcf52259_ctrl[] = {
200 VBR, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202 };
203 static const enum m68k_register mcf52277_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
205 0
206 };
207 static const enum m68k_register mcf5235_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
209 0
210 };
211 static const enum m68k_register mcf5249_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
213 0
214 };
215 static const enum m68k_register mcf5250_ctrl[] = {
216 VBR,
217 0
218 };
219 static const enum m68k_register mcf5253_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
221 0
222 };
223 static const enum m68k_register mcf5271_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
225 0
226 };
227 static const enum m68k_register mcf5272_ctrl[] = {
228 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
229 0
230 };
231 static const enum m68k_register mcf5275_ctrl[] = {
232 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
233 0
234 };
235 static const enum m68k_register mcf5282_ctrl[] = {
236 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
237 0
238 };
239 static const enum m68k_register mcf53017_ctrl[] = {
240 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
241 0
242 };
243 static const enum m68k_register mcf5307_ctrl[] = {
244 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
245 0
246 };
247 static const enum m68k_register mcf5329_ctrl[] = {
248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
249 0
250 };
251 static const enum m68k_register mcf5373_ctrl[] = {
252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
253 0
254 };
255 static const enum m68k_register mcfv4e_ctrl[] = {
256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
269 0
270 };
271 static const enum m68k_register mcf5407_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
273 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279 };
280 static const enum m68k_register mcf54418_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
282 VBR, PC, RAMBAR1,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
286 RAMBAR /* RAMBAR1 */,
287 0
288 };
289 static const enum m68k_register mcf54455_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR1,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
295 RAMBAR /* RAMBAR1 */,
296 0
297 };
298 static const enum m68k_register mcf5475_ctrl[] = {
299 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
300 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
301 /* Legacy names */
302 TC /* ASID */, BUSCR /* MMUBAR */,
303 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
304 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
305 0
306 };
307 static const enum m68k_register mcf5485_ctrl[] = {
308 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
309 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
310 /* Legacy names */
311 TC /* ASID */, BUSCR /* MMUBAR */,
312 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
313 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
314 0
315 };
316 static const enum m68k_register fido_ctrl[] = {
317 SFC, DFC, USP, VBR, CAC, MBO,
318 0
319 };
320 #define cpu32_ctrl m68010_ctrl
321
322 static const enum m68k_register *control_regs;
323
324 /* Internal form of a 68020 instruction. */
325 struct m68k_it
326 {
327 const char *error;
328 const char *args; /* List of opcode info. */
329 int numargs;
330
331 int numo; /* Number of shorts in opcode. */
332 short opcode[11];
333
334 struct m68k_op operands[6];
335
336 int nexp; /* Number of exprs in use. */
337 struct m68k_exp exprs[4];
338
339 int nfrag; /* Number of frags we have to produce. */
340 struct
341 {
342 int fragoff; /* Where in the current opcode the frag ends. */
343 symbolS *fadd;
344 offsetT foff;
345 int fragty;
346 }
347 fragb[4];
348
349 int nrel; /* Num of reloc structs in use. */
350 struct
351 {
352 int n;
353 expressionS exp;
354 char wid;
355 char pcrel;
356 /* In a pc relative address the difference between the address
357 of the offset and the address that the offset is relative
358 to. This depends on the addressing mode. Basically this
359 is the value to put in the offset field to address the
360 first byte of the offset, without regarding the special
361 significance of some values (in the branch instruction, for
362 example). */
363 int pcrel_fix;
364 /* Whether this expression needs special pic relocation, and if
365 so, which. */
366 enum pic_relocation pic_reloc;
367 }
368 reloc[5]; /* Five is enough??? */
369 };
370
371 #define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
372 #define float_of_arch(x) ((x) & mfloat)
373 #define mmu_of_arch(x) ((x) & mmmu)
374 #define arch_coldfire_p(x) ((x) & mcfisa_a)
375 #define arch_coldfire_fpu(x) ((x) & cfloat)
376
377 /* Macros for determining if cpu supports a specific addressing mode. */
378 #define HAVE_LONG_DISP(x) \
379 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
380 #define HAVE_LONG_CALL(x) \
381 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
382 #define HAVE_LONG_COND(x) \
383 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
384 #define HAVE_LONG_BRANCH(x) \
385 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
386 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
387
388 static struct m68k_it the_ins; /* The instruction being assembled. */
389
390 #define op(ex) ((ex)->exp.X_op)
391 #define adds(ex) ((ex)->exp.X_add_symbol)
392 #define subs(ex) ((ex)->exp.X_op_symbol)
393 #define offs(ex) ((ex)->exp.X_add_number)
394
395 /* Macros for adding things to the m68k_it struct. */
396 #define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
397
398 /* Like addword, but goes BEFORE general operands. */
399
400 static void
insop(int w,const struct m68k_incant * opcode)401 insop (int w, const struct m68k_incant *opcode)
402 {
403 int z;
404 for (z = the_ins.numo; z > opcode->m_codenum; --z)
405 the_ins.opcode[z] = the_ins.opcode[z - 1];
406 for (z = 0; z < the_ins.nrel; z++)
407 the_ins.reloc[z].n += 2;
408 for (z = 0; z < the_ins.nfrag; z++)
409 the_ins.fragb[z].fragoff++;
410 the_ins.opcode[opcode->m_codenum] = w;
411 the_ins.numo++;
412 }
413
414 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
415 Blecch. */
416 static void
add_fix(int width,struct m68k_exp * exp,int pc_rel,int pc_fix)417 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
418 {
419 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
420 ? the_ins.numo * 2 - 1
421 : (width == 'b'
422 ? the_ins.numo * 2 + 1
423 : the_ins.numo * 2));
424 the_ins.reloc[the_ins.nrel].exp = exp->exp;
425 the_ins.reloc[the_ins.nrel].wid = width;
426 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
427 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
428 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
429 }
430
431 /* Cause an extra frag to be generated here, inserting up to 10 bytes
432 (that value is chosen in the frag_var call in md_assemble). TYPE
433 is the subtype of the frag to be generated; its primary type is
434 rs_machine_dependent.
435
436 The TYPE parameter is also used by md_convert_frag_1 and
437 md_estimate_size_before_relax. The appropriate type of fixup will
438 be emitted by md_convert_frag_1.
439
440 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
441 static void
add_frag(symbolS * add,offsetT off,int type)442 add_frag (symbolS *add, offsetT off, int type)
443 {
444 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
445 the_ins.fragb[the_ins.nfrag].fadd = add;
446 the_ins.fragb[the_ins.nfrag].foff = off;
447 the_ins.fragb[the_ins.nfrag++].fragty = type;
448 }
449
450 #define isvar(ex) \
451 (op (ex) != O_constant && op (ex) != O_big)
452
453 static char *crack_operand (char *str, struct m68k_op *opP);
454 static int get_num (struct m68k_exp *exp, int ok);
455 static int reverse_16_bits (int in);
456 static int reverse_8_bits (int in);
457 static void install_gen_operand (int mode, int val);
458 static void install_operand (int mode, int val);
459 static void s_data1 (int);
460 static void s_data2 (int);
461 static void s_even (int);
462 static void s_proc (int);
463 static void s_chip (int);
464 static void s_fopt (int);
465 static void s_opt (int);
466 static void s_reg (int);
467 static void s_restore (int);
468 static void s_save (int);
469 static void s_mri_if (int);
470 static void s_mri_else (int);
471 static void s_mri_endi (int);
472 static void s_mri_break (int);
473 static void s_mri_next (int);
474 static void s_mri_for (int);
475 static void s_mri_endf (int);
476 static void s_mri_repeat (int);
477 static void s_mri_until (int);
478 static void s_mri_while (int);
479 static void s_mri_endw (int);
480 static void s_m68k_cpu (int);
481 static void s_m68k_arch (int);
482
483 struct m68k_cpu
484 {
485 unsigned long arch; /* Architecture features. */
486 const enum m68k_register *control_regs; /* Control regs on chip */
487 const char *name; /* Name */
488 int alias; /* Alias for a canonical name. If 1, then
489 succeeds canonical name, if -1 then
490 succeeds canonical name, if <-1 ||>1 this is a
491 deprecated name, and the next/previous name
492 should be used. */
493 };
494
495 /* We hold flags for features explicitly enabled and explicitly
496 disabled. */
497 static int current_architecture;
498 static int not_current_architecture;
499 static const struct m68k_cpu *selected_arch;
500 static const struct m68k_cpu *selected_cpu;
501 static int initialized;
502
503 /* Architecture models. */
504 static const struct m68k_cpu m68k_archs[] =
505 {
506 {m68000, m68000_ctrl, "68000", 0},
507 {m68010, m68010_ctrl, "68010", 0},
508 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
509 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
510 {m68040, m68040_ctrl, "68040", 0},
511 {m68060, m68060_ctrl, "68060", 0},
512 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
513 {fido_a, fido_ctrl, "fidoa", 0},
514 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
515 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
516 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
517 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
518 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
519 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
520 {0,0,NULL, 0}
521 };
522
523 /* For -mno-mac we want to turn off all types of mac. */
524 static const unsigned no_mac = mcfmac | mcfemac;
525
526 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
527 for either. */
528 static const struct m68k_cpu m68k_extensions[] =
529 {
530 {m68851, NULL, "68851", -1},
531 {m68881, NULL, "68881", -1},
532 {m68881, NULL, "68882", -1},
533
534 {cfloat|m68881, NULL, "float", 0},
535
536 {mcfhwdiv, NULL, "div", 1},
537 {mcfusp, NULL, "usp", 1},
538 {mcfmac, (void *)&no_mac, "mac", 1},
539 {mcfemac, NULL, "emac", 1},
540
541 {0,NULL,NULL, 0}
542 };
543
544 /* Processor list */
545 static const struct m68k_cpu m68k_cpus[] =
546 {
547 {m68000, m68000_ctrl, "68000", 0},
548 {m68000, m68000_ctrl, "68ec000", 1},
549 {m68000, m68000_ctrl, "68hc000", 1},
550 {m68000, m68000_ctrl, "68hc001", 1},
551 {m68000, m68000_ctrl, "68008", 1},
552 {m68000, m68000_ctrl, "68302", 1},
553 {m68000, m68000_ctrl, "68306", 1},
554 {m68000, m68000_ctrl, "68307", 1},
555 {m68000, m68000_ctrl, "68322", 1},
556 {m68000, m68000_ctrl, "68356", 1},
557 {m68010, m68010_ctrl, "68010", 0},
558 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
559 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
560 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
561 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
562 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
563 {m68040, m68040_ctrl, "68040", 0},
564 {m68040, m68040_ctrl, "68ec040", 1},
565 {m68060, m68060_ctrl, "68060", 0},
566 {m68060, m68060_ctrl, "68ec060", 1},
567
568 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
569 {cpu32|m68881, cpu32_ctrl, "68330", 1},
570 {cpu32|m68881, cpu32_ctrl, "68331", 1},
571 {cpu32|m68881, cpu32_ctrl, "68332", 1},
572 {cpu32|m68881, cpu32_ctrl, "68333", 1},
573 {cpu32|m68881, cpu32_ctrl, "68334", 1},
574 {cpu32|m68881, cpu32_ctrl, "68336", 1},
575 {cpu32|m68881, cpu32_ctrl, "68340", 1},
576 {cpu32|m68881, cpu32_ctrl, "68341", 1},
577 {cpu32|m68881, cpu32_ctrl, "68349", 1},
578 {cpu32|m68881, cpu32_ctrl, "68360", 1},
579
580 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
581 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
582 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
583 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
584 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
585 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
586 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
587 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
588 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
589 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
590 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
591 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
592
593 {mcfisa_a, mcf_ctrl, "5200", 0},
594 {mcfisa_a, mcf_ctrl, "5202", 1},
595 {mcfisa_a, mcf_ctrl, "5204", 1},
596 {mcfisa_a, mcf5206_ctrl, "5206", 1},
597
598 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
599
600 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
601 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
602
603 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
604 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
605
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
607 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
608 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
612 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
613
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
615
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
617 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
618
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
623
624 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
626
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
628 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
629
630 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
633 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
635
636 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
637 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
638 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
639
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
641 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
644 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
646
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
649
650 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
651
652 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
653 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
654
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
659
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
661 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
664 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
665 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
666 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
667
668 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
669
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
674
675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
678
679 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
680
681 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
682 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
683 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
684 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
685 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
686
687 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
688 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
689 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
690 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
691 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
692 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
693
694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
695 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
696 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
697 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
698 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
699 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
700 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
701
702 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
704 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
705 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
706 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
708 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
709
710 {fido_a, fido_ctrl, "fidoa", 0},
711 {fido_a, fido_ctrl, "fido", 1},
712
713 {0,NULL,NULL, 0}
714 };
715
716 static const struct m68k_cpu *m68k_lookup_cpu
717 (const char *, const struct m68k_cpu *, int, int *);
718 static int m68k_set_arch (const char *, int, int);
719 static int m68k_set_cpu (const char *, int, int);
720 static int m68k_set_extension (const char *, int, int);
721 static void m68k_init_arch (void);
722
723 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
724 architecture and we have a lot of relaxation modes. */
725
726 /* Macros used in the relaxation code. */
727 #define TAB(x,y) (((x) << 2) + (y))
728 #define TABTYPE(x) ((x) >> 2)
729
730 /* Relaxation states. */
731 #define BYTE 0
732 #define SHORT 1
733 #define LONG 2
734 #define SZ_UNDEF 3
735
736 /* Here are all the relaxation modes we support. First we can relax ordinary
737 branches. On 68020 and higher and on CPU32 all branch instructions take
738 three forms, so on these CPUs all branches always remain as such. When we
739 have to expand to the LONG form on a 68000, though, we substitute an
740 absolute jump instead. This is a direct replacement for unconditional
741 branches and a branch over a jump for conditional branches. However, if the
742 user requires PIC and disables this with --pcrel, we can only relax between
743 BYTE and SHORT forms, punting if that isn't enough. This gives us four
744 different relaxation modes for branches: */
745
746 #define BRANCHBWL 0 /* Branch byte, word, or long. */
747 #define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
748 #define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
749 #define BRANCHBW 3 /* Branch byte or word. */
750
751 /* We also relax coprocessor branches and DBcc's. All CPUs that support
752 coprocessor branches support them in word and long forms, so we have only
753 one relaxation mode for them. DBcc's are word only on all CPUs. We can
754 relax them to the LONG form with a branch-around sequence. This sequence
755 can use a long branch (if available) or an absolute jump (if acceptable).
756 This gives us two relaxation modes. If long branches are not available and
757 absolute jumps are not acceptable, we don't relax DBcc's. */
758
759 #define FBRANCH 4 /* Coprocessor branch. */
760 #define DBCCLBR 5 /* DBcc relaxable with a long branch. */
761 #define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
762
763 /* That's all for instruction relaxation. However, we also relax PC-relative
764 operands. Specifically, we have three operand relaxation modes. On the
765 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
766 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
767 two. Also PC+displacement+index operands in their simple form (with a non-
768 suppressed index without memory indirection) are supported on all CPUs, but
769 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
770 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
771 form of the PC+displacement+index operand. Finally, some absolute operands
772 can be relaxed down to 16-bit PC-relative. */
773
774 #define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
775 #define PCINDEX 8 /* PC + displacement + index. */
776 #define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
777
778 /* This relaxation is required for branches where there is no long
779 branch and we are in pcrel mode. We generate a bne/beq pair. */
780 #define BRANCHBWPL 10 /* Branch byte, word or pair of longs
781 */
782
783 /* Note that calls to frag_var need to specify the maximum expansion
784 needed; this is currently 12 bytes for bne/beq pair. */
785 #define FRAG_VAR_SIZE 12
786
787 /* The fields are:
788 How far Forward this mode will reach:
789 How far Backward this mode will reach:
790 How many bytes this mode will add to the size of the frag
791 Which mode to go to if the offset won't fit in this one
792
793 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
794 relax_typeS md_relax_table[] =
795 {
796 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
797 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
798 { 0, 0, 4, 0 },
799 { 1, 1, 0, 0 },
800
801 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
802 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
803 { 0, 0, 4, 0 },
804 { 1, 1, 0, 0 },
805
806 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
807 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
808 { 0, 0, 6, 0 },
809 { 1, 1, 0, 0 },
810
811 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
812 { 0, 0, 2, 0 },
813 { 1, 1, 0, 0 },
814 { 1, 1, 0, 0 },
815
816 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
817 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
818 { 0, 0, 4, 0 },
819 { 1, 1, 0, 0 },
820
821 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
822 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
823 { 0, 0, 10, 0 },
824 { 1, 1, 0, 0 },
825
826 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
827 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
828 { 0, 0, 10, 0 },
829 { 1, 1, 0, 0 },
830
831 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
832 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
833 { 0, 0, 6, 0 },
834 { 1, 1, 0, 0 },
835
836 { 125, -130, 0, TAB (PCINDEX, SHORT) },
837 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
838 { 0, 0, 4, 0 },
839 { 1, 1, 0, 0 },
840
841 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
842 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
843 { 0, 0, 4, 0 },
844 { 1, 1, 0, 0 },
845
846 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
847 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
848 { 0, 0, 10, 0 },
849 { 1, 1, 0, 0 },
850 };
851
852 /* These are the machine dependent pseudo-ops. These are included so
853 the assembler can work on the output from the SUN C compiler, which
854 generates these. */
855
856 /* This table describes all the machine specific pseudo-ops the assembler
857 has to support. The fields are:
858 pseudo-op name without dot
859 function to call to execute this pseudo-op
860 Integer arg to pass to the function. */
861 const pseudo_typeS md_pseudo_table[] =
862 {
863 {"data1", s_data1, 0},
864 {"data2", s_data2, 0},
865 {"even", s_even, 0},
866 {"skip", s_space, 0},
867 {"proc", s_proc, 0},
868 {"align", s_align_bytes, 0},
869 {"swbeg", s_ignore, 0},
870 {"long", m68k_elf_cons, 4},
871 {"extend", float_cons, 'x'},
872 {"ldouble", float_cons, 'x'},
873
874 {"arch", s_m68k_arch, 0},
875 {"cpu", s_m68k_cpu, 0},
876 {"gnu_attribute", m68k_elf_gnu_attribute, 0},
877
878 /* The following pseudo-ops are supported for MRI compatibility. */
879 {"chip", s_chip, 0},
880 {"comline", s_space, 1},
881 {"fopt", s_fopt, 0},
882 {"mask2", s_ignore, 0},
883 {"opt", s_opt, 0},
884 {"reg", s_reg, 0},
885 {"restore", s_restore, 0},
886 {"save", s_save, 0},
887
888 {"if", s_mri_if, 0},
889 {"if.b", s_mri_if, 'b'},
890 {"if.w", s_mri_if, 'w'},
891 {"if.l", s_mri_if, 'l'},
892 {"else", s_mri_else, 0},
893 {"else.s", s_mri_else, 's'},
894 {"else.l", s_mri_else, 'l'},
895 {"endi", s_mri_endi, 0},
896 {"break", s_mri_break, 0},
897 {"break.s", s_mri_break, 's'},
898 {"break.l", s_mri_break, 'l'},
899 {"next", s_mri_next, 0},
900 {"next.s", s_mri_next, 's'},
901 {"next.l", s_mri_next, 'l'},
902 {"for", s_mri_for, 0},
903 {"for.b", s_mri_for, 'b'},
904 {"for.w", s_mri_for, 'w'},
905 {"for.l", s_mri_for, 'l'},
906 {"endf", s_mri_endf, 0},
907 {"repeat", s_mri_repeat, 0},
908 {"until", s_mri_until, 0},
909 {"until.b", s_mri_until, 'b'},
910 {"until.w", s_mri_until, 'w'},
911 {"until.l", s_mri_until, 'l'},
912 {"while", s_mri_while, 0},
913 {"while.b", s_mri_while, 'b'},
914 {"while.w", s_mri_while, 'w'},
915 {"while.l", s_mri_while, 'l'},
916 {"endw", s_mri_endw, 0},
917
918 {0, 0, 0}
919 };
920
921 /* The mote pseudo ops are put into the opcode table, since they
922 don't start with a . they look like opcodes to gas. */
923
924 const pseudo_typeS mote_pseudo_table[] =
925 {
926
927 {"dcl", cons, 4},
928 {"dc", cons, 2},
929 {"dcw", cons, 2},
930 {"dcb", cons, 1},
931
932 {"dsl", s_space, 4},
933 {"ds", s_space, 2},
934 {"dsw", s_space, 2},
935 {"dsb", s_space, 1},
936
937 {"xdef", s_globl, 0},
938 {"align", s_align_bytes, 0},
939 {0, 0, 0}
940 };
941
942 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
943 gives identical results to a 32-bit host. */
944 #define TRUNC(X) ((valueT) (X) & 0xffffffff)
945 #define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
946
947 #define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
948 #define isubyte(x) ((valueT) TRUNC (x) < 0x100)
949 #define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
950 #define isuword(x) ((valueT) TRUNC (x) < 0x10000)
951
952 #define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
953 #define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
954 #define islong(x) (1)
955
956 static char notend_table[256];
957 static char alt_notend_table[256];
958 #define notend(s) \
959 (! (notend_table[(unsigned char) *s] \
960 || (*s == ':' \
961 && alt_notend_table[(unsigned char) s[1]])))
962
963
964 /* Return zero if the reference to SYMBOL from within the same segment may
965 be relaxed. */
966
967 /* On an ELF system, we can't relax an externally visible symbol,
968 because it may be overridden by a shared library. However, if
969 TARGET_OS is "elf", then we presume that we are assembling for an
970 embedded system, in which case we don't have to worry about shared
971 libraries, and we can relax any external sym. */
972
973 #define relaxable_symbol(symbol) \
974 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
975 || S_IS_WEAK (symbol)))
976
977 /* Compute the relocation code for a fixup of SIZE bytes, using pc
978 relative relocation if PCREL is non-zero. PIC says whether a special
979 pic relocation was requested. */
980
981 static bfd_reloc_code_real_type
get_reloc_code(int size,int pcrel,enum pic_relocation pic)982 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
983 {
984 switch (pic)
985 {
986 case pic_got_pcrel:
987 switch (size)
988 {
989 case 1:
990 return BFD_RELOC_8_GOT_PCREL;
991 case 2:
992 return BFD_RELOC_16_GOT_PCREL;
993 case 4:
994 return BFD_RELOC_32_GOT_PCREL;
995 }
996 break;
997
998 case pic_got_off:
999 switch (size)
1000 {
1001 case 1:
1002 return BFD_RELOC_8_GOTOFF;
1003 case 2:
1004 return BFD_RELOC_16_GOTOFF;
1005 case 4:
1006 return BFD_RELOC_32_GOTOFF;
1007 }
1008 break;
1009
1010 case pic_plt_pcrel:
1011 switch (size)
1012 {
1013 case 1:
1014 return BFD_RELOC_8_PLT_PCREL;
1015 case 2:
1016 return BFD_RELOC_16_PLT_PCREL;
1017 case 4:
1018 return BFD_RELOC_32_PLT_PCREL;
1019 }
1020 break;
1021
1022 case pic_plt_off:
1023 switch (size)
1024 {
1025 case 1:
1026 return BFD_RELOC_8_PLTOFF;
1027 case 2:
1028 return BFD_RELOC_16_PLTOFF;
1029 case 4:
1030 return BFD_RELOC_32_PLTOFF;
1031 }
1032 break;
1033
1034 case pic_tls_gd:
1035 switch (size)
1036 {
1037 case 1:
1038 return BFD_RELOC_68K_TLS_GD8;
1039 case 2:
1040 return BFD_RELOC_68K_TLS_GD16;
1041 case 4:
1042 return BFD_RELOC_68K_TLS_GD32;
1043 }
1044 break;
1045
1046 case pic_tls_ldm:
1047 switch (size)
1048 {
1049 case 1:
1050 return BFD_RELOC_68K_TLS_LDM8;
1051 case 2:
1052 return BFD_RELOC_68K_TLS_LDM16;
1053 case 4:
1054 return BFD_RELOC_68K_TLS_LDM32;
1055 }
1056 break;
1057
1058 case pic_tls_ldo:
1059 switch (size)
1060 {
1061 case 1:
1062 return BFD_RELOC_68K_TLS_LDO8;
1063 case 2:
1064 return BFD_RELOC_68K_TLS_LDO16;
1065 case 4:
1066 return BFD_RELOC_68K_TLS_LDO32;
1067 }
1068 break;
1069
1070 case pic_tls_ie:
1071 switch (size)
1072 {
1073 case 1:
1074 return BFD_RELOC_68K_TLS_IE8;
1075 case 2:
1076 return BFD_RELOC_68K_TLS_IE16;
1077 case 4:
1078 return BFD_RELOC_68K_TLS_IE32;
1079 }
1080 break;
1081
1082 case pic_tls_le:
1083 switch (size)
1084 {
1085 case 1:
1086 return BFD_RELOC_68K_TLS_LE8;
1087 case 2:
1088 return BFD_RELOC_68K_TLS_LE16;
1089 case 4:
1090 return BFD_RELOC_68K_TLS_LE32;
1091 }
1092 break;
1093
1094 case pic_none:
1095 if (pcrel)
1096 {
1097 switch (size)
1098 {
1099 case 1:
1100 return BFD_RELOC_8_PCREL;
1101 case 2:
1102 return BFD_RELOC_16_PCREL;
1103 case 4:
1104 return BFD_RELOC_32_PCREL;
1105 }
1106 }
1107 else
1108 {
1109 switch (size)
1110 {
1111 case 1:
1112 return BFD_RELOC_8;
1113 case 2:
1114 return BFD_RELOC_16;
1115 case 4:
1116 return BFD_RELOC_32;
1117 }
1118 }
1119 }
1120
1121 if (pcrel)
1122 {
1123 if (pic == pic_none)
1124 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1125 else
1126 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1127 }
1128 else
1129 {
1130 if (pic == pic_none)
1131 as_bad (_("Can not do %d byte relocation"), size);
1132 else
1133 as_bad (_("Can not do %d byte pic relocation"), size);
1134 }
1135
1136 return BFD_RELOC_NONE;
1137 }
1138
1139 /* Here we decide which fixups can be adjusted to make them relative
1140 to the beginning of the section instead of the symbol. Basically
1141 we need to make sure that the dynamic relocations are done
1142 correctly, so in some cases we force the original symbol to be
1143 used. */
1144 int
tc_m68k_fix_adjustable(fixS * fixP)1145 tc_m68k_fix_adjustable (fixS *fixP)
1146 {
1147 /* Adjust_reloc_syms doesn't know about the GOT. */
1148 switch (fixP->fx_r_type)
1149 {
1150 case BFD_RELOC_8_GOT_PCREL:
1151 case BFD_RELOC_16_GOT_PCREL:
1152 case BFD_RELOC_32_GOT_PCREL:
1153 case BFD_RELOC_8_GOTOFF:
1154 case BFD_RELOC_16_GOTOFF:
1155 case BFD_RELOC_32_GOTOFF:
1156 case BFD_RELOC_8_PLT_PCREL:
1157 case BFD_RELOC_16_PLT_PCREL:
1158 case BFD_RELOC_32_PLT_PCREL:
1159 case BFD_RELOC_8_PLTOFF:
1160 case BFD_RELOC_16_PLTOFF:
1161 case BFD_RELOC_32_PLTOFF:
1162 case BFD_RELOC_68K_TLS_GD32:
1163 case BFD_RELOC_68K_TLS_GD16:
1164 case BFD_RELOC_68K_TLS_GD8:
1165 case BFD_RELOC_68K_TLS_LDM32:
1166 case BFD_RELOC_68K_TLS_LDM16:
1167 case BFD_RELOC_68K_TLS_LDM8:
1168 case BFD_RELOC_68K_TLS_LDO32:
1169 case BFD_RELOC_68K_TLS_LDO16:
1170 case BFD_RELOC_68K_TLS_LDO8:
1171 case BFD_RELOC_68K_TLS_IE32:
1172 case BFD_RELOC_68K_TLS_IE16:
1173 case BFD_RELOC_68K_TLS_IE8:
1174 case BFD_RELOC_68K_TLS_LE32:
1175 case BFD_RELOC_68K_TLS_LE16:
1176 case BFD_RELOC_68K_TLS_LE8:
1177 return 0;
1178
1179 case BFD_RELOC_VTABLE_INHERIT:
1180 case BFD_RELOC_VTABLE_ENTRY:
1181 return 0;
1182
1183 default:
1184 return 1;
1185 }
1186 }
1187
1188 arelent *
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)1189 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1190 {
1191 arelent *reloc;
1192 bfd_reloc_code_real_type code;
1193
1194 /* If the tcbit is set, then this was a fixup of a negative value
1195 that was never resolved. We do not have a reloc to handle this,
1196 so just return. We assume that other code will have detected this
1197 situation and produced a helpful error message, so we just tell the
1198 user that the reloc cannot be produced. */
1199 if (fixp->fx_tcbit)
1200 {
1201 if (fixp->fx_addsy)
1202 as_bad_where (fixp->fx_file, fixp->fx_line,
1203 _("Unable to produce reloc against symbol '%s'"),
1204 S_GET_NAME (fixp->fx_addsy));
1205 return NULL;
1206 }
1207
1208 if (fixp->fx_r_type != BFD_RELOC_NONE)
1209 {
1210 code = fixp->fx_r_type;
1211
1212 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1213 that fixup_segment converted a non-PC relative reloc into a
1214 PC relative reloc. In such a case, we need to convert the
1215 reloc code. */
1216 if (fixp->fx_pcrel)
1217 {
1218 switch (code)
1219 {
1220 case BFD_RELOC_8:
1221 code = BFD_RELOC_8_PCREL;
1222 break;
1223 case BFD_RELOC_16:
1224 code = BFD_RELOC_16_PCREL;
1225 break;
1226 case BFD_RELOC_32:
1227 code = BFD_RELOC_32_PCREL;
1228 break;
1229 case BFD_RELOC_8_PCREL:
1230 case BFD_RELOC_16_PCREL:
1231 case BFD_RELOC_32_PCREL:
1232 case BFD_RELOC_8_GOT_PCREL:
1233 case BFD_RELOC_16_GOT_PCREL:
1234 case BFD_RELOC_32_GOT_PCREL:
1235 case BFD_RELOC_8_GOTOFF:
1236 case BFD_RELOC_16_GOTOFF:
1237 case BFD_RELOC_32_GOTOFF:
1238 case BFD_RELOC_8_PLT_PCREL:
1239 case BFD_RELOC_16_PLT_PCREL:
1240 case BFD_RELOC_32_PLT_PCREL:
1241 case BFD_RELOC_8_PLTOFF:
1242 case BFD_RELOC_16_PLTOFF:
1243 case BFD_RELOC_32_PLTOFF:
1244 case BFD_RELOC_68K_TLS_GD32:
1245 case BFD_RELOC_68K_TLS_GD16:
1246 case BFD_RELOC_68K_TLS_GD8:
1247 case BFD_RELOC_68K_TLS_LDM32:
1248 case BFD_RELOC_68K_TLS_LDM16:
1249 case BFD_RELOC_68K_TLS_LDM8:
1250 case BFD_RELOC_68K_TLS_LDO32:
1251 case BFD_RELOC_68K_TLS_LDO16:
1252 case BFD_RELOC_68K_TLS_LDO8:
1253 case BFD_RELOC_68K_TLS_IE32:
1254 case BFD_RELOC_68K_TLS_IE16:
1255 case BFD_RELOC_68K_TLS_IE8:
1256 case BFD_RELOC_68K_TLS_LE32:
1257 case BFD_RELOC_68K_TLS_LE16:
1258 case BFD_RELOC_68K_TLS_LE8:
1259 break;
1260 default:
1261 as_bad_where (fixp->fx_file, fixp->fx_line,
1262 _("Cannot make %s relocation PC relative"),
1263 bfd_get_reloc_code_name (code));
1264 }
1265 }
1266 }
1267 else
1268 {
1269 #define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1270 switch (F (fixp->fx_size, fixp->fx_pcrel))
1271 {
1272 #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1273 MAP (1, 0, BFD_RELOC_8);
1274 MAP (2, 0, BFD_RELOC_16);
1275 MAP (4, 0, BFD_RELOC_32);
1276 MAP (1, 1, BFD_RELOC_8_PCREL);
1277 MAP (2, 1, BFD_RELOC_16_PCREL);
1278 MAP (4, 1, BFD_RELOC_32_PCREL);
1279 default:
1280 abort ();
1281 }
1282 }
1283 #undef F
1284 #undef MAP
1285
1286 reloc = XNEW (arelent);
1287 reloc->sym_ptr_ptr = XNEW (asymbol *);
1288 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1289 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1290 if (!fixp->fx_pcrel)
1291 reloc->addend = fixp->fx_addnumber;
1292 else
1293 reloc->addend = (section->vma
1294 + fixp->fx_pcrel_adjust
1295 + fixp->fx_addnumber
1296 + md_pcrel_from (fixp));
1297
1298 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1299 gas_assert (reloc->howto != 0);
1300
1301 return reloc;
1302 }
1303
1304 /* Handle of the OPCODE hash table. NULL means any use before
1305 m68k_ip_begin() will crash. */
1306 static htab_t op_hash;
1307
1308 /* Assemble an m68k instruction. */
1309
1310 static void
m68k_ip(char * instring)1311 m68k_ip (char *instring)
1312 {
1313 char *p;
1314 struct m68k_op *opP;
1315 const struct m68k_incant *opcode;
1316 const char *s;
1317 int tmpreg = 0, baseo = 0, outro = 0, nextword;
1318 char *pdot, *pdotmove;
1319 enum m68k_size siz1, siz2;
1320 char c;
1321 int losing;
1322 int opsfound;
1323 struct m68k_op operands_backup[6];
1324 LITTLENUM_TYPE words[6];
1325 LITTLENUM_TYPE *wordp;
1326 unsigned long ok_arch = 0;
1327
1328 if (*instring == ' ')
1329 instring++; /* Skip leading whitespace. */
1330
1331 /* Scan up to end of operation-code, which MUST end in end-of-string
1332 or exactly 1 space. */
1333 pdot = 0;
1334 for (p = instring; *p != '\0'; p++)
1335 {
1336 if (*p == ' ')
1337 break;
1338 if (*p == '.')
1339 pdot = p;
1340 }
1341
1342 if (p == instring)
1343 {
1344 the_ins.error = _("No operator");
1345 return;
1346 }
1347
1348 /* p now points to the end of the opcode name, probably whitespace.
1349 Make sure the name is null terminated by clobbering the
1350 whitespace, look it up in the hash table, then fix it back.
1351 Remove a dot, first, since the opcode tables have none. */
1352 if (pdot != NULL)
1353 {
1354 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1355 *pdotmove = pdotmove[1];
1356 p--;
1357 }
1358
1359 c = *p;
1360 *p = '\0';
1361 opcode = (const struct m68k_incant *) str_hash_find (op_hash, instring);
1362 *p = c;
1363
1364 if (pdot != NULL)
1365 {
1366 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1367 *pdotmove = pdotmove[-1];
1368 *pdot = '.';
1369 ++p;
1370 }
1371
1372 if (opcode == NULL)
1373 {
1374 the_ins.error = _("Unknown operator");
1375 return;
1376 }
1377
1378 /* Found a legitimate opcode, start matching operands. */
1379 while (*p == ' ')
1380 ++p;
1381
1382 if (opcode->m_operands == 0)
1383 {
1384 char *old = input_line_pointer;
1385 *old = '\n';
1386 input_line_pointer = p;
1387 /* Ahh - it's a motorola style pseudo op. */
1388 mote_pseudo_table[opcode->m_opnum].poc_handler
1389 (mote_pseudo_table[opcode->m_opnum].poc_val);
1390 input_line_pointer = old;
1391 *old = 0;
1392
1393 return;
1394 }
1395
1396 if (flag_mri && opcode->m_opnum == 0)
1397 {
1398 /* In MRI mode, random garbage is allowed after an instruction
1399 which accepts no operands. */
1400 the_ins.args = opcode->m_operands;
1401 the_ins.numargs = opcode->m_opnum;
1402 the_ins.numo = opcode->m_codenum;
1403 the_ins.opcode[0] = getone (opcode);
1404 the_ins.opcode[1] = gettwo (opcode);
1405 return;
1406 }
1407
1408 for (opP = &the_ins.operands[0]; *p; opP++)
1409 {
1410 p = crack_operand (p, opP);
1411
1412 if (opP->error)
1413 {
1414 the_ins.error = opP->error;
1415 return;
1416 }
1417 }
1418
1419 opsfound = opP - &the_ins.operands[0];
1420
1421 /* This ugly hack is to support the floating pt opcodes in their
1422 standard form. Essentially, we fake a first entry of type COP#1 */
1423 if (opcode->m_operands[0] == 'I')
1424 {
1425 int n;
1426
1427 for (n = opsfound; n > 0; --n)
1428 the_ins.operands[n] = the_ins.operands[n - 1];
1429
1430 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1431 the_ins.operands[0].mode = CONTROL;
1432 the_ins.operands[0].reg = m68k_float_copnum;
1433 opsfound++;
1434 }
1435
1436 /* We've got the operands. Find an opcode that'll accept them. */
1437 for (losing = 0;;)
1438 {
1439 /* If we didn't get the right number of ops, or we have no
1440 common model with this pattern then reject this pattern. */
1441
1442 ok_arch |= opcode->m_arch;
1443 if (opsfound != opcode->m_opnum
1444 || ((opcode->m_arch & current_architecture) == 0))
1445 ++losing;
1446 else
1447 {
1448 int i;
1449
1450 /* Make a copy of the operands of this insn so that
1451 we can modify them safely, should we want to. */
1452 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1453 for (i = 0; i < opsfound; i++)
1454 operands_backup[i] = the_ins.operands[i];
1455
1456 for (s = opcode->m_operands, opP = &operands_backup[0];
1457 *s && !losing;
1458 s += 2, opP++)
1459 {
1460 /* Warning: this switch is huge! */
1461 /* I've tried to organize the cases into this order:
1462 non-alpha first, then alpha by letter. Lower-case
1463 goes directly before uppercase counterpart. */
1464 /* Code with multiple case ...: gets sorted by the lowest
1465 case ... it belongs to. I hope this makes sense. */
1466 switch (*s)
1467 {
1468 case '!':
1469 switch (opP->mode)
1470 {
1471 case IMMED:
1472 case DREG:
1473 case AREG:
1474 case FPREG:
1475 case CONTROL:
1476 case AINC:
1477 case ADEC:
1478 case REGLST:
1479 losing++;
1480 break;
1481 default:
1482 break;
1483 }
1484 break;
1485
1486 case '<':
1487 switch (opP->mode)
1488 {
1489 case DREG:
1490 case AREG:
1491 case FPREG:
1492 case CONTROL:
1493 case IMMED:
1494 case ADEC:
1495 case REGLST:
1496 losing++;
1497 break;
1498 default:
1499 break;
1500 }
1501 break;
1502
1503 case '>':
1504 switch (opP->mode)
1505 {
1506 case DREG:
1507 case AREG:
1508 case FPREG:
1509 case CONTROL:
1510 case IMMED:
1511 case AINC:
1512 case REGLST:
1513 losing++;
1514 break;
1515 case ABSL:
1516 break;
1517 default:
1518 if (opP->reg == PC
1519 || opP->reg == ZPC)
1520 losing++;
1521 break;
1522 }
1523 break;
1524
1525 case 'm':
1526 switch (opP->mode)
1527 {
1528 case DREG:
1529 case AREG:
1530 case AINDR:
1531 case AINC:
1532 case ADEC:
1533 break;
1534 default:
1535 losing++;
1536 }
1537 break;
1538
1539 case 'n':
1540 switch (opP->mode)
1541 {
1542 case DISP:
1543 break;
1544 default:
1545 losing++;
1546 }
1547 break;
1548
1549 case 'o':
1550 switch (opP->mode)
1551 {
1552 case BASE:
1553 case ABSL:
1554 case IMMED:
1555 break;
1556 default:
1557 losing++;
1558 }
1559 break;
1560
1561 case 'p':
1562 switch (opP->mode)
1563 {
1564 case DREG:
1565 case AREG:
1566 case AINDR:
1567 case AINC:
1568 case ADEC:
1569 break;
1570 case DISP:
1571 if (opP->reg == PC || opP->reg == ZPC)
1572 losing++;
1573 break;
1574 default:
1575 losing++;
1576 }
1577 break;
1578
1579 case 'q':
1580 switch (opP->mode)
1581 {
1582 case DREG:
1583 case AINDR:
1584 case AINC:
1585 case ADEC:
1586 break;
1587 case DISP:
1588 if (opP->reg == PC || opP->reg == ZPC)
1589 losing++;
1590 break;
1591 default:
1592 losing++;
1593 break;
1594 }
1595 break;
1596
1597 case 'v':
1598 switch (opP->mode)
1599 {
1600 case DREG:
1601 case AINDR:
1602 case AINC:
1603 case ADEC:
1604 case ABSL:
1605 break;
1606 case DISP:
1607 if (opP->reg == PC || opP->reg == ZPC)
1608 losing++;
1609 break;
1610 default:
1611 losing++;
1612 break;
1613 }
1614 break;
1615
1616 case '#':
1617 if (opP->mode != IMMED)
1618 losing++;
1619 else if (s[1] == 'b'
1620 && ! isvar (&opP->disp)
1621 && (opP->disp.exp.X_op != O_constant
1622 || ! isbyte (opP->disp.exp.X_add_number)))
1623 losing++;
1624 else if (s[1] == 'B'
1625 && ! isvar (&opP->disp)
1626 && (opP->disp.exp.X_op != O_constant
1627 || ! issbyte (opP->disp.exp.X_add_number)))
1628 losing++;
1629 else if (s[1] == 'w'
1630 && ! isvar (&opP->disp)
1631 && (opP->disp.exp.X_op != O_constant
1632 || ! isword (opP->disp.exp.X_add_number)))
1633 losing++;
1634 else if (s[1] == 'W'
1635 && ! isvar (&opP->disp)
1636 && (opP->disp.exp.X_op != O_constant
1637 || ! issword (opP->disp.exp.X_add_number)))
1638 losing++;
1639 break;
1640
1641 case '^':
1642 case 'T':
1643 if (opP->mode != IMMED)
1644 losing++;
1645 break;
1646
1647 case '$':
1648 if (opP->mode == AREG
1649 || opP->mode == CONTROL
1650 || opP->mode == FPREG
1651 || opP->mode == IMMED
1652 || opP->mode == REGLST
1653 || (opP->mode != ABSL
1654 && (opP->reg == PC
1655 || opP->reg == ZPC)))
1656 losing++;
1657 break;
1658
1659 case '%':
1660 if (opP->mode == CONTROL
1661 || opP->mode == FPREG
1662 || opP->mode == REGLST
1663 || opP->mode == IMMED
1664 || (opP->mode != ABSL
1665 && (opP->reg == PC
1666 || opP->reg == ZPC)))
1667 losing++;
1668 break;
1669
1670 case '&':
1671 switch (opP->mode)
1672 {
1673 case DREG:
1674 case AREG:
1675 case FPREG:
1676 case CONTROL:
1677 case IMMED:
1678 case AINC:
1679 case ADEC:
1680 case REGLST:
1681 losing++;
1682 break;
1683 case ABSL:
1684 break;
1685 default:
1686 if (opP->reg == PC
1687 || opP->reg == ZPC)
1688 losing++;
1689 break;
1690 }
1691 break;
1692
1693 case '*':
1694 if (opP->mode == CONTROL
1695 || opP->mode == FPREG
1696 || opP->mode == REGLST)
1697 losing++;
1698 break;
1699
1700 case '+':
1701 if (opP->mode != AINC)
1702 losing++;
1703 break;
1704
1705 case '-':
1706 if (opP->mode != ADEC)
1707 losing++;
1708 break;
1709
1710 case '/':
1711 switch (opP->mode)
1712 {
1713 case AREG:
1714 case CONTROL:
1715 case FPREG:
1716 case AINC:
1717 case ADEC:
1718 case IMMED:
1719 case REGLST:
1720 losing++;
1721 break;
1722 default:
1723 break;
1724 }
1725 break;
1726
1727 case ';':
1728 switch (opP->mode)
1729 {
1730 case AREG:
1731 case CONTROL:
1732 case FPREG:
1733 case REGLST:
1734 losing++;
1735 break;
1736 default:
1737 break;
1738 }
1739 break;
1740
1741 case '?':
1742 switch (opP->mode)
1743 {
1744 case AREG:
1745 case CONTROL:
1746 case FPREG:
1747 case AINC:
1748 case ADEC:
1749 case IMMED:
1750 case REGLST:
1751 losing++;
1752 break;
1753 case ABSL:
1754 break;
1755 default:
1756 if (opP->reg == PC || opP->reg == ZPC)
1757 losing++;
1758 break;
1759 }
1760 break;
1761
1762 case '@':
1763 switch (opP->mode)
1764 {
1765 case AREG:
1766 case CONTROL:
1767 case FPREG:
1768 case IMMED:
1769 case REGLST:
1770 losing++;
1771 break;
1772 default:
1773 break;
1774 }
1775 break;
1776
1777 case '~': /* For now! (JF FOO is this right?) */
1778 switch (opP->mode)
1779 {
1780 case DREG:
1781 case AREG:
1782 case CONTROL:
1783 case FPREG:
1784 case IMMED:
1785 case REGLST:
1786 losing++;
1787 break;
1788 case ABSL:
1789 break;
1790 default:
1791 if (opP->reg == PC
1792 || opP->reg == ZPC)
1793 losing++;
1794 break;
1795 }
1796 break;
1797
1798 case '3':
1799 if (opP->mode != CONTROL
1800 || (opP->reg != TT0 && opP->reg != TT1))
1801 losing++;
1802 break;
1803
1804 case 'A':
1805 if (opP->mode != AREG)
1806 losing++;
1807 break;
1808
1809 case 'a':
1810 if (opP->mode != AINDR)
1811 ++losing;
1812 break;
1813
1814 case '4':
1815 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1816 && (opP->mode != DISP
1817 || opP->reg < ADDR0
1818 || opP->reg > ADDR7))
1819 ++losing;
1820 break;
1821
1822 case 'B': /* FOO */
1823 if (opP->mode != ABSL
1824 || (flag_long_jumps
1825 && startswith (instring, "jbsr")))
1826 losing++;
1827 break;
1828
1829 case 'b':
1830 switch (opP->mode)
1831 {
1832 case IMMED:
1833 case ABSL:
1834 case AREG:
1835 case FPREG:
1836 case CONTROL:
1837 case POST:
1838 case PRE:
1839 case REGLST:
1840 losing++;
1841 break;
1842 default:
1843 break;
1844 }
1845 break;
1846
1847 case 'C':
1848 if (opP->mode != CONTROL || opP->reg != CCR)
1849 losing++;
1850 break;
1851
1852 case 'd':
1853 if (opP->mode != DISP
1854 || opP->reg < ADDR0
1855 || opP->reg > ADDR7)
1856 losing++;
1857 break;
1858
1859 case 'D':
1860 if (opP->mode != DREG)
1861 losing++;
1862 break;
1863
1864 case 'E':
1865 if (opP->reg != ACC)
1866 losing++;
1867 break;
1868
1869 case 'e':
1870 if (opP->reg != ACC && opP->reg != ACC1
1871 && opP->reg != ACC2 && opP->reg != ACC3)
1872 losing++;
1873 break;
1874
1875 case 'F':
1876 if (opP->mode != FPREG)
1877 losing++;
1878 break;
1879
1880 case 'G':
1881 if (opP->reg != MACSR)
1882 losing++;
1883 break;
1884
1885 case 'g':
1886 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1887 losing++;
1888 break;
1889
1890 case 'H':
1891 if (opP->reg != MASK)
1892 losing++;
1893 break;
1894
1895 case 'I':
1896 if (opP->mode != CONTROL
1897 || opP->reg < COP0
1898 || opP->reg > COP7)
1899 losing++;
1900 break;
1901
1902 case 'i':
1903 if (opP->mode != LSH && opP->mode != RSH)
1904 losing++;
1905 break;
1906
1907 case 'J':
1908 if (opP->mode != CONTROL
1909 || opP->reg < USP
1910 || opP->reg > last_movec_reg
1911 || !control_regs)
1912 losing++;
1913 else
1914 {
1915 const enum m68k_register *rp;
1916
1917 for (rp = control_regs; *rp; rp++)
1918 {
1919 if (*rp == opP->reg)
1920 break;
1921 /* In most CPUs RAMBAR refers to control reg
1922 c05 (RAMBAR1), but a few CPUs have it
1923 refer to c04 (RAMBAR0). */
1924 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1925 {
1926 opP->reg = RAMBAR_ALT;
1927 break;
1928 }
1929 }
1930 if (*rp == 0)
1931 losing++;
1932 }
1933 break;
1934
1935 case 'k':
1936 if (opP->mode != IMMED)
1937 losing++;
1938 break;
1939
1940 case 'l':
1941 case 'L':
1942 if (opP->mode == DREG
1943 || opP->mode == AREG
1944 || opP->mode == FPREG)
1945 {
1946 if (s[1] == '8')
1947 losing++;
1948 else
1949 {
1950 switch (opP->mode)
1951 {
1952 case DREG:
1953 opP->mask = 1 << (opP->reg - DATA0);
1954 break;
1955 case AREG:
1956 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1957 break;
1958 case FPREG:
1959 opP->mask = 1 << (opP->reg - FP0 + 16);
1960 break;
1961 default:
1962 abort ();
1963 }
1964 opP->mode = REGLST;
1965 }
1966 }
1967 else if (opP->mode == CONTROL)
1968 {
1969 if (s[1] != '8')
1970 losing++;
1971 else
1972 {
1973 switch (opP->reg)
1974 {
1975 case FPI:
1976 opP->mask = 1 << 24;
1977 break;
1978 case FPS:
1979 opP->mask = 1 << 25;
1980 break;
1981 case FPC:
1982 opP->mask = 1 << 26;
1983 break;
1984 default:
1985 losing++;
1986 break;
1987 }
1988 opP->mode = REGLST;
1989 }
1990 }
1991 else if (opP->mode != REGLST)
1992 losing++;
1993 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1994 losing++;
1995 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1996 losing++;
1997 break;
1998
1999 case 'M':
2000 if (opP->mode != IMMED)
2001 losing++;
2002 else if (opP->disp.exp.X_op != O_constant
2003 || ! issbyte (opP->disp.exp.X_add_number))
2004 losing++;
2005 else if (! m68k_quick
2006 && instring[3] != 'q'
2007 && instring[4] != 'q')
2008 losing++;
2009 break;
2010
2011 case 'O':
2012 if (opP->mode != DREG
2013 && opP->mode != IMMED
2014 && opP->mode != ABSL)
2015 losing++;
2016 break;
2017
2018 case 'Q':
2019 if (opP->mode != IMMED)
2020 losing++;
2021 else if (opP->disp.exp.X_op != O_constant
2022 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2023 losing++;
2024 else if (! m68k_quick
2025 && (startswith (instring, "add")
2026 || startswith (instring, "sub"))
2027 && instring[3] != 'q')
2028 losing++;
2029 break;
2030
2031 case 'R':
2032 if (opP->mode != DREG && opP->mode != AREG)
2033 losing++;
2034 break;
2035
2036 case 'r':
2037 if (opP->mode != AINDR
2038 && (opP->mode != BASE
2039 || (opP->reg != 0
2040 && opP->reg != ZADDR0)
2041 || opP->disp.exp.X_op != O_absent
2042 || ((opP->index.reg < DATA0
2043 || opP->index.reg > DATA7)
2044 && (opP->index.reg < ADDR0
2045 || opP->index.reg > ADDR7))
2046 || opP->index.size != SIZE_UNSPEC
2047 || opP->index.scale != 1))
2048 losing++;
2049 break;
2050
2051 case 's':
2052 if (opP->mode != CONTROL
2053 || ! (opP->reg == FPI
2054 || opP->reg == FPS
2055 || opP->reg == FPC))
2056 losing++;
2057 break;
2058
2059 case 'S':
2060 if (opP->mode != CONTROL || opP->reg != SR)
2061 losing++;
2062 break;
2063
2064 case 't':
2065 if (opP->mode != IMMED)
2066 losing++;
2067 else if (opP->disp.exp.X_op != O_constant
2068 || TRUNC (opP->disp.exp.X_add_number) > 7)
2069 losing++;
2070 break;
2071
2072 case 'U':
2073 if (opP->mode != CONTROL || opP->reg != USP)
2074 losing++;
2075 break;
2076
2077 case 'x':
2078 if (opP->mode != IMMED)
2079 losing++;
2080 else if (opP->disp.exp.X_op != O_constant
2081 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2082 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2083 losing++;
2084 break;
2085
2086 case 'j':
2087 if (opP->mode != IMMED)
2088 losing++;
2089 else if (opP->disp.exp.X_op != O_constant
2090 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2091 losing++;
2092 break;
2093
2094 case 'K':
2095 if (opP->mode != IMMED)
2096 losing++;
2097 else if (opP->disp.exp.X_op != O_constant
2098 || TRUNC (opP->disp.exp.X_add_number) > 511)
2099 losing++;
2100 break;
2101
2102 /* JF these are out of order. We could put them
2103 in order if we were willing to put up with
2104 bunches of #ifdef m68851s in the code.
2105
2106 Don't forget that you need these operands
2107 to use 68030 MMU instructions. */
2108 #ifndef NO_68851
2109 /* Memory addressing mode used by pflushr. */
2110 case '|':
2111 if (opP->mode == CONTROL
2112 || opP->mode == FPREG
2113 || opP->mode == DREG
2114 || opP->mode == AREG
2115 || opP->mode == REGLST)
2116 losing++;
2117 /* We should accept immediate operands, but they
2118 supposedly have to be quad word, and we don't
2119 handle that. I would like to see what a Motorola
2120 assembler does before doing something here. */
2121 if (opP->mode == IMMED)
2122 losing++;
2123 break;
2124
2125 case 'f':
2126 if (opP->mode != CONTROL
2127 || (opP->reg != SFC && opP->reg != DFC))
2128 losing++;
2129 break;
2130
2131 case '0':
2132 if (opP->mode != CONTROL || opP->reg != TC)
2133 losing++;
2134 break;
2135
2136 case '1':
2137 if (opP->mode != CONTROL || opP->reg != AC)
2138 losing++;
2139 break;
2140
2141 case '2':
2142 if (opP->mode != CONTROL
2143 || (opP->reg != CAL
2144 && opP->reg != VAL
2145 && opP->reg != SCC))
2146 losing++;
2147 break;
2148
2149 case 'V':
2150 if (opP->mode != CONTROL
2151 || opP->reg != VAL)
2152 losing++;
2153 break;
2154
2155 case 'W':
2156 if (opP->mode != CONTROL
2157 || (opP->reg != DRP
2158 && opP->reg != SRP
2159 && opP->reg != CRP))
2160 losing++;
2161 break;
2162
2163 case 'w':
2164 switch (opP->mode)
2165 {
2166 case IMMED:
2167 case ABSL:
2168 case AREG:
2169 case DREG:
2170 case FPREG:
2171 case CONTROL:
2172 case POST:
2173 case PRE:
2174 case REGLST:
2175 losing++;
2176 break;
2177 default:
2178 break;
2179 }
2180 break;
2181
2182 case 'X':
2183 if (opP->mode != CONTROL
2184 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2185 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2186 losing++;
2187 break;
2188
2189 case 'Y':
2190 if (opP->mode != CONTROL || opP->reg != PSR)
2191 losing++;
2192 break;
2193
2194 case 'Z':
2195 if (opP->mode != CONTROL || opP->reg != PCSR)
2196 losing++;
2197 break;
2198 #endif
2199 case 'c':
2200 if (opP->mode != CONTROL
2201 || (opP->reg != NC
2202 && opP->reg != IC
2203 && opP->reg != DC
2204 && opP->reg != BC))
2205 losing++;
2206 break;
2207
2208 case '_':
2209 if (opP->mode != ABSL)
2210 ++losing;
2211 break;
2212
2213 case 'u':
2214 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2215 losing++;
2216 /* FIXME: kludge instead of fixing parser:
2217 upper/lower registers are *not* CONTROL
2218 registers, but ordinary ones. */
2219 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2220 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2221 opP->mode = DREG;
2222 else
2223 opP->mode = AREG;
2224 break;
2225
2226 case 'y':
2227 if (!(opP->mode == AINDR
2228 || (opP->mode == DISP
2229 && !(opP->reg == PC || opP->reg == ZPC))))
2230 losing++;
2231 break;
2232
2233 case 'z':
2234 if (!(opP->mode == AINDR || opP->mode == DISP))
2235 losing++;
2236 break;
2237
2238 default:
2239 abort ();
2240 }
2241
2242 if (losing)
2243 break;
2244 }
2245
2246 /* Since we have found the correct instruction, copy
2247 in the modifications that we may have made. */
2248 if (!losing)
2249 for (i = 0; i < opsfound; i++)
2250 the_ins.operands[i] = operands_backup[i];
2251 }
2252
2253 if (!losing)
2254 break;
2255
2256 opcode = opcode->m_next;
2257
2258 if (!opcode)
2259 {
2260 if (ok_arch
2261 && !(ok_arch & current_architecture))
2262 {
2263 const struct m68k_cpu *cpu;
2264 int any = 0;
2265 size_t space = 400;
2266 char *buf = XNEWVEC (char, space + 1);
2267 size_t len;
2268 int paren = 1;
2269
2270 the_ins.error = buf;
2271 /* Make sure there's a NUL at the end of the buffer -- strncpy
2272 won't write one when it runs out of buffer. */
2273 buf[space] = 0;
2274 #define APPEND(STRING) \
2275 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2276
2277 APPEND (_("invalid instruction for this architecture; needs "));
2278 switch (ok_arch)
2279 {
2280 case mcfisa_a:
2281 APPEND ("ColdFire ISA_A");
2282 break;
2283 case mcfhwdiv:
2284 APPEND ("ColdFire ");
2285 APPEND (_("hardware divide"));
2286 break;
2287 case mcfisa_aa:
2288 APPEND ("ColdFire ISA_A+");
2289 break;
2290 case mcfisa_b:
2291 APPEND ("ColdFire ISA_B");
2292 break;
2293 case mcfisa_c:
2294 APPEND ("ColdFire ISA_C");
2295 break;
2296 case cfloat:
2297 APPEND ("ColdFire fpu");
2298 break;
2299 case mfloat:
2300 APPEND ("M68K fpu");
2301 break;
2302 case mmmu:
2303 APPEND ("M68K mmu");
2304 break;
2305 case m68020up:
2306 APPEND ("68020 ");
2307 APPEND (_("or higher"));
2308 break;
2309 case m68000up:
2310 APPEND ("68000 ");
2311 APPEND (_("or higher"));
2312 break;
2313 case m68010up:
2314 APPEND ("68010 ");
2315 APPEND (_("or higher"));
2316 break;
2317 default:
2318 paren = 0;
2319 }
2320 if (paren)
2321 APPEND (" (");
2322
2323 for (cpu = m68k_cpus; cpu->name; cpu++)
2324 if (!cpu->alias && (cpu->arch & ok_arch))
2325 {
2326 const struct m68k_cpu *alias;
2327 int seen_master = 0;
2328
2329 if (any)
2330 APPEND (", ");
2331 any = 0;
2332 APPEND (cpu->name);
2333 for (alias = cpu; alias != m68k_cpus; alias--)
2334 if (alias[-1].alias >= 0)
2335 break;
2336 for (; !seen_master || alias->alias > 0; alias++)
2337 {
2338 if (!alias->alias)
2339 seen_master = 1;
2340 else
2341 {
2342 if (any)
2343 APPEND (", ");
2344 else
2345 APPEND (" [");
2346 APPEND (alias->name);
2347 any = 1;
2348 }
2349 }
2350 if (any)
2351 APPEND ("]");
2352 any = 1;
2353 }
2354 if (paren)
2355 APPEND (")");
2356 #undef APPEND
2357 if (!space)
2358 {
2359 /* We ran out of space, so replace the end of the list
2360 with ellipsis. */
2361 buf -= 4;
2362 while (*buf != ' ')
2363 buf--;
2364 strcpy (buf, " ...");
2365 }
2366 }
2367 else
2368 the_ins.error = _("operands mismatch");
2369 return;
2370 }
2371
2372 losing = 0;
2373 }
2374
2375 /* Now assemble it. */
2376 the_ins.args = opcode->m_operands;
2377 the_ins.numargs = opcode->m_opnum;
2378 the_ins.numo = opcode->m_codenum;
2379 the_ins.opcode[0] = getone (opcode);
2380 the_ins.opcode[1] = gettwo (opcode);
2381
2382 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2383 {
2384 int have_disp = 0;
2385 int use_pl = 0;
2386
2387 /* This switch is a doozy.
2388 Watch the first step; it's a big one! */
2389 switch (s[0])
2390 {
2391
2392 case '*':
2393 case '~':
2394 case '%':
2395 case ';':
2396 case '@':
2397 case '!':
2398 case '&':
2399 case '$':
2400 case '?':
2401 case '/':
2402 case '<':
2403 case '>':
2404 case 'b':
2405 case 'm':
2406 case 'n':
2407 case 'o':
2408 case 'p':
2409 case 'q':
2410 case 'v':
2411 case 'w':
2412 case 'y':
2413 case 'z':
2414 case '4':
2415 #ifndef NO_68851
2416 case '|':
2417 #endif
2418 switch (opP->mode)
2419 {
2420 case IMMED:
2421 tmpreg = 0x3c; /* 7.4 */
2422 if (strchr ("bwl", s[1]))
2423 nextword = get_num (&opP->disp, 90);
2424 else
2425 nextword = get_num (&opP->disp, 0);
2426 if (isvar (&opP->disp))
2427 add_fix (s[1], &opP->disp, 0, 0);
2428 switch (s[1])
2429 {
2430 case 'b':
2431 if (!isbyte (nextword))
2432 opP->error = _("operand out of range");
2433 addword (nextword);
2434 baseo = 0;
2435 break;
2436 case 'w':
2437 if (!isword (nextword))
2438 opP->error = _("operand out of range");
2439 addword (nextword);
2440 baseo = 0;
2441 break;
2442 case 'W':
2443 if (!issword (nextword))
2444 opP->error = _("operand out of range");
2445 addword (nextword);
2446 baseo = 0;
2447 break;
2448 case 'l':
2449 addword (nextword >> 16);
2450 addword (nextword);
2451 baseo = 0;
2452 break;
2453
2454 case 'f':
2455 baseo = 2;
2456 outro = 8;
2457 break;
2458 case 'F':
2459 baseo = 4;
2460 outro = 11;
2461 break;
2462 case 'x':
2463 baseo = 6;
2464 outro = 15;
2465 break;
2466 case 'p':
2467 baseo = 6;
2468 outro = -1;
2469 break;
2470 default:
2471 abort ();
2472 }
2473 if (!baseo)
2474 break;
2475
2476 /* We gotta put out some float. */
2477 if (op (&opP->disp) != O_big)
2478 {
2479 valueT val;
2480 int gencnt;
2481
2482 /* Can other cases happen here? */
2483 if (op (&opP->disp) != O_constant)
2484 abort ();
2485
2486 val = (valueT) offs (&opP->disp);
2487 gencnt = 0;
2488 do
2489 {
2490 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2491 val >>= LITTLENUM_NUMBER_OF_BITS;
2492 ++gencnt;
2493 }
2494 while (val != 0);
2495 offs (&opP->disp) = gencnt;
2496 }
2497 if (offs (&opP->disp) > 0)
2498 {
2499 if (offs (&opP->disp) > baseo)
2500 {
2501 as_warn (_("Bignum too big for %c format; truncated"),
2502 s[1]);
2503 offs (&opP->disp) = baseo;
2504 }
2505 baseo -= offs (&opP->disp);
2506 while (baseo--)
2507 addword (0);
2508 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2509 offs (&opP->disp)--;
2510 --wordp)
2511 addword (*wordp);
2512 break;
2513 }
2514 gen_to_words (words, baseo, (long) outro);
2515 for (wordp = words; baseo--; wordp++)
2516 addword (*wordp);
2517 break;
2518 case DREG:
2519 tmpreg = opP->reg - DATA; /* 0.dreg */
2520 break;
2521 case AREG:
2522 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2523 break;
2524 case AINDR:
2525 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2526 break;
2527 case ADEC:
2528 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2529 break;
2530 case AINC:
2531 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2532 break;
2533 case DISP:
2534
2535 nextword = get_num (&opP->disp, 90);
2536
2537 /* Convert mode 5 addressing with a zero offset into
2538 mode 2 addressing to reduce the instruction size by a
2539 word. */
2540 if (! isvar (&opP->disp)
2541 && (nextword == 0)
2542 && (opP->disp.size == SIZE_UNSPEC)
2543 && (opP->reg >= ADDR0)
2544 && (opP->reg <= ADDR7))
2545 {
2546 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2547 break;
2548 }
2549
2550 if (opP->reg == PC
2551 && ! isvar (&opP->disp)
2552 && m68k_abspcadd)
2553 {
2554 opP->disp.exp.X_op = O_symbol;
2555 opP->disp.exp.X_add_symbol =
2556 section_symbol (absolute_section);
2557 }
2558
2559 /* Force into index mode. Hope this works. */
2560
2561 /* We do the first bit for 32-bit displacements, and the
2562 second bit for 16 bit ones. It is possible that we
2563 should make the default be WORD instead of LONG, but
2564 I think that'd break GCC, so we put up with a little
2565 inefficiency for the sake of working output. */
2566
2567 if (!issword (nextword)
2568 || (isvar (&opP->disp)
2569 && ((opP->disp.size == SIZE_UNSPEC
2570 && flag_short_refs == 0
2571 && cpu_of_arch (current_architecture) >= m68020
2572 && ! arch_coldfire_p (current_architecture))
2573 || opP->disp.size == SIZE_LONG)))
2574 {
2575 if (cpu_of_arch (current_architecture) < m68020
2576 || arch_coldfire_p (current_architecture))
2577 opP->error =
2578 _("displacement too large for this architecture; needs 68020 or higher");
2579 if (opP->reg == PC)
2580 tmpreg = 0x3B; /* 7.3 */
2581 else
2582 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2583 if (isvar (&opP->disp))
2584 {
2585 if (opP->reg == PC)
2586 {
2587 if (opP->disp.size == SIZE_LONG
2588 /* If the displacement needs pic
2589 relocation it cannot be relaxed. */
2590 || opP->disp.pic_reloc != pic_none)
2591 {
2592 addword (0x0170);
2593 add_fix ('l', &opP->disp, 1, 2);
2594 }
2595 else
2596 {
2597 add_frag (adds (&opP->disp),
2598 SEXT (offs (&opP->disp)),
2599 TAB (PCREL1632, SZ_UNDEF));
2600 break;
2601 }
2602 }
2603 else
2604 {
2605 addword (0x0170);
2606 add_fix ('l', &opP->disp, 0, 0);
2607 }
2608 }
2609 else
2610 addword (0x0170);
2611 addword (nextword >> 16);
2612 }
2613 else
2614 {
2615 if (opP->reg == PC)
2616 tmpreg = 0x3A; /* 7.2 */
2617 else
2618 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2619
2620 if (isvar (&opP->disp))
2621 {
2622 if (opP->reg == PC)
2623 {
2624 add_fix ('w', &opP->disp, 1, 0);
2625 }
2626 else
2627 add_fix ('w', &opP->disp, 0, 0);
2628 }
2629 }
2630 addword (nextword);
2631 break;
2632
2633 case POST:
2634 case PRE:
2635 case BASE:
2636 nextword = 0;
2637 baseo = get_num (&opP->disp, 90);
2638 if (opP->mode == POST || opP->mode == PRE)
2639 outro = get_num (&opP->odisp, 90);
2640 /* Figure out the `addressing mode'.
2641 Also turn on the BASE_DISABLE bit, if needed. */
2642 if (opP->reg == PC || opP->reg == ZPC)
2643 {
2644 tmpreg = 0x3b; /* 7.3 */
2645 if (opP->reg == ZPC)
2646 nextword |= 0x80;
2647 }
2648 else if (opP->reg == 0)
2649 {
2650 nextword |= 0x80;
2651 tmpreg = 0x30; /* 6.garbage */
2652 }
2653 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2654 {
2655 nextword |= 0x80;
2656 tmpreg = 0x30 + opP->reg - ZADDR0;
2657 }
2658 else
2659 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2660
2661 siz1 = opP->disp.size;
2662 if (opP->mode == POST || opP->mode == PRE)
2663 siz2 = opP->odisp.size;
2664 else
2665 siz2 = SIZE_UNSPEC;
2666
2667 /* Index register stuff. */
2668 if (opP->index.reg != 0
2669 && opP->index.reg >= DATA
2670 && opP->index.reg <= ADDR7)
2671 {
2672 nextword |= (opP->index.reg - DATA) << 12;
2673
2674 if (opP->index.size == SIZE_LONG
2675 || (opP->index.size == SIZE_UNSPEC
2676 && m68k_index_width_default == SIZE_LONG))
2677 nextword |= 0x800;
2678
2679 if ((opP->index.scale != 1
2680 && cpu_of_arch (current_architecture) < m68020)
2681 || (opP->index.scale == 8
2682 && (arch_coldfire_p (current_architecture)
2683 && !arch_coldfire_fpu (current_architecture))))
2684 {
2685 opP->error =
2686 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2687 }
2688
2689 if (arch_coldfire_p (current_architecture)
2690 && opP->index.size == SIZE_WORD)
2691 opP->error = _("invalid index size for coldfire");
2692
2693 switch (opP->index.scale)
2694 {
2695 case 1:
2696 break;
2697 case 2:
2698 nextword |= 0x200;
2699 break;
2700 case 4:
2701 nextword |= 0x400;
2702 break;
2703 case 8:
2704 nextword |= 0x600;
2705 break;
2706 default:
2707 abort ();
2708 }
2709 /* IF it's simple,
2710 GET US OUT OF HERE! */
2711
2712 /* Must be INDEX, with an index register. Address
2713 register cannot be ZERO-PC, and either :b was
2714 forced, or we know it will fit. For a 68000 or
2715 68010, force this mode anyways, because the
2716 larger modes aren't supported. */
2717 if (opP->mode == BASE
2718 && ((opP->reg >= ADDR0
2719 && opP->reg <= ADDR7)
2720 || opP->reg == PC))
2721 {
2722 if (siz1 == SIZE_BYTE
2723 || cpu_of_arch (current_architecture) < m68020
2724 || arch_coldfire_p (current_architecture)
2725 || (siz1 == SIZE_UNSPEC
2726 && ! isvar (&opP->disp)
2727 && issbyte (baseo)))
2728 {
2729 nextword += baseo & 0xff;
2730 addword (nextword);
2731 if (isvar (&opP->disp))
2732 {
2733 /* Do a byte relocation. If it doesn't
2734 fit (possible on m68000) let the
2735 fixup processing complain later. */
2736 if (opP->reg == PC)
2737 add_fix ('B', &opP->disp, 1, 1);
2738 else
2739 add_fix ('B', &opP->disp, 0, 0);
2740 }
2741 else if (siz1 != SIZE_BYTE)
2742 {
2743 if (siz1 != SIZE_UNSPEC)
2744 as_warn (_("Forcing byte displacement"));
2745 if (! issbyte (baseo))
2746 opP->error = _("byte displacement out of range");
2747 }
2748
2749 break;
2750 }
2751 else if (siz1 == SIZE_UNSPEC
2752 && opP->reg == PC
2753 && isvar (&opP->disp)
2754 && subs (&opP->disp) == NULL
2755 /* If the displacement needs pic
2756 relocation it cannot be relaxed. */
2757 && opP->disp.pic_reloc == pic_none)
2758 {
2759 /* The code in md_convert_frag_1 needs to be
2760 able to adjust nextword. Call frag_grow
2761 to ensure that we have enough space in
2762 the frag obstack to make all the bytes
2763 contiguous. */
2764 frag_grow (14);
2765 nextword += baseo & 0xff;
2766 addword (nextword);
2767 add_frag (adds (&opP->disp),
2768 SEXT (offs (&opP->disp)),
2769 TAB (PCINDEX, SZ_UNDEF));
2770
2771 break;
2772 }
2773 }
2774 }
2775 else
2776 {
2777 nextword |= 0x40; /* No index reg. */
2778 if (opP->index.reg >= ZDATA0
2779 && opP->index.reg <= ZDATA7)
2780 nextword |= (opP->index.reg - ZDATA0) << 12;
2781 else if (opP->index.reg >= ZADDR0
2782 && opP->index.reg <= ZADDR7)
2783 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2784 }
2785
2786 /* It isn't simple. */
2787
2788 if (cpu_of_arch (current_architecture) < m68020
2789 || arch_coldfire_p (current_architecture))
2790 opP->error =
2791 _("invalid operand mode for this architecture; needs 68020 or higher");
2792
2793 nextword |= 0x100;
2794 /* If the guy specified a width, we assume that it is
2795 wide enough. Maybe it isn't. If so, we lose. */
2796 switch (siz1)
2797 {
2798 case SIZE_UNSPEC:
2799 if (isvar (&opP->disp)
2800 ? m68k_rel32
2801 : ! issword (baseo))
2802 {
2803 siz1 = SIZE_LONG;
2804 nextword |= 0x30;
2805 }
2806 else if (! isvar (&opP->disp) && baseo == 0)
2807 nextword |= 0x10;
2808 else
2809 {
2810 nextword |= 0x20;
2811 siz1 = SIZE_WORD;
2812 }
2813 break;
2814 case SIZE_BYTE:
2815 as_warn (_(":b not permitted; defaulting to :w"));
2816 /* Fall through. */
2817 case SIZE_WORD:
2818 nextword |= 0x20;
2819 break;
2820 case SIZE_LONG:
2821 nextword |= 0x30;
2822 break;
2823 }
2824
2825 /* Figure out inner displacement stuff. */
2826 if (opP->mode == POST || opP->mode == PRE)
2827 {
2828 if (cpu_of_arch (current_architecture) & cpu32)
2829 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2830 switch (siz2)
2831 {
2832 case SIZE_UNSPEC:
2833 if (isvar (&opP->odisp)
2834 ? m68k_rel32
2835 : ! issword (outro))
2836 {
2837 siz2 = SIZE_LONG;
2838 nextword |= 0x3;
2839 }
2840 else if (! isvar (&opP->odisp) && outro == 0)
2841 nextword |= 0x1;
2842 else
2843 {
2844 nextword |= 0x2;
2845 siz2 = SIZE_WORD;
2846 }
2847 break;
2848 case 1:
2849 as_warn (_(":b not permitted; defaulting to :w"));
2850 /* Fall through. */
2851 case 2:
2852 nextword |= 0x2;
2853 break;
2854 case 3:
2855 nextword |= 0x3;
2856 break;
2857 }
2858 if (opP->mode == POST
2859 && (nextword & 0x40) == 0)
2860 nextword |= 0x04;
2861 }
2862 addword (nextword);
2863
2864 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2865 {
2866 if (opP->reg == PC || opP->reg == ZPC)
2867 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2868 else
2869 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2870 }
2871 if (siz1 == SIZE_LONG)
2872 addword (baseo >> 16);
2873 if (siz1 != SIZE_UNSPEC)
2874 addword (baseo);
2875
2876 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2877 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2878 if (siz2 == SIZE_LONG)
2879 addword (outro >> 16);
2880 if (siz2 != SIZE_UNSPEC)
2881 addword (outro);
2882
2883 break;
2884
2885 case ABSL:
2886 nextword = get_num (&opP->disp, 90);
2887 switch (opP->disp.size)
2888 {
2889 default:
2890 abort ();
2891 case SIZE_UNSPEC:
2892 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2893 {
2894 tmpreg = 0x38; /* 7.0 */
2895 addword (nextword);
2896 break;
2897 }
2898 if (isvar (&opP->disp)
2899 && !subs (&opP->disp)
2900 && adds (&opP->disp)
2901 /* If the displacement needs pic relocation it
2902 cannot be relaxed. */
2903 && opP->disp.pic_reloc == pic_none
2904 && !flag_long_jumps
2905 && !strchr ("~%&$?", s[0]))
2906 {
2907 tmpreg = 0x3A; /* 7.2 */
2908 add_frag (adds (&opP->disp),
2909 SEXT (offs (&opP->disp)),
2910 TAB (ABSTOPCREL, SZ_UNDEF));
2911 break;
2912 }
2913 /* Fall through. */
2914 case SIZE_LONG:
2915 if (isvar (&opP->disp))
2916 add_fix ('l', &opP->disp, 0, 0);
2917
2918 tmpreg = 0x39;/* 7.1 mode */
2919 addword (nextword >> 16);
2920 addword (nextword);
2921 break;
2922
2923 case SIZE_BYTE:
2924 as_bad (_("unsupported byte value; use a different suffix"));
2925 /* Fall through. */
2926
2927 case SIZE_WORD:
2928 if (isvar (&opP->disp))
2929 add_fix ('w', &opP->disp, 0, 0);
2930
2931 tmpreg = 0x38;/* 7.0 mode */
2932 addword (nextword);
2933 break;
2934 }
2935 break;
2936 case CONTROL:
2937 case FPREG:
2938 default:
2939 as_bad (_("unknown/incorrect operand"));
2940 /* abort (); */
2941 }
2942
2943 /* If s[0] is '4', then this is for the mac instructions
2944 that can have a trailing_ampersand set. If so, set 0x100
2945 bit on tmpreg so install_gen_operand can check for it and
2946 set the appropriate bit (word2, bit 5). */
2947 if (s[0] == '4')
2948 {
2949 if (opP->trailing_ampersand)
2950 tmpreg |= 0x100;
2951 }
2952 install_gen_operand (s[1], tmpreg);
2953 break;
2954
2955 case '#':
2956 case '^':
2957 switch (s[1])
2958 { /* JF: I hate floating point! */
2959 case 'j':
2960 tmpreg = 70;
2961 break;
2962 case '8':
2963 tmpreg = 20;
2964 break;
2965 case 'C':
2966 tmpreg = 50;
2967 break;
2968 case '3':
2969 default:
2970 tmpreg = 90;
2971 break;
2972 }
2973 tmpreg = get_num (&opP->disp, tmpreg);
2974 if (isvar (&opP->disp))
2975 add_fix (s[1], &opP->disp, 0, 0);
2976 switch (s[1])
2977 {
2978 case 'b': /* Danger: These do no check for
2979 certain types of overflow.
2980 user beware! */
2981 if (!isbyte (tmpreg))
2982 opP->error = _("out of range");
2983 insop (tmpreg, opcode);
2984 if (isvar (&opP->disp))
2985 the_ins.reloc[the_ins.nrel - 1].n =
2986 (opcode->m_codenum) * 2 + 1;
2987 break;
2988 case 'B':
2989 if (!issbyte (tmpreg))
2990 opP->error = _("out of range");
2991 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2992 if (isvar (&opP->disp))
2993 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2994 break;
2995 case 'w':
2996 if (!isword (tmpreg))
2997 opP->error = _("out of range");
2998 insop (tmpreg, opcode);
2999 if (isvar (&opP->disp))
3000 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3001 break;
3002 case 'W':
3003 if (!issword (tmpreg))
3004 opP->error = _("out of range");
3005 insop (tmpreg, opcode);
3006 if (isvar (&opP->disp))
3007 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3008 break;
3009 case 'l':
3010 /* Because of the way insop works, we put these two out
3011 backwards. */
3012 insop (tmpreg, opcode);
3013 insop (tmpreg >> 16, opcode);
3014 if (isvar (&opP->disp))
3015 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3016 break;
3017 case '3':
3018 tmpreg &= 0xFF;
3019 /* Fall through. */
3020 case '8':
3021 case 'C':
3022 case 'j':
3023 install_operand (s[1], tmpreg);
3024 break;
3025 default:
3026 abort ();
3027 }
3028 break;
3029
3030 case '+':
3031 case '-':
3032 case 'A':
3033 case 'a':
3034 install_operand (s[1], opP->reg - ADDR);
3035 break;
3036
3037 case 'B':
3038 tmpreg = get_num (&opP->disp, 90);
3039
3040 switch (s[1])
3041 {
3042 case 'B':
3043 add_fix ('B', &opP->disp, 1, -1);
3044 break;
3045 case 'W':
3046 add_fix ('w', &opP->disp, 1, 0);
3047 addword (0);
3048 break;
3049 case 'L':
3050 long_branch:
3051 the_ins.opcode[0] |= 0xff;
3052 add_fix ('l', &opP->disp, 1, 0);
3053 addword (0);
3054 addword (0);
3055 break;
3056 case 'g': /* Conditional branch */
3057 have_disp = HAVE_LONG_CALL (current_architecture);
3058 goto var_branch;
3059
3060 case 'b': /* Unconditional branch */
3061 have_disp = HAVE_LONG_BRANCH (current_architecture);
3062 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3063 goto var_branch;
3064
3065 case 's': /* Unconditional subroutine */
3066 have_disp = HAVE_LONG_CALL (current_architecture);
3067
3068 var_branch:
3069 if (subs (&opP->disp) /* We can't relax it. */
3070 /* If the displacement needs pic relocation it cannot be
3071 relaxed. */
3072 || opP->disp.pic_reloc != pic_none)
3073 {
3074 if (!have_disp)
3075 as_warn (_("Can't use long branches on this architecture"));
3076 goto long_branch;
3077 }
3078
3079 /* This could either be a symbol, or an absolute
3080 address. If it's an absolute address, turn it into
3081 an absolute jump right here and keep it out of the
3082 relaxer. */
3083 if (adds (&opP->disp) == 0)
3084 {
3085 if (the_ins.opcode[0] == 0x6000) /* jbra */
3086 the_ins.opcode[0] = 0x4EF9;
3087 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
3088 the_ins.opcode[0] = 0x4EB9;
3089 else /* jCC */
3090 {
3091 the_ins.opcode[0] ^= 0x0100;
3092 the_ins.opcode[0] |= 0x0006;
3093 addword (0x4EF9);
3094 }
3095 add_fix ('l', &opP->disp, 0, 0);
3096 addword (0);
3097 addword (0);
3098 break;
3099 }
3100
3101 /* Now we know it's going into the relaxer. Now figure
3102 out which mode. We try in this order of preference:
3103 long branch, absolute jump, byte/word branches only. */
3104 if (have_disp)
3105 add_frag (adds (&opP->disp),
3106 SEXT (offs (&opP->disp)),
3107 TAB (BRANCHBWL, SZ_UNDEF));
3108 else if (! flag_keep_pcrel)
3109 {
3110 if ((the_ins.opcode[0] == 0x6000)
3111 || (the_ins.opcode[0] == 0x6100))
3112 add_frag (adds (&opP->disp),
3113 SEXT (offs (&opP->disp)),
3114 TAB (BRABSJUNC, SZ_UNDEF));
3115 else
3116 add_frag (adds (&opP->disp),
3117 SEXT (offs (&opP->disp)),
3118 TAB (BRABSJCOND, SZ_UNDEF));
3119 }
3120 else
3121 add_frag (adds (&opP->disp),
3122 SEXT (offs (&opP->disp)),
3123 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3124 : TAB (BRANCHBW, SZ_UNDEF)));
3125 break;
3126 case 'w':
3127 if (isvar (&opP->disp))
3128 {
3129 /* Check for DBcc instructions. We can relax them,
3130 but only if we have long branches and/or absolute
3131 jumps. */
3132 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3133 && (HAVE_LONG_BRANCH (current_architecture)
3134 || ! flag_keep_pcrel))
3135 {
3136 if (HAVE_LONG_BRANCH (current_architecture))
3137 add_frag (adds (&opP->disp),
3138 SEXT (offs (&opP->disp)),
3139 TAB (DBCCLBR, SZ_UNDEF));
3140 else
3141 add_frag (adds (&opP->disp),
3142 SEXT (offs (&opP->disp)),
3143 TAB (DBCCABSJ, SZ_UNDEF));
3144 break;
3145 }
3146 add_fix ('w', &opP->disp, 1, 0);
3147 }
3148 addword (0);
3149 break;
3150 case 'C': /* Fixed size LONG coproc branches. */
3151 add_fix ('l', &opP->disp, 1, 0);
3152 addword (0);
3153 addword (0);
3154 break;
3155 case 'c': /* Var size Coprocesssor branches. */
3156 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3157 {
3158 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3159 add_fix ('l', &opP->disp, 1, 0);
3160 addword (0);
3161 addword (0);
3162 }
3163 else
3164 add_frag (adds (&opP->disp),
3165 SEXT (offs (&opP->disp)),
3166 TAB (FBRANCH, SZ_UNDEF));
3167 break;
3168 default:
3169 abort ();
3170 }
3171 break;
3172
3173 case 'C': /* Ignore it. */
3174 break;
3175
3176 case 'd': /* JF this is a kludge. */
3177 install_operand ('s', opP->reg - ADDR);
3178 tmpreg = get_num (&opP->disp, 90);
3179 if (!issword (tmpreg))
3180 {
3181 as_warn (_("Expression out of range, using 0"));
3182 tmpreg = 0;
3183 }
3184 addword (tmpreg);
3185 break;
3186
3187 case 'D':
3188 install_operand (s[1], opP->reg - DATA);
3189 break;
3190
3191 case 'e': /* EMAC ACCx, reg/reg. */
3192 install_operand (s[1], opP->reg - ACC);
3193 break;
3194
3195 case 'E': /* Ignore it. */
3196 break;
3197
3198 case 'F':
3199 install_operand (s[1], opP->reg - FP0);
3200 break;
3201
3202 case 'g': /* EMAC ACCEXTx. */
3203 install_operand (s[1], opP->reg - ACCEXT01);
3204 break;
3205
3206 case 'G': /* Ignore it. */
3207 case 'H':
3208 break;
3209
3210 case 'I':
3211 tmpreg = opP->reg - COP0;
3212 install_operand (s[1], tmpreg);
3213 break;
3214
3215 case 'i': /* MAC/EMAC scale factor. */
3216 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3217 break;
3218
3219 case 'J': /* JF foo. */
3220 switch (opP->reg)
3221 {
3222 case SFC:
3223 tmpreg = 0x000;
3224 break;
3225 case DFC:
3226 tmpreg = 0x001;
3227 break;
3228 case CACR:
3229 tmpreg = 0x002;
3230 break;
3231 case TC:
3232 case ASID:
3233 tmpreg = 0x003;
3234 break;
3235 case ACR0:
3236 case ITT0:
3237 tmpreg = 0x004;
3238 break;
3239 case ACR1:
3240 case ITT1:
3241 tmpreg = 0x005;
3242 break;
3243 case ACR2:
3244 case DTT0:
3245 tmpreg = 0x006;
3246 break;
3247 case ACR3:
3248 case DTT1:
3249 tmpreg = 0x007;
3250 break;
3251 case BUSCR:
3252 case MMUBAR:
3253 tmpreg = 0x008;
3254 break;
3255 case RGPIOBAR:
3256 tmpreg = 0x009;
3257 break;
3258 case ACR4:
3259 case ACR5:
3260 case ACR6:
3261 case ACR7:
3262 tmpreg = 0x00c + (opP->reg - ACR4);
3263 break;
3264
3265 case USP:
3266 tmpreg = 0x800;
3267 break;
3268 case VBR:
3269 tmpreg = 0x801;
3270 break;
3271 case CAAR:
3272 case CPUCR:
3273 tmpreg = 0x802;
3274 break;
3275 case MSP:
3276 tmpreg = 0x803;
3277 break;
3278 case ISP:
3279 tmpreg = 0x804;
3280 break;
3281 case MMUSR:
3282 tmpreg = 0x805;
3283 break;
3284 case URP:
3285 tmpreg = 0x806;
3286 break;
3287 case SRP:
3288 tmpreg = 0x807;
3289 break;
3290 case PCR:
3291 tmpreg = 0x808;
3292 break;
3293 case ROMBAR:
3294 case ROMBAR0:
3295 tmpreg = 0xC00;
3296 break;
3297 case ROMBAR1:
3298 tmpreg = 0xC01;
3299 break;
3300 case FLASHBAR:
3301 case RAMBAR0:
3302 case RAMBAR_ALT:
3303 tmpreg = 0xC04;
3304 break;
3305 case RAMBAR:
3306 case RAMBAR1:
3307 tmpreg = 0xC05;
3308 break;
3309 case MPCR:
3310 tmpreg = 0xC0C;
3311 break;
3312 case EDRAMBAR:
3313 tmpreg = 0xC0D;
3314 break;
3315 case MBAR0:
3316 case MBAR2:
3317 case SECMBAR:
3318 tmpreg = 0xC0E;
3319 break;
3320 case MBAR1:
3321 case MBAR:
3322 tmpreg = 0xC0F;
3323 break;
3324 case PCR1U0:
3325 tmpreg = 0xD02;
3326 break;
3327 case PCR1L0:
3328 tmpreg = 0xD03;
3329 break;
3330 case PCR2U0:
3331 tmpreg = 0xD04;
3332 break;
3333 case PCR2L0:
3334 tmpreg = 0xD05;
3335 break;
3336 case PCR3U0:
3337 tmpreg = 0xD06;
3338 break;
3339 case PCR3L0:
3340 tmpreg = 0xD07;
3341 break;
3342 case PCR1L1:
3343 tmpreg = 0xD0A;
3344 break;
3345 case PCR1U1:
3346 tmpreg = 0xD0B;
3347 break;
3348 case PCR2L1:
3349 tmpreg = 0xD0C;
3350 break;
3351 case PCR2U1:
3352 tmpreg = 0xD0D;
3353 break;
3354 case PCR3L1:
3355 tmpreg = 0xD0E;
3356 break;
3357 case PCR3U1:
3358 tmpreg = 0xD0F;
3359 break;
3360 case CAC:
3361 tmpreg = 0xFFE;
3362 break;
3363 case MBO:
3364 tmpreg = 0xFFF;
3365 break;
3366 default:
3367 abort ();
3368 }
3369 install_operand (s[1], tmpreg);
3370 break;
3371
3372 case 'k':
3373 tmpreg = get_num (&opP->disp, 55);
3374 install_operand (s[1], tmpreg & 0x7f);
3375 break;
3376
3377 case 'l':
3378 tmpreg = opP->mask;
3379 if (s[1] == 'w')
3380 {
3381 if (tmpreg & 0x7FF0000)
3382 as_bad (_("Floating point register in register list"));
3383 insop (reverse_16_bits (tmpreg), opcode);
3384 }
3385 else
3386 {
3387 if (tmpreg & 0x700FFFF)
3388 as_bad (_("Wrong register in floating-point reglist"));
3389 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3390 }
3391 break;
3392
3393 case 'L':
3394 tmpreg = opP->mask;
3395 if (s[1] == 'w')
3396 {
3397 if (tmpreg & 0x7FF0000)
3398 as_bad (_("Floating point register in register list"));
3399 insop (tmpreg, opcode);
3400 }
3401 else if (s[1] == '8')
3402 {
3403 if (tmpreg & 0x0FFFFFF)
3404 as_bad (_("incorrect register in reglist"));
3405 install_operand (s[1], tmpreg >> 24);
3406 }
3407 else
3408 {
3409 if (tmpreg & 0x700FFFF)
3410 as_bad (_("wrong register in floating-point reglist"));
3411 else
3412 install_operand (s[1], tmpreg >> 16);
3413 }
3414 break;
3415
3416 case 'M':
3417 install_operand (s[1], get_num (&opP->disp, 60));
3418 break;
3419
3420 case 'O':
3421 tmpreg = ((opP->mode == DREG)
3422 ? 0x20 + (int) (opP->reg - DATA)
3423 : (get_num (&opP->disp, 40) & 0x1F));
3424 install_operand (s[1], tmpreg);
3425 break;
3426
3427 case 'Q':
3428 tmpreg = get_num (&opP->disp, 10);
3429 if (tmpreg == 8)
3430 tmpreg = 0;
3431 install_operand (s[1], tmpreg);
3432 break;
3433
3434 case 'R':
3435 /* This depends on the fact that ADDR registers are eight
3436 more than their corresponding DATA regs, so the result
3437 will have the ADDR_REG bit set. */
3438 install_operand (s[1], opP->reg - DATA);
3439 break;
3440
3441 case 'r':
3442 if (opP->mode == AINDR)
3443 install_operand (s[1], opP->reg - DATA);
3444 else
3445 install_operand (s[1], opP->index.reg - DATA);
3446 break;
3447
3448 case 's':
3449 if (opP->reg == FPI)
3450 tmpreg = 0x1;
3451 else if (opP->reg == FPS)
3452 tmpreg = 0x2;
3453 else if (opP->reg == FPC)
3454 tmpreg = 0x4;
3455 else
3456 abort ();
3457 install_operand (s[1], tmpreg);
3458 break;
3459
3460 case 'S': /* Ignore it. */
3461 break;
3462
3463 case 'T':
3464 install_operand (s[1], get_num (&opP->disp, 30));
3465 break;
3466
3467 case 'U': /* Ignore it. */
3468 break;
3469
3470 case 'c':
3471 switch (opP->reg)
3472 {
3473 case NC:
3474 tmpreg = 0;
3475 break;
3476 case DC:
3477 tmpreg = 1;
3478 break;
3479 case IC:
3480 tmpreg = 2;
3481 break;
3482 case BC:
3483 tmpreg = 3;
3484 break;
3485 default:
3486 as_fatal (_("failed sanity check"));
3487 } /* switch on cache token. */
3488 install_operand (s[1], tmpreg);
3489 break;
3490 #ifndef NO_68851
3491 /* JF: These are out of order, I fear. */
3492 case 'f':
3493 switch (opP->reg)
3494 {
3495 case SFC:
3496 tmpreg = 0;
3497 break;
3498 case DFC:
3499 tmpreg = 1;
3500 break;
3501 default:
3502 abort ();
3503 }
3504 install_operand (s[1], tmpreg);
3505 break;
3506
3507 case '0':
3508 case '1':
3509 case '2':
3510 switch (opP->reg)
3511 {
3512 case TC:
3513 tmpreg = 0;
3514 break;
3515 case CAL:
3516 tmpreg = 4;
3517 break;
3518 case VAL:
3519 tmpreg = 5;
3520 break;
3521 case SCC:
3522 tmpreg = 6;
3523 break;
3524 case AC:
3525 tmpreg = 7;
3526 break;
3527 default:
3528 abort ();
3529 }
3530 install_operand (s[1], tmpreg);
3531 break;
3532
3533 case 'V':
3534 if (opP->reg == VAL)
3535 break;
3536 abort ();
3537
3538 case 'W':
3539 switch (opP->reg)
3540 {
3541 case DRP:
3542 tmpreg = 1;
3543 break;
3544 case SRP:
3545 tmpreg = 2;
3546 break;
3547 case CRP:
3548 tmpreg = 3;
3549 break;
3550 default:
3551 abort ();
3552 }
3553 install_operand (s[1], tmpreg);
3554 break;
3555
3556 case 'X':
3557 switch (opP->reg)
3558 {
3559 case BAD:
3560 case BAD + 1:
3561 case BAD + 2:
3562 case BAD + 3:
3563 case BAD + 4:
3564 case BAD + 5:
3565 case BAD + 6:
3566 case BAD + 7:
3567 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3568 break;
3569
3570 case BAC:
3571 case BAC + 1:
3572 case BAC + 2:
3573 case BAC + 3:
3574 case BAC + 4:
3575 case BAC + 5:
3576 case BAC + 6:
3577 case BAC + 7:
3578 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3579 break;
3580
3581 default:
3582 abort ();
3583 }
3584 install_operand (s[1], tmpreg);
3585 break;
3586 case 'Y':
3587 know (opP->reg == PSR);
3588 break;
3589 case 'Z':
3590 know (opP->reg == PCSR);
3591 break;
3592 #endif /* m68851 */
3593 case '3':
3594 switch (opP->reg)
3595 {
3596 case TT0:
3597 tmpreg = 2;
3598 break;
3599 case TT1:
3600 tmpreg = 3;
3601 break;
3602 default:
3603 abort ();
3604 }
3605 install_operand (s[1], tmpreg);
3606 break;
3607 case 't':
3608 tmpreg = get_num (&opP->disp, 20);
3609 install_operand (s[1], tmpreg);
3610 break;
3611 case '_': /* used only for move16 absolute 32-bit address. */
3612 if (isvar (&opP->disp))
3613 add_fix ('l', &opP->disp, 0, 0);
3614 tmpreg = get_num (&opP->disp, 90);
3615 addword (tmpreg >> 16);
3616 addword (tmpreg & 0xFFFF);
3617 break;
3618 case 'u':
3619 install_operand (s[1], opP->reg - DATA0L);
3620 opP->reg -= (DATA0L);
3621 opP->reg &= 0x0F; /* remove upper/lower bit. */
3622 break;
3623 case 'x':
3624 tmpreg = get_num (&opP->disp, 80);
3625 if (tmpreg == -1)
3626 tmpreg = 0;
3627 install_operand (s[1], tmpreg);
3628 break;
3629 case 'j':
3630 tmpreg = get_num (&opP->disp, 10);
3631 install_operand (s[1], tmpreg - 1);
3632 break;
3633 case 'K':
3634 tmpreg = get_num (&opP->disp, 65);
3635 install_operand (s[1], tmpreg);
3636 break;
3637 default:
3638 abort ();
3639 }
3640 }
3641
3642 /* By the time when get here (FINALLY) the_ins contains the complete
3643 instruction, ready to be emitted. . . */
3644 }
3645
3646 static int
reverse_16_bits(int in)3647 reverse_16_bits (int in)
3648 {
3649 int out = 0;
3650 int n;
3651
3652 static int mask[16] =
3653 {
3654 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3655 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3656 };
3657 for (n = 0; n < 16; n++)
3658 {
3659 if (in & mask[n])
3660 out |= mask[15 - n];
3661 }
3662 return out;
3663 } /* reverse_16_bits() */
3664
3665 static int
reverse_8_bits(int in)3666 reverse_8_bits (int in)
3667 {
3668 int out = 0;
3669 int n;
3670
3671 static int mask[8] =
3672 {
3673 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3674 };
3675
3676 for (n = 0; n < 8; n++)
3677 {
3678 if (in & mask[n])
3679 out |= mask[7 - n];
3680 }
3681 return out;
3682 } /* reverse_8_bits() */
3683
3684 /* Cause an extra frag to be generated here, inserting up to
3685 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3686 generated; its primary type is rs_machine_dependent.
3687
3688 The TYPE parameter is also used by md_convert_frag_1 and
3689 md_estimate_size_before_relax. The appropriate type of fixup will
3690 be emitted by md_convert_frag_1.
3691
3692 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3693 static void
install_operand(int mode,int val)3694 install_operand (int mode, int val)
3695 {
3696 switch (mode)
3697 {
3698 case 's':
3699 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
3700 break;
3701 case 'd':
3702 the_ins.opcode[0] |= val << 9;
3703 break;
3704 case 'E':
3705 the_ins.opcode[1] |= val << 9;
3706 break;
3707 case '1':
3708 the_ins.opcode[1] |= val << 12;
3709 break;
3710 case '2':
3711 the_ins.opcode[1] |= val << 6;
3712 break;
3713 case '3':
3714 the_ins.opcode[1] |= val;
3715 break;
3716 case '4':
3717 the_ins.opcode[2] |= val << 12;
3718 break;
3719 case '5':
3720 the_ins.opcode[2] |= val << 6;
3721 break;
3722 case '6':
3723 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3724 three words long! */
3725 the_ins.numo++;
3726 the_ins.opcode[2] |= val;
3727 break;
3728 case '7':
3729 the_ins.opcode[1] |= val << 7;
3730 break;
3731 case '8':
3732 the_ins.opcode[1] |= val << 10;
3733 break;
3734 #ifndef NO_68851
3735 case '9':
3736 the_ins.opcode[1] |= val << 5;
3737 break;
3738 #endif
3739
3740 case 't':
3741 the_ins.opcode[1] |= (val << 10) | (val << 7);
3742 break;
3743 case 'D':
3744 the_ins.opcode[1] |= (val << 12) | val;
3745 break;
3746 case 'g':
3747 the_ins.opcode[0] |= val = 0xff;
3748 break;
3749 case 'i':
3750 the_ins.opcode[0] |= val << 9;
3751 break;
3752 case 'C':
3753 the_ins.opcode[1] |= val;
3754 break;
3755 case 'j':
3756 the_ins.opcode[1] |= val;
3757 the_ins.numo++; /* What a hack. */
3758 break;
3759 case 'k':
3760 the_ins.opcode[1] |= val << 4;
3761 break;
3762 case 'b':
3763 case 'w':
3764 case 'W':
3765 case 'l':
3766 break;
3767 case 'e':
3768 the_ins.opcode[0] |= (val << 6);
3769 break;
3770 case 'L':
3771 the_ins.opcode[1] = (val >> 16);
3772 the_ins.opcode[2] = val & 0xffff;
3773 break;
3774 case 'm':
3775 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3776 the_ins.opcode[0] |= ((val & 0x7) << 9);
3777 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3778 break;
3779 case 'n': /* MAC/EMAC Rx on !load. */
3780 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3781 the_ins.opcode[0] |= ((val & 0x7) << 9);
3782 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3783 break;
3784 case 'o': /* MAC/EMAC Rx on load. */
3785 the_ins.opcode[1] |= val << 12;
3786 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3787 break;
3788 case 'M': /* MAC/EMAC Ry on !load. */
3789 the_ins.opcode[0] |= (val & 0xF);
3790 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3791 break;
3792 case 'N': /* MAC/EMAC Ry on load. */
3793 the_ins.opcode[1] |= (val & 0xF);
3794 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3795 break;
3796 case 'h':
3797 the_ins.opcode[1] |= ((val != 1) << 10);
3798 break;
3799 case 'F':
3800 the_ins.opcode[0] |= ((val & 0x3) << 9);
3801 break;
3802 case 'f':
3803 the_ins.opcode[0] |= ((val & 0x3) << 0);
3804 break;
3805 case 'G': /* EMAC accumulator in a EMAC load instruction. */
3806 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3807 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3808 break;
3809 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
3810 the_ins.opcode[0] |= ((val & 0x1) << 7);
3811 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3812 break;
3813 case 'I':
3814 the_ins.opcode[1] |= ((val & 0x3) << 9);
3815 break;
3816 case ']':
3817 the_ins.opcode[0] |= (val & 0x1) <<10;
3818 break;
3819 case 'c':
3820 default:
3821 as_fatal (_("failed sanity check."));
3822 }
3823 }
3824
3825 static void
install_gen_operand(int mode,int val)3826 install_gen_operand (int mode, int val)
3827 {
3828 switch (mode)
3829 {
3830 case '/': /* Special for mask loads for mac/msac insns with
3831 possible mask; trailing_ampersand set in bit 8. */
3832 the_ins.opcode[0] |= (val & 0x3f);
3833 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3834 break;
3835 case 's':
3836 the_ins.opcode[0] |= val;
3837 break;
3838 case 'd':
3839 /* This is a kludge!!! */
3840 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3841 break;
3842 case 'b':
3843 case 'w':
3844 case 'l':
3845 case 'f':
3846 case 'F':
3847 case 'x':
3848 case 'p':
3849 the_ins.opcode[0] |= val;
3850 break;
3851 /* more stuff goes here. */
3852 default:
3853 as_fatal (_("failed sanity check."));
3854 }
3855 }
3856
3857 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3858 then deal with the bitfield hack. */
3859
3860 static char *
crack_operand(char * str,struct m68k_op * opP)3861 crack_operand (char *str, struct m68k_op *opP)
3862 {
3863 int parens;
3864 int c;
3865 char *beg_str;
3866 int inquote = 0;
3867
3868 if (!str)
3869 {
3870 return str;
3871 }
3872 beg_str = str;
3873 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3874 {
3875 if (! inquote)
3876 {
3877 if (*str == '(')
3878 parens++;
3879 else if (*str == ')')
3880 {
3881 if (!parens)
3882 { /* ERROR. */
3883 opP->error = _("Extra )");
3884 return str;
3885 }
3886 --parens;
3887 }
3888 }
3889 if (flag_mri && *str == '\'')
3890 inquote = ! inquote;
3891 }
3892 if (!*str && parens)
3893 { /* ERROR. */
3894 opP->error = _("Missing )");
3895 return str;
3896 }
3897 c = *str;
3898 *str = '\0';
3899 if (m68k_ip_op (beg_str, opP) != 0)
3900 {
3901 *str = c;
3902 return str;
3903 }
3904 *str = c;
3905 if (c == '}')
3906 c = *++str; /* JF bitfield hack. */
3907 if (c)
3908 {
3909 c = *++str;
3910 if (!c)
3911 as_bad (_("Missing operand"));
3912 }
3913
3914 /* Detect MRI REG symbols and convert them to REGLSTs. */
3915 if (opP->mode == CONTROL && (int)opP->reg < 0)
3916 {
3917 opP->mode = REGLST;
3918 opP->mask = ~(int)opP->reg;
3919 opP->reg = 0;
3920 }
3921
3922 return str;
3923 }
3924
3925 /* This is the guts of the machine-dependent assembler. STR points to a
3926 machine dependent instruction. This function is supposed to emit
3927 the frags/bytes it assembles to.
3928 */
3929
3930 static void
insert_reg(const char * regname,int regnum)3931 insert_reg (const char *regname, int regnum)
3932 {
3933 char buf[100];
3934 int i;
3935
3936 #ifdef REGISTER_PREFIX
3937 if (!flag_reg_prefix_optional)
3938 {
3939 buf[0] = REGISTER_PREFIX;
3940 strcpy (buf + 1, regname);
3941 regname = buf;
3942 }
3943 #endif
3944
3945 symbol_table_insert (symbol_new (regname, reg_section,
3946 &zero_address_frag, regnum));
3947
3948 for (i = 0; regname[i]; i++)
3949 buf[i] = TOUPPER (regname[i]);
3950 buf[i] = '\0';
3951
3952 symbol_table_insert (symbol_new (buf, reg_section,
3953 &zero_address_frag, regnum));
3954 }
3955
3956 struct init_entry
3957 {
3958 const char *name;
3959 int number;
3960 };
3961
3962 static const struct init_entry init_table[] =
3963 {
3964 { "d0", DATA0 },
3965 { "d1", DATA1 },
3966 { "d2", DATA2 },
3967 { "d3", DATA3 },
3968 { "d4", DATA4 },
3969 { "d5", DATA5 },
3970 { "d6", DATA6 },
3971 { "d7", DATA7 },
3972 { "a0", ADDR0 },
3973 { "a1", ADDR1 },
3974 { "a2", ADDR2 },
3975 { "a3", ADDR3 },
3976 { "a4", ADDR4 },
3977 { "a5", ADDR5 },
3978 { "a6", ADDR6 },
3979 { "fp", ADDR6 },
3980 { "a7", ADDR7 },
3981 { "sp", ADDR7 },
3982 { "ssp", ADDR7 },
3983 { "fp0", FP0 },
3984 { "fp1", FP1 },
3985 { "fp2", FP2 },
3986 { "fp3", FP3 },
3987 { "fp4", FP4 },
3988 { "fp5", FP5 },
3989 { "fp6", FP6 },
3990 { "fp7", FP7 },
3991 { "fpi", FPI },
3992 { "fpiar", FPI },
3993 { "fpc", FPI },
3994 { "fps", FPS },
3995 { "fpsr", FPS },
3996 { "fpc", FPC },
3997 { "fpcr", FPC },
3998 { "control", FPC },
3999 { "status", FPS },
4000 { "iaddr", FPI },
4001
4002 { "cop0", COP0 },
4003 { "cop1", COP1 },
4004 { "cop2", COP2 },
4005 { "cop3", COP3 },
4006 { "cop4", COP4 },
4007 { "cop5", COP5 },
4008 { "cop6", COP6 },
4009 { "cop7", COP7 },
4010 { "pc", PC },
4011 { "zpc", ZPC },
4012 { "sr", SR },
4013
4014 { "ccr", CCR },
4015 { "cc", CCR },
4016
4017 { "acc", ACC },
4018 { "acc0", ACC },
4019 { "acc1", ACC1 },
4020 { "acc2", ACC2 },
4021 { "acc3", ACC3 },
4022 { "accext01", ACCEXT01 },
4023 { "accext23", ACCEXT23 },
4024 { "macsr", MACSR },
4025 { "mask", MASK },
4026
4027 /* Control registers. */
4028 { "sfc", SFC }, /* Source Function Code. */
4029 { "sfcr", SFC },
4030 { "dfc", DFC }, /* Destination Function Code. */
4031 { "dfcr", DFC },
4032 { "cacr", CACR }, /* Cache Control Register. */
4033 { "caar", CAAR }, /* Cache Address Register. */
4034 { "cpucr", CPUCR }, /* CPU Control Register. */
4035
4036 { "usp", USP }, /* User Stack Pointer. */
4037 { "vbr", VBR }, /* Vector Base Register. */
4038 { "msp", MSP }, /* Master Stack Pointer. */
4039 { "isp", ISP }, /* Interrupt Stack Pointer. */
4040
4041 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4042 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4043 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4044 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
4045
4046 /* 68ec040 versions of same */
4047 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4048 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4049 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4050 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
4051
4052 /* Coldfire versions of same. The ColdFire programmer's reference
4053 manual indicated that the order is 2,3,0,1, but Ken Rose
4054 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
4055 { "acr0", ACR0 }, /* Access Control Unit 0. */
4056 { "acr1", ACR1 }, /* Access Control Unit 1. */
4057 { "acr2", ACR2 }, /* Access Control Unit 2. */
4058 { "acr3", ACR3 }, /* Access Control Unit 3. */
4059 { "acr4", ACR4 }, /* Access Control Unit 4. */
4060 { "acr5", ACR5 }, /* Access Control Unit 5. */
4061 { "acr6", ACR6 }, /* Access Control Unit 6. */
4062 { "acr7", ACR7 }, /* Access Control Unit 7. */
4063
4064 { "tc", TC }, /* MMU Translation Control Register. */
4065 { "tcr", TC },
4066 { "asid", ASID },
4067
4068 { "mmusr", MMUSR }, /* MMU Status Register. */
4069 { "srp", SRP }, /* User Root Pointer. */
4070 { "urp", URP }, /* Supervisor Root Pointer. */
4071
4072 { "buscr", BUSCR },
4073 { "mmubar", MMUBAR },
4074 { "pcr", PCR },
4075
4076 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4077 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4078 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4079 { "mbar", MBAR }, /* Module Base Address Register. */
4080
4081 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4082 { "mbar1", MBAR1 }, /* mcfv4e registers. */
4083 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
4084 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4085 { "mpcr", MPCR }, /* mcfv4e registers. */
4086 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4087 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4088 { "asid", TC }, /* mcfv4e registers. */
4089 { "mmubar", BUSCR }, /* mcfv4e registers. */
4090 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4091 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4092 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4093 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4094 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4095 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4096 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4097 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4098 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4099 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4100 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4101 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4102
4103 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4104 { "rambar", RAMBAR }, /* mcf528x registers. */
4105
4106 { "mbar2", MBAR2 }, /* mcf5249 registers. */
4107
4108 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4109
4110 { "cac", CAC }, /* fido registers. */
4111 { "mbb", MBO }, /* fido registers (obsolete). */
4112 { "mbo", MBO }, /* fido registers. */
4113 /* End of control registers. */
4114
4115 { "ac", AC },
4116 { "bc", BC },
4117 { "cal", CAL },
4118 { "crp", CRP },
4119 { "drp", DRP },
4120 { "pcsr", PCSR },
4121 { "psr", PSR },
4122 { "scc", SCC },
4123 { "val", VAL },
4124 { "bad0", BAD0 },
4125 { "bad1", BAD1 },
4126 { "bad2", BAD2 },
4127 { "bad3", BAD3 },
4128 { "bad4", BAD4 },
4129 { "bad5", BAD5 },
4130 { "bad6", BAD6 },
4131 { "bad7", BAD7 },
4132 { "bac0", BAC0 },
4133 { "bac1", BAC1 },
4134 { "bac2", BAC2 },
4135 { "bac3", BAC3 },
4136 { "bac4", BAC4 },
4137 { "bac5", BAC5 },
4138 { "bac6", BAC6 },
4139 { "bac7", BAC7 },
4140
4141 { "ic", IC },
4142 { "dc", DC },
4143 { "nc", NC },
4144
4145 { "tt0", TT0 },
4146 { "tt1", TT1 },
4147 /* 68ec030 versions of same. */
4148 { "ac0", TT0 },
4149 { "ac1", TT1 },
4150 /* 68ec030 access control unit, identical to 030 MMU status reg. */
4151 { "acusr", PSR },
4152
4153 /* Suppressed data and address registers. */
4154 { "zd0", ZDATA0 },
4155 { "zd1", ZDATA1 },
4156 { "zd2", ZDATA2 },
4157 { "zd3", ZDATA3 },
4158 { "zd4", ZDATA4 },
4159 { "zd5", ZDATA5 },
4160 { "zd6", ZDATA6 },
4161 { "zd7", ZDATA7 },
4162 { "za0", ZADDR0 },
4163 { "za1", ZADDR1 },
4164 { "za2", ZADDR2 },
4165 { "za3", ZADDR3 },
4166 { "za4", ZADDR4 },
4167 { "za5", ZADDR5 },
4168 { "za6", ZADDR6 },
4169 { "za7", ZADDR7 },
4170
4171 /* Upper and lower data and address registers, used by macw and msacw. */
4172 { "d0l", DATA0L },
4173 { "d1l", DATA1L },
4174 { "d2l", DATA2L },
4175 { "d3l", DATA3L },
4176 { "d4l", DATA4L },
4177 { "d5l", DATA5L },
4178 { "d6l", DATA6L },
4179 { "d7l", DATA7L },
4180
4181 { "a0l", ADDR0L },
4182 { "a1l", ADDR1L },
4183 { "a2l", ADDR2L },
4184 { "a3l", ADDR3L },
4185 { "a4l", ADDR4L },
4186 { "a5l", ADDR5L },
4187 { "a6l", ADDR6L },
4188 { "a7l", ADDR7L },
4189
4190 { "d0u", DATA0U },
4191 { "d1u", DATA1U },
4192 { "d2u", DATA2U },
4193 { "d3u", DATA3U },
4194 { "d4u", DATA4U },
4195 { "d5u", DATA5U },
4196 { "d6u", DATA6U },
4197 { "d7u", DATA7U },
4198
4199 { "a0u", ADDR0U },
4200 { "a1u", ADDR1U },
4201 { "a2u", ADDR2U },
4202 { "a3u", ADDR3U },
4203 { "a4u", ADDR4U },
4204 { "a5u", ADDR5U },
4205 { "a6u", ADDR6U },
4206 { "a7u", ADDR7U },
4207
4208 { 0, 0 }
4209 };
4210
4211 static void
init_regtable(void)4212 init_regtable (void)
4213 {
4214 int i;
4215 for (i = 0; init_table[i].name; i++)
4216 insert_reg (init_table[i].name, init_table[i].number);
4217 }
4218
4219 void
md_assemble(char * str)4220 md_assemble (char *str)
4221 {
4222 const char *er;
4223 short *fromP;
4224 char *toP = NULL;
4225 int m, n = 0;
4226 char *to_beg_P;
4227 int shorts_this_frag;
4228 fixS *fixP;
4229
4230 if (!selected_cpu && !selected_arch)
4231 {
4232 /* We've not selected an architecture yet. Set the default
4233 now. We do this lazily so that an initial .cpu or .arch directive
4234 can specify. */
4235 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4236 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4237 }
4238 if (!initialized)
4239 m68k_init_arch ();
4240
4241 /* In MRI mode, the instruction and operands are separated by a
4242 space. Anything following the operands is a comment. The label
4243 has already been removed. */
4244 if (flag_mri)
4245 {
4246 char *s;
4247 int fields = 0;
4248 int infield = 0;
4249 int inquote = 0;
4250
4251 for (s = str; *s != '\0'; s++)
4252 {
4253 if ((*s == ' ' || *s == '\t') && ! inquote)
4254 {
4255 if (infield)
4256 {
4257 ++fields;
4258 if (fields >= 2)
4259 {
4260 *s = '\0';
4261 break;
4262 }
4263 infield = 0;
4264 }
4265 }
4266 else
4267 {
4268 if (! infield)
4269 infield = 1;
4270 if (*s == '\'')
4271 inquote = ! inquote;
4272 }
4273 }
4274 }
4275
4276 bool hasnop = false;
4277 char nop[4] = "nop";
4278 toP = NULL;
4279 next:
4280 memset (&the_ins, '\0', sizeof (the_ins));
4281
4282 m68k_ip (str);
4283
4284 if (lcfix == true && hasnop == false &&
4285 (the_ins.opcode[0] & 0xf000) == 0xf000)
4286 {
4287 memset (&the_ins, '\0', sizeof (the_ins));
4288 m68k_ip (nop);
4289 hasnop = true;
4290 }
4291 else
4292 hasnop = false;
4293
4294 er = the_ins.error;
4295 if (!er)
4296 {
4297 for (n = 0; n < the_ins.numargs; n++)
4298 if (the_ins.operands[n].error)
4299 {
4300 er = the_ins.operands[n].error;
4301 break;
4302 }
4303 }
4304 if (er)
4305 {
4306 as_bad (_("%s -- statement `%s' ignored"), er, str);
4307 return;
4308 }
4309
4310 /* If there is a current label, record that it marks an instruction. */
4311 if (current_label != NULL)
4312 {
4313 current_label->text = 1;
4314 current_label = NULL;
4315 }
4316
4317 /* Tie dwarf2 debug info to the address at the start of the insn. */
4318 dwarf2_emit_insn (0);
4319
4320 if (the_ins.nfrag == 0)
4321 {
4322 /* No frag hacking involved; just put it out. */
4323 toP = frag_more (2 * the_ins.numo);
4324 fromP = &the_ins.opcode[0];
4325 for (m = the_ins.numo; m; --m)
4326 {
4327 md_number_to_chars (toP, (long) (*fromP), 2);
4328 toP += 2;
4329 fromP++;
4330 }
4331 /* Put out symbol-dependent info. */
4332 for (m = 0; m < the_ins.nrel; m++)
4333 {
4334 switch (the_ins.reloc[m].wid)
4335 {
4336 case 'B':
4337 n = 1;
4338 break;
4339 case 'b':
4340 n = 1;
4341 break;
4342 case '3':
4343 n = 1;
4344 break;
4345 case 'w':
4346 case 'W':
4347 n = 2;
4348 break;
4349 case 'l':
4350 n = 4;
4351 break;
4352 default:
4353 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
4354 the_ins.reloc[m].wid);
4355 }
4356
4357 fixP = fix_new_exp (frag_now,
4358 ((toP - frag_now->fr_literal)
4359 - the_ins.numo * 2 + the_ins.reloc[m].n),
4360 n,
4361 &the_ins.reloc[m].exp,
4362 the_ins.reloc[m].pcrel,
4363 get_reloc_code (n, the_ins.reloc[m].pcrel,
4364 the_ins.reloc[m].pic_reloc));
4365 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4366 if (the_ins.reloc[m].wid == 'B')
4367 fixP->fx_signed = 1;
4368 }
4369 if (hasnop == true)
4370 goto next;
4371 return;
4372 }
4373
4374 /* There's some frag hacking. */
4375 {
4376 /* Calculate the max frag size. */
4377 int wid;
4378
4379 wid = 2 * the_ins.fragb[0].fragoff;
4380 for (n = 1; n < the_ins.nfrag; n++)
4381 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4382 /* frag_var part. */
4383 wid += FRAG_VAR_SIZE;
4384 /* Make sure the whole insn fits in one chunk, in particular that
4385 the var part is attached, as we access one byte before the
4386 variable frag for byte branches. */
4387 frag_grow (wid);
4388 }
4389
4390 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4391 {
4392 int wid;
4393
4394 if (n == 0)
4395 wid = 2 * the_ins.fragb[n].fragoff;
4396 else
4397 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4398 toP = frag_more (wid);
4399 to_beg_P = toP;
4400 shorts_this_frag = 0;
4401 for (m = wid / 2; m; --m)
4402 {
4403 md_number_to_chars (toP, (long) (*fromP), 2);
4404 toP += 2;
4405 fromP++;
4406 shorts_this_frag++;
4407 }
4408 for (m = 0; m < the_ins.nrel; m++)
4409 {
4410 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4411 {
4412 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4413 break;
4414 }
4415 wid = the_ins.reloc[m].wid;
4416 if (wid == 0)
4417 continue;
4418 the_ins.reloc[m].wid = 0;
4419 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4420
4421 fixP = fix_new_exp (frag_now,
4422 ((toP - frag_now->fr_literal)
4423 - the_ins.numo * 2 + the_ins.reloc[m].n),
4424 wid,
4425 &the_ins.reloc[m].exp,
4426 the_ins.reloc[m].pcrel,
4427 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4428 the_ins.reloc[m].pic_reloc));
4429 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4430 }
4431 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4432 (relax_substateT) (the_ins.fragb[n].fragty),
4433 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4434 }
4435 gas_assert (the_ins.nfrag >= 1);
4436 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
4437 shorts_this_frag = 0;
4438 if (n)
4439 {
4440 toP = frag_more (n * 2);
4441 while (n--)
4442 {
4443 md_number_to_chars (toP, (long) (*fromP), 2);
4444 toP += 2;
4445 fromP++;
4446 shorts_this_frag++;
4447 }
4448 }
4449 for (m = 0; m < the_ins.nrel; m++)
4450 {
4451 int wid;
4452
4453 wid = the_ins.reloc[m].wid;
4454 if (wid == 0)
4455 continue;
4456 the_ins.reloc[m].wid = 0;
4457 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4458
4459 fixP = fix_new_exp (frag_now,
4460 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4461 - shorts_this_frag * 2),
4462 wid,
4463 &the_ins.reloc[m].exp,
4464 the_ins.reloc[m].pcrel,
4465 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4466 the_ins.reloc[m].pic_reloc));
4467 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4468 }
4469 if (hasnop == true)
4470 goto next;
4471 }
4472
4473 /* Comparison function used by qsort to rank the opcode entries by name. */
4474
4475 static int
m68k_compare_opcode(const void * v1,const void * v2)4476 m68k_compare_opcode (const void * v1, const void * v2)
4477 {
4478 struct m68k_opcode * op1, * op2;
4479 int ret;
4480
4481 if (v1 == v2)
4482 return 0;
4483
4484 op1 = *(struct m68k_opcode **) v1;
4485 op2 = *(struct m68k_opcode **) v2;
4486
4487 /* Compare the two names. If different, return the comparison.
4488 If the same, return the order they are in the opcode table. */
4489 ret = strcmp (op1->name, op2->name);
4490 if (ret)
4491 return ret;
4492 if (op1 < op2)
4493 return -1;
4494 return 1;
4495 }
4496
4497 void
md_begin(void)4498 md_begin (void)
4499 {
4500 const struct m68k_opcode *ins;
4501 struct m68k_incant *hack, *slak;
4502 int i;
4503
4504 /* Set up hash tables with 68000 instructions.
4505 similar to what the vax assembler does. */
4506 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4507 a copy of it at runtime, adding in the information we want but isn't
4508 there. I think it'd be better to have an awk script hack the table
4509 at compile time. Or even just xstr the table and use it as-is. But
4510 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4511 names. */
4512
4513 if (flag_mri)
4514 {
4515 flag_reg_prefix_optional = 1;
4516 m68k_abspcadd = 1;
4517 if (! m68k_rel32_from_cmdline)
4518 m68k_rel32 = 0;
4519 }
4520
4521 /* First sort the opcode table into alphabetical order to separate
4522 the order that the assembler wants to see the opcodes from the
4523 order that the disassembler wants to see them. */
4524 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
4525
4526 for (i = m68k_numopcodes; i--;)
4527 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4528
4529 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4530 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4531
4532 op_hash = str_htab_create ();
4533
4534 obstack_begin (&robyn, 4000);
4535 for (i = 0; i < m68k_numopcodes; i++)
4536 {
4537 hack = slak = XOBNEW (&robyn, struct m68k_incant);
4538 do
4539 {
4540 ins = m68k_sorted_opcodes[i];
4541
4542 /* We must enter all insns into the table, because .arch and
4543 .cpu directives can change things. */
4544 slak->m_operands = ins->args;
4545 slak->m_arch = ins->arch;
4546 slak->m_opcode = ins->opcode;
4547
4548 /* In most cases we can determine the number of opcode words
4549 by checking the second word of the mask. Unfortunately
4550 some instructions have 2 opcode words, but no fixed bits
4551 in the second word. A leading dot in the operands
4552 string also indicates 2 opcodes. */
4553 if (*slak->m_operands == '.')
4554 {
4555 slak->m_operands++;
4556 slak->m_codenum = 2;
4557 }
4558 else if (ins->match & 0xffffL)
4559 slak->m_codenum = 2;
4560 else
4561 slak->m_codenum = 1;
4562 slak->m_opnum = strlen (slak->m_operands) / 2;
4563
4564 if (i + 1 != m68k_numopcodes
4565 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4566 {
4567 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
4568 i++;
4569 }
4570 else
4571 slak->m_next = 0;
4572 slak = slak->m_next;
4573 }
4574 while (slak);
4575
4576 if (str_hash_insert (op_hash, ins->name, hack, 0) != NULL)
4577 as_fatal (_("duplicate %s"), ins->name);
4578 }
4579
4580 for (i = 0; i < m68k_numaliases; i++)
4581 {
4582 const char *name = m68k_opcode_aliases[i].primary;
4583 const char *alias = m68k_opcode_aliases[i].alias;
4584 void *val = (void *) str_hash_find (op_hash, name);
4585
4586 if (!val)
4587 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4588 if (str_hash_insert (op_hash, alias, val, 0) != NULL)
4589 as_fatal (_("duplicate %s"), alias);
4590 }
4591
4592 /* In MRI mode, all unsized branches are variable sized. Normally,
4593 they are word sized. */
4594 if (flag_mri)
4595 {
4596 static struct m68k_opcode_alias mri_aliases[] =
4597 {
4598 { "bhi", "jhi", },
4599 { "bls", "jls", },
4600 { "bcc", "jcc", },
4601 { "bcs", "jcs", },
4602 { "bne", "jne", },
4603 { "beq", "jeq", },
4604 { "bvc", "jvc", },
4605 { "bvs", "jvs", },
4606 { "bpl", "jpl", },
4607 { "bmi", "jmi", },
4608 { "bge", "jge", },
4609 { "blt", "jlt", },
4610 { "bgt", "jgt", },
4611 { "ble", "jle", },
4612 { "bra", "jra", },
4613 { "bsr", "jbsr", },
4614 };
4615
4616 for (i = 0;
4617 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4618 i++)
4619 {
4620 const char *name = mri_aliases[i].primary;
4621 const char *alias = mri_aliases[i].alias;
4622 void *val = (void *) str_hash_find (op_hash, name);
4623
4624 if (!val)
4625 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4626 str_hash_insert (op_hash, alias, val, 1);
4627 }
4628 }
4629
4630 for (i = 0; i < (int) sizeof (notend_table); i++)
4631 {
4632 notend_table[i] = 0;
4633 alt_notend_table[i] = 0;
4634 }
4635
4636 notend_table[','] = 1;
4637 notend_table['{'] = 1;
4638 notend_table['}'] = 1;
4639 alt_notend_table['a'] = 1;
4640 alt_notend_table['A'] = 1;
4641 alt_notend_table['d'] = 1;
4642 alt_notend_table['D'] = 1;
4643 alt_notend_table['#'] = 1;
4644 alt_notend_table['&'] = 1;
4645 alt_notend_table['f'] = 1;
4646 alt_notend_table['F'] = 1;
4647 #ifdef REGISTER_PREFIX
4648 alt_notend_table[REGISTER_PREFIX] = 1;
4649 #endif
4650
4651 /* We need to put '(' in alt_notend_table to handle
4652 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
4653 alt_notend_table['('] = 1;
4654
4655 /* We need to put '@' in alt_notend_table to handle
4656 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
4657 alt_notend_table['@'] = 1;
4658
4659 /* We need to put digits in alt_notend_table to handle
4660 bfextu %d0{24:1},%d0 */
4661 alt_notend_table['0'] = 1;
4662 alt_notend_table['1'] = 1;
4663 alt_notend_table['2'] = 1;
4664 alt_notend_table['3'] = 1;
4665 alt_notend_table['4'] = 1;
4666 alt_notend_table['5'] = 1;
4667 alt_notend_table['6'] = 1;
4668 alt_notend_table['7'] = 1;
4669 alt_notend_table['8'] = 1;
4670 alt_notend_table['9'] = 1;
4671
4672 #ifndef MIT_SYNTAX_ONLY
4673 /* Insert pseudo ops, these have to go into the opcode table since
4674 gas expects pseudo ops to start with a dot. */
4675 {
4676 int n = 0;
4677
4678 while (mote_pseudo_table[n].poc_name)
4679 {
4680 hack = XOBNEW (&robyn, struct m68k_incant);
4681 str_hash_insert (op_hash,
4682 mote_pseudo_table[n].poc_name, hack, 0);
4683 hack->m_operands = 0;
4684 hack->m_opnum = n;
4685 n++;
4686 }
4687 }
4688 #endif
4689
4690 init_regtable ();
4691
4692 record_alignment (text_section, 2);
4693 record_alignment (data_section, 2);
4694 record_alignment (bss_section, 2);
4695 }
4696
4697
4698 /* This is called when a label is defined. */
4699
4700 void
m68k_frob_label(symbolS * sym)4701 m68k_frob_label (symbolS *sym)
4702 {
4703 struct m68k_tc_sy *n;
4704
4705 n = symbol_get_tc (sym);
4706 n->file = as_where (&n->line);
4707 n->text = 0;
4708 current_label = n;
4709
4710 dwarf2_emit_label (sym);
4711 }
4712
4713 /* This is called when a value that is not an instruction is emitted. */
4714
4715 void
m68k_flush_pending_output(void)4716 m68k_flush_pending_output (void)
4717 {
4718 current_label = NULL;
4719 }
4720
4721 /* This is called at the end of the assembly, when the final value of
4722 the label is known. We warn if this is a text symbol aligned at an
4723 odd location. */
4724
4725 void
m68k_frob_symbol(symbolS * sym)4726 m68k_frob_symbol (symbolS *sym)
4727 {
4728 if (S_GET_SEGMENT (sym) == reg_section
4729 && (int) S_GET_VALUE (sym) < 0)
4730 {
4731 S_SET_SEGMENT (sym, absolute_section);
4732 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4733 }
4734 else if ((S_GET_VALUE (sym) & 1) != 0)
4735 {
4736 struct m68k_tc_sy *l;
4737 l = symbol_get_tc (sym);
4738
4739 if (l->text)
4740 as_warn_where (l->file, l->line,
4741 _("text label `%s' aligned to odd boundary"),
4742 S_GET_NAME (sym));
4743 }
4744 }
4745
4746 /* This is called if we go in or out of MRI mode because of the .mri
4747 pseudo-op. */
4748
4749 void
m68k_mri_mode_change(int on)4750 m68k_mri_mode_change (int on)
4751 {
4752 if (on)
4753 {
4754 if (! flag_reg_prefix_optional)
4755 {
4756 flag_reg_prefix_optional = 1;
4757 #ifdef REGISTER_PREFIX
4758 init_regtable ();
4759 #endif
4760 }
4761 m68k_abspcadd = 1;
4762 if (! m68k_rel32_from_cmdline)
4763 m68k_rel32 = 0;
4764 }
4765 else
4766 {
4767 if (! reg_prefix_optional_seen)
4768 {
4769 #ifdef REGISTER_PREFIX_OPTIONAL
4770 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4771 #else
4772 flag_reg_prefix_optional = 0;
4773 #endif
4774 #ifdef REGISTER_PREFIX
4775 init_regtable ();
4776 #endif
4777 }
4778 m68k_abspcadd = 0;
4779 if (! m68k_rel32_from_cmdline)
4780 m68k_rel32 = 1;
4781 }
4782 }
4783
4784 const char *
md_atof(int type,char * litP,int * sizeP)4785 md_atof (int type, char *litP, int *sizeP)
4786 {
4787 return ieee_md_atof (type, litP, sizeP, true);
4788 }
4789
4790 void
md_number_to_chars(char * buf,valueT val,int n)4791 md_number_to_chars (char *buf, valueT val, int n)
4792 {
4793 number_to_chars_bigendian (buf, val, n);
4794 }
4795
4796 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg ATTRIBUTE_UNUSED)4797 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4798 {
4799 offsetT val = *valP;
4800 addressT upper_limit;
4801 offsetT lower_limit;
4802
4803 /* This is unnecessary but it convinces the native rs6000 compiler
4804 to generate the code we want. */
4805 char *buf = fixP->fx_frag->fr_literal;
4806 buf += fixP->fx_where;
4807 /* End ibm compiler workaround. */
4808
4809 val = SEXT (val);
4810
4811 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4812 fixP->fx_done = 1;
4813
4814 if (fixP->fx_addsy)
4815 {
4816 memset (buf, 0, fixP->fx_size);
4817 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
4818
4819 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4820 && !S_IS_DEFINED (fixP->fx_addsy)
4821 && !S_IS_WEAK (fixP->fx_addsy))
4822 S_SET_WEAK (fixP->fx_addsy);
4823
4824 switch (fixP->fx_r_type)
4825 {
4826 case BFD_RELOC_68K_TLS_GD32:
4827 case BFD_RELOC_68K_TLS_GD16:
4828 case BFD_RELOC_68K_TLS_GD8:
4829 case BFD_RELOC_68K_TLS_LDM32:
4830 case BFD_RELOC_68K_TLS_LDM16:
4831 case BFD_RELOC_68K_TLS_LDM8:
4832 case BFD_RELOC_68K_TLS_LDO32:
4833 case BFD_RELOC_68K_TLS_LDO16:
4834 case BFD_RELOC_68K_TLS_LDO8:
4835 case BFD_RELOC_68K_TLS_IE32:
4836 case BFD_RELOC_68K_TLS_IE16:
4837 case BFD_RELOC_68K_TLS_IE8:
4838 case BFD_RELOC_68K_TLS_LE32:
4839 case BFD_RELOC_68K_TLS_LE16:
4840 case BFD_RELOC_68K_TLS_LE8:
4841 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4842 break;
4843
4844 default:
4845 break;
4846 }
4847
4848 return;
4849 }
4850
4851 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4852 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4853 return;
4854
4855 switch (fixP->fx_size)
4856 {
4857 /* The cast to offsetT below are necessary to make code
4858 correct for machines where ints are smaller than offsetT. */
4859 case 1:
4860 *buf++ = val;
4861 upper_limit = 0x7f;
4862 lower_limit = - (offsetT) 0x80;
4863 break;
4864 case 2:
4865 *buf++ = (val >> 8);
4866 *buf++ = val;
4867 upper_limit = 0x7fff;
4868 lower_limit = - (offsetT) 0x8000;
4869 break;
4870 case 4:
4871 *buf++ = (val >> 24);
4872 *buf++ = (val >> 16);
4873 *buf++ = (val >> 8);
4874 *buf++ = val;
4875 upper_limit = 0x7fffffff;
4876 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
4877 break;
4878 default:
4879 BAD_CASE (fixP->fx_size);
4880 }
4881
4882 /* Fix up a negative reloc. */
4883 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4884 {
4885 fixP->fx_addsy = fixP->fx_subsy;
4886 fixP->fx_subsy = NULL;
4887 fixP->fx_tcbit = 1;
4888 }
4889
4890 /* For non-pc-relative values, it's conceivable we might get something
4891 like "0xff" for a byte field. So extend the upper part of the range
4892 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4893 so that we can do any range checking at all. */
4894 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4895 upper_limit = upper_limit * 2 + 1;
4896
4897 if ((addressT) val > upper_limit
4898 && (val > 0 || val < lower_limit))
4899 as_bad_where (fixP->fx_file, fixP->fx_line,
4900 _("value %ld out of range"), (long)val);
4901
4902 /* A one byte PC-relative reloc means a short branch. We can't use
4903 a short branch with a value of 0 or -1, because those indicate
4904 different opcodes (branches with longer offsets). fixup_segment
4905 in write.c may have clobbered fx_pcrel, so we need to examine the
4906 reloc type. */
4907 if ((fixP->fx_pcrel
4908 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4909 && fixP->fx_size == 1
4910 && (fixP->fx_addsy == NULL
4911 || S_IS_DEFINED (fixP->fx_addsy))
4912 && (val == 0 || val == -1))
4913 as_bad_where (fixP->fx_file, fixP->fx_line,
4914 _("invalid byte branch offset"));
4915 }
4916
4917 /* *fragP has been relaxed to its final size, and now needs to have
4918 the bytes inside it modified to conform to the new size There is UGLY
4919 MAGIC here. ..
4920 */
4921 static void
md_convert_frag_1(fragS * fragP)4922 md_convert_frag_1 (fragS *fragP)
4923 {
4924 long disp;
4925 fixS *fixP = NULL;
4926
4927 /* Address in object code of the displacement. */
4928 int object_address = fragP->fr_fix + fragP->fr_address;
4929
4930 /* Address in gas core of the place to store the displacement. */
4931 /* This convinces the native rs6000 compiler to generate the code we
4932 want. */
4933 char *buffer_address = fragP->fr_literal;
4934 buffer_address += fragP->fr_fix;
4935 /* End ibm compiler workaround. */
4936
4937 /* The displacement of the address, from current location. */
4938 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4939 disp = (disp + fragP->fr_offset) - object_address;
4940
4941 switch (fragP->fr_subtype)
4942 {
4943 case TAB (BRANCHBWL, BYTE):
4944 case TAB (BRABSJUNC, BYTE):
4945 case TAB (BRABSJCOND, BYTE):
4946 case TAB (BRANCHBW, BYTE):
4947 case TAB (BRANCHBWPL, BYTE):
4948 know (issbyte (disp));
4949 if (disp == 0)
4950 as_bad_where (fragP->fr_file, fragP->fr_line,
4951 _("short branch with zero offset: use :w"));
4952 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
4953 fragP->fr_offset, 1, RELAX_RELOC_PC8);
4954 fixP->fx_pcrel_adjust = -1;
4955 break;
4956 case TAB (BRANCHBWL, SHORT):
4957 case TAB (BRABSJUNC, SHORT):
4958 case TAB (BRABSJCOND, SHORT):
4959 case TAB (BRANCHBW, SHORT):
4960 case TAB (BRANCHBWPL, SHORT):
4961 fragP->fr_opcode[1] = 0x00;
4962 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4963 fragP->fr_offset, 1, RELAX_RELOC_PC16);
4964 fragP->fr_fix += 2;
4965 break;
4966 case TAB (BRANCHBWL, LONG):
4967 fragP->fr_opcode[1] = (char) 0xFF;
4968 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4969 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4970 fragP->fr_fix += 4;
4971 break;
4972 case TAB (BRANCHBWPL, LONG):
4973 /* Here we are converting an unconditional branch into a pair of
4974 conditional branches, in order to get the range. */
4975 fragP->fr_opcode[0] = 0x66; /* bne */
4976 fragP->fr_opcode[1] = 0xFF;
4977 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4978 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4979 fixP->fx_file = fragP->fr_file;
4980 fixP->fx_line = fragP->fr_line;
4981 fragP->fr_fix += 4; /* Skip first offset */
4982 buffer_address += 4;
4983 *buffer_address++ = 0x67; /* beq */
4984 *buffer_address++ = 0xff;
4985 fragP->fr_fix += 2; /* Skip second branch opcode */
4986 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4988 fragP->fr_fix += 4;
4989 break;
4990 case TAB (BRABSJUNC, LONG):
4991 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
4992 {
4993 if (flag_keep_pcrel)
4994 as_bad_where (fragP->fr_file, fragP->fr_line,
4995 _("Conversion of PC relative BSR to absolute JSR"));
4996 fragP->fr_opcode[0] = 0x4E;
4997 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
4998 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4999 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5000 fragP->fr_fix += 4;
5001 }
5002 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5003 {
5004 if (flag_keep_pcrel)
5005 as_bad_where (fragP->fr_file, fragP->fr_line,
5006 _("Conversion of PC relative branch to absolute jump"));
5007 fragP->fr_opcode[0] = 0x4E;
5008 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
5009 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5010 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5011 fragP->fr_fix += 4;
5012 }
5013 else
5014 {
5015 /* This cannot happen, because jbsr and jbra are the only two
5016 unconditional branches. */
5017 abort ();
5018 }
5019 break;
5020 case TAB (BRABSJCOND, LONG):
5021 if (flag_keep_pcrel)
5022 as_bad_where (fragP->fr_file, fragP->fr_line,
5023 _("Conversion of PC relative conditional branch to absolute jump"));
5024
5025 /* Only Bcc 68000 instructions can come here
5026 Change bcc into b!cc/jmp absl long. */
5027 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5028 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
5029
5030 /* JF: these used to be fr_opcode[2,3], but they may be in a
5031 different frag, in which case referring to them is a no-no.
5032 Only fr_opcode[0,1] are guaranteed to work. */
5033 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5034 *buffer_address++ = (char) 0xf9;
5035 fragP->fr_fix += 2; /* Account for jmp instruction. */
5036 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5037 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5038 fragP->fr_fix += 4;
5039 break;
5040 case TAB (FBRANCH, SHORT):
5041 know ((fragP->fr_opcode[1] & 0x40) == 0);
5042 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5043 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5044 fragP->fr_fix += 2;
5045 break;
5046 case TAB (FBRANCH, LONG):
5047 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
5048 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5049 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5050 fragP->fr_fix += 4;
5051 break;
5052 case TAB (DBCCLBR, SHORT):
5053 case TAB (DBCCABSJ, SHORT):
5054 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5055 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5056 fragP->fr_fix += 2;
5057 break;
5058 case TAB (DBCCLBR, LONG):
5059 /* Only DBcc instructions can come here.
5060 Change dbcc into dbcc/bral.
5061 JF: these used to be fr_opcode[2-7], but that's wrong. */
5062 *buffer_address++ = 0x00; /* Branch offset = 4. */
5063 *buffer_address++ = 0x04;
5064 *buffer_address++ = 0x60; /* Put in bra pc+6. */
5065 *buffer_address++ = 0x06;
5066 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5067 *buffer_address++ = (char) 0xff;
5068
5069 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5070 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5071 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5072 fragP->fr_fix += 4;
5073 break;
5074 case TAB (DBCCABSJ, LONG):
5075 /* Only DBcc instructions can come here.
5076 Change dbcc into dbcc/jmp.
5077 JF: these used to be fr_opcode[2-7], but that's wrong. */
5078 if (flag_keep_pcrel)
5079 as_bad_where (fragP->fr_file, fragP->fr_line,
5080 _("Conversion of PC relative conditional branch to absolute jump"));
5081
5082 *buffer_address++ = 0x00; /* Branch offset = 4. */
5083 *buffer_address++ = 0x04;
5084 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
5085 *buffer_address++ = 0x06;
5086 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
5087 *buffer_address++ = (char) 0xf9;
5088
5089 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
5090 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5091 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5092 fragP->fr_fix += 4;
5093 break;
5094 case TAB (PCREL1632, SHORT):
5095 fragP->fr_opcode[1] &= ~0x3F;
5096 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5097 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5098 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5099 fragP->fr_fix += 2;
5100 break;
5101 case TAB (PCREL1632, LONG):
5102 /* Already set to mode 7.3; this indicates: PC indirect with
5103 suppressed index, 32-bit displacement. */
5104 *buffer_address++ = 0x01;
5105 *buffer_address++ = 0x70;
5106 fragP->fr_fix += 2;
5107 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5108 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5109 fixP->fx_pcrel_adjust = 2;
5110 fragP->fr_fix += 4;
5111 break;
5112 case TAB (PCINDEX, BYTE):
5113 gas_assert (fragP->fr_fix >= 2);
5114 buffer_address[-2] &= ~1;
5115 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5116 fragP->fr_offset, 1, RELAX_RELOC_PC8);
5117 fixP->fx_pcrel_adjust = 1;
5118 break;
5119 case TAB (PCINDEX, SHORT):
5120 gas_assert (fragP->fr_fix >= 2);
5121 buffer_address[-2] |= 0x1;
5122 buffer_address[-1] = 0x20;
5123 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5124 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5125 fixP->fx_pcrel_adjust = 2;
5126 fragP->fr_fix += 2;
5127 break;
5128 case TAB (PCINDEX, LONG):
5129 gas_assert (fragP->fr_fix >= 2);
5130 buffer_address[-2] |= 0x1;
5131 buffer_address[-1] = 0x30;
5132 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5133 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5134 fixP->fx_pcrel_adjust = 2;
5135 fragP->fr_fix += 4;
5136 break;
5137 case TAB (ABSTOPCREL, SHORT):
5138 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5139 fragP->fr_offset, 1, RELAX_RELOC_PC16);
5140 fragP->fr_fix += 2;
5141 break;
5142 case TAB (ABSTOPCREL, LONG):
5143 if (flag_keep_pcrel)
5144 as_bad_where (fragP->fr_file, fragP->fr_line,
5145 _("Conversion of PC relative displacement to absolute"));
5146 /* The thing to do here is force it to ABSOLUTE LONG, since
5147 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
5148 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5149 abort ();
5150 fragP->fr_opcode[1] &= ~0x3F;
5151 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
5152 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5153 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5154 fragP->fr_fix += 4;
5155 break;
5156 }
5157 if (fixP)
5158 {
5159 fixP->fx_file = fragP->fr_file;
5160 fixP->fx_line = fragP->fr_line;
5161 }
5162 }
5163
5164 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec ATTRIBUTE_UNUSED,fragS * fragP)5165 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5166 segT sec ATTRIBUTE_UNUSED,
5167 fragS *fragP)
5168 {
5169 md_convert_frag_1 (fragP);
5170 }
5171
5172 /* Force truly undefined symbols to their maximum size, and generally set up
5173 the frag list to be relaxed
5174 */
5175 int
md_estimate_size_before_relax(fragS * fragP,segT segment)5176 md_estimate_size_before_relax (fragS *fragP, segT segment)
5177 {
5178 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
5179 switch (fragP->fr_subtype)
5180 {
5181 case TAB (BRANCHBWL, SZ_UNDEF):
5182 case TAB (BRANCHBWPL, SZ_UNDEF):
5183 case TAB (BRABSJUNC, SZ_UNDEF):
5184 case TAB (BRABSJCOND, SZ_UNDEF):
5185 {
5186 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5187 && relaxable_symbol (fragP->fr_symbol))
5188 {
5189 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5190 }
5191 else if (flag_short_refs)
5192 {
5193 /* Symbol is undefined and we want short ref. */
5194 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5195 }
5196 else
5197 {
5198 /* Symbol is still undefined. Make it LONG. */
5199 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5200 }
5201 break;
5202 }
5203
5204 case TAB (BRANCHBW, SZ_UNDEF):
5205 {
5206 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5207 && relaxable_symbol (fragP->fr_symbol))
5208 {
5209 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5210 }
5211 else
5212 {
5213 /* Symbol is undefined and we don't have long branches. */
5214 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5215 }
5216 break;
5217 }
5218
5219 case TAB (FBRANCH, SZ_UNDEF):
5220 case TAB (DBCCLBR, SZ_UNDEF):
5221 case TAB (DBCCABSJ, SZ_UNDEF):
5222 case TAB (PCREL1632, SZ_UNDEF):
5223 {
5224 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5225 && relaxable_symbol (fragP->fr_symbol))
5226 || flag_short_refs)
5227 {
5228 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5229 }
5230 else
5231 {
5232 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5233 }
5234 break;
5235 }
5236
5237 case TAB (PCINDEX, SZ_UNDEF):
5238 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5239 && relaxable_symbol (fragP->fr_symbol)))
5240 {
5241 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5242 }
5243 else
5244 {
5245 fragP->fr_subtype = TAB (PCINDEX, LONG);
5246 }
5247 break;
5248
5249 case TAB (ABSTOPCREL, SZ_UNDEF):
5250 {
5251 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5252 && relaxable_symbol (fragP->fr_symbol)))
5253 {
5254 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5255 }
5256 else
5257 {
5258 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5259 }
5260 break;
5261 }
5262
5263 default:
5264 break;
5265 }
5266
5267 /* Now that SZ_UNDEF are taken care of, check others. */
5268 switch (fragP->fr_subtype)
5269 {
5270 case TAB (BRANCHBWL, BYTE):
5271 case TAB (BRABSJUNC, BYTE):
5272 case TAB (BRABSJCOND, BYTE):
5273 case TAB (BRANCHBW, BYTE):
5274 /* We can't do a short jump to the next instruction, so in that
5275 case we force word mode. If the symbol is at the start of a
5276 frag, and it is the next frag with any data in it (usually
5277 this is just the next frag, but assembler listings may
5278 introduce empty frags), we must use word mode. */
5279 if (fragP->fr_symbol)
5280 {
5281 fragS *sym_frag;
5282
5283 sym_frag = symbol_get_frag (fragP->fr_symbol);
5284 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5285 {
5286 fragS *l;
5287
5288 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5289 if (l->fr_fix != 0)
5290 break;
5291 if (l == sym_frag)
5292 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5293 }
5294 }
5295 break;
5296 default:
5297 break;
5298 }
5299 return md_relax_table[fragP->fr_subtype].rlx_length;
5300 }
5301
5302 #ifndef WORKING_DOT_WORD
5303 int md_short_jump_size = 4;
5304 int md_long_jump_size = 6;
5305
5306 void
md_create_short_jump(char * ptr,addressT from_addr,addressT to_addr,fragS * frag ATTRIBUTE_UNUSED,symbolS * to_symbol ATTRIBUTE_UNUSED)5307 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5308 fragS *frag ATTRIBUTE_UNUSED,
5309 symbolS *to_symbol ATTRIBUTE_UNUSED)
5310 {
5311 valueT offset;
5312
5313 offset = to_addr - (from_addr + 2);
5314
5315 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5316 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5317 }
5318
5319 void
md_create_long_jump(char * ptr,addressT from_addr,addressT to_addr,fragS * frag,symbolS * to_symbol)5320 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5321 fragS *frag, symbolS *to_symbol)
5322 {
5323 valueT offset;
5324
5325 if (!HAVE_LONG_BRANCH (current_architecture))
5326 {
5327 if (flag_keep_pcrel)
5328 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5329 offset = to_addr - S_GET_VALUE (to_symbol);
5330 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5331 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5332 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5333 0, NO_RELOC);
5334 }
5335 else
5336 {
5337 offset = to_addr - (from_addr + 2);
5338 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5339 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5340 }
5341 }
5342
5343 #endif
5344
5345 /* Different values of OK tell what it's OK to return. Things that
5346 aren't OK are an error (what a shock, no?)
5347
5348 0: Everything is OK
5349 10: Absolute 1:8 only
5350 20: Absolute 0:7 only
5351 30: absolute 0:15 only
5352 40: Absolute 0:31 only
5353 50: absolute 0:127 only
5354 55: absolute -64:63 only
5355 60: absolute -128:127 only
5356 65: absolute 0:511 only
5357 70: absolute 0:4095 only
5358 80: absolute -1, 1:7 only
5359 90: No bignums. */
5360
5361 static int
get_num(struct m68k_exp * exp,int ok)5362 get_num (struct m68k_exp *exp, int ok)
5363 {
5364 if (exp->exp.X_op == O_absent)
5365 {
5366 /* Do the same thing the VAX asm does. */
5367 op (exp) = O_constant;
5368 adds (exp) = 0;
5369 subs (exp) = 0;
5370 offs (exp) = 0;
5371 if (ok == 10)
5372 {
5373 as_warn (_("expression out of range: defaulting to 1"));
5374 offs (exp) = 1;
5375 }
5376 }
5377 else if (exp->exp.X_op == O_constant)
5378 {
5379 switch (ok)
5380 {
5381 case 10:
5382 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5383 {
5384 as_warn (_("expression out of range: defaulting to 1"));
5385 offs (exp) = 1;
5386 }
5387 break;
5388 case 20:
5389 if ((valueT) TRUNC (offs (exp)) > 7)
5390 goto outrange;
5391 break;
5392 case 30:
5393 if ((valueT) TRUNC (offs (exp)) > 15)
5394 goto outrange;
5395 break;
5396 case 40:
5397 if ((valueT) TRUNC (offs (exp)) > 32)
5398 goto outrange;
5399 break;
5400 case 50:
5401 if ((valueT) TRUNC (offs (exp)) > 127)
5402 goto outrange;
5403 break;
5404 case 55:
5405 if ((valueT) SEXT (offs (exp)) + 64 > 127)
5406 goto outrange;
5407 break;
5408 case 60:
5409 if ((valueT) SEXT (offs (exp)) + 128 > 255)
5410 goto outrange;
5411 break;
5412 case 65:
5413 if ((valueT) TRUNC (offs (exp)) > 511)
5414 goto outrange;
5415 break;
5416 case 70:
5417 if ((valueT) TRUNC (offs (exp)) > 4095)
5418 {
5419 outrange:
5420 as_warn (_("expression out of range: defaulting to 0"));
5421 offs (exp) = 0;
5422 }
5423 break;
5424 case 80:
5425 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5426 && (valueT) TRUNC (offs (exp)) - 1 > 6)
5427 {
5428 as_warn (_("expression out of range: defaulting to 1"));
5429 offs (exp) = 1;
5430 }
5431 break;
5432 default:
5433 break;
5434 }
5435 }
5436 else if (exp->exp.X_op == O_big)
5437 {
5438 if (offs (exp) <= 0 /* flonum. */
5439 && (ok == 90 /* no bignums */
5440 || (ok > 10 /* Small-int ranges including 0 ok. */
5441 /* If we have a flonum zero, a zero integer should
5442 do as well (e.g., in moveq). */
5443 && generic_floating_point_number.exponent == 0
5444 && generic_floating_point_number.low[0] == 0)))
5445 {
5446 /* HACK! Turn it into a long. */
5447 LITTLENUM_TYPE words[6];
5448
5449 gen_to_words (words, 2, 8L); /* These numbers are magic! */
5450 op (exp) = O_constant;
5451 adds (exp) = 0;
5452 subs (exp) = 0;
5453 offs (exp) = words[1] | (words[0] << 16);
5454 }
5455 else if (ok != 0)
5456 {
5457 op (exp) = O_constant;
5458 adds (exp) = 0;
5459 subs (exp) = 0;
5460 offs (exp) = (ok == 10) ? 1 : 0;
5461 as_warn (_("Can't deal with expression; defaulting to %ld"),
5462 (long) offs (exp));
5463 }
5464 }
5465 else
5466 {
5467 if (ok >= 10 && ok <= 80)
5468 {
5469 op (exp) = O_constant;
5470 adds (exp) = 0;
5471 subs (exp) = 0;
5472 offs (exp) = (ok == 10) ? 1 : 0;
5473 as_warn (_("Can't deal with expression; defaulting to %ld"),
5474 (long) offs (exp));
5475 }
5476 }
5477
5478 if (exp->size != SIZE_UNSPEC)
5479 {
5480 switch (exp->size)
5481 {
5482 case SIZE_UNSPEC:
5483 case SIZE_LONG:
5484 break;
5485 case SIZE_BYTE:
5486 if (!isbyte (offs (exp)))
5487 as_warn (_("expression doesn't fit in BYTE"));
5488 break;
5489 case SIZE_WORD:
5490 if (!isword (offs (exp)))
5491 as_warn (_("expression doesn't fit in WORD"));
5492 break;
5493 }
5494 }
5495
5496 return offs (exp);
5497 }
5498
5499 /* These are the back-ends for the various machine dependent pseudo-ops. */
5500
5501 static void
s_data1(int ignore ATTRIBUTE_UNUSED)5502 s_data1 (int ignore ATTRIBUTE_UNUSED)
5503 {
5504 subseg_set (data_section, 1);
5505 demand_empty_rest_of_line ();
5506 }
5507
5508 static void
s_data2(int ignore ATTRIBUTE_UNUSED)5509 s_data2 (int ignore ATTRIBUTE_UNUSED)
5510 {
5511 subseg_set (data_section, 2);
5512 demand_empty_rest_of_line ();
5513 }
5514
5515 static void
s_even(int ignore ATTRIBUTE_UNUSED)5516 s_even (int ignore ATTRIBUTE_UNUSED)
5517 {
5518 int temp;
5519 long temp_fill;
5520
5521 temp = 1; /* JF should be 2? */
5522 temp_fill = get_absolute_expression ();
5523 if (!need_pass_2) /* Never make frag if expect extra pass. */
5524 frag_align (temp, (int) temp_fill, 0);
5525 demand_empty_rest_of_line ();
5526 record_alignment (now_seg, temp);
5527 }
5528
5529 static void
s_proc(int ignore ATTRIBUTE_UNUSED)5530 s_proc (int ignore ATTRIBUTE_UNUSED)
5531 {
5532 demand_empty_rest_of_line ();
5533 }
5534
5535 /* Pseudo-ops handled for MRI compatibility. */
5536
5537 /* This function returns non-zero if the argument is a conditional
5538 pseudo-op. This is called when checking whether a pending
5539 alignment is needed. */
5540
5541 int
m68k_conditional_pseudoop(const pseudo_typeS * pop)5542 m68k_conditional_pseudoop (const pseudo_typeS *pop)
5543 {
5544 return (pop->poc_handler == s_mri_if
5545 || pop->poc_handler == s_mri_else);
5546 }
5547
5548 /* Handle an MRI style chip specification. */
5549
5550 static void
mri_chip(void)5551 mri_chip (void)
5552 {
5553 char *s;
5554 char c;
5555 int i;
5556
5557 s = input_line_pointer;
5558 /* We can't use get_symbol_name since the processor names are not proper
5559 symbols. */
5560 while (is_part_of_name (c = *input_line_pointer++))
5561 ;
5562 *--input_line_pointer = 0;
5563 for (i = 0; m68k_cpus[i].name; i++)
5564 if (strcasecmp (s, m68k_cpus[i].name) == 0)
5565 break;
5566 if (!m68k_cpus[i].name)
5567 {
5568 as_bad (_("%s: unrecognized processor name"), s);
5569 *input_line_pointer = c;
5570 ignore_rest_of_line ();
5571 return;
5572 }
5573 *input_line_pointer = c;
5574
5575 if (*input_line_pointer == '/')
5576 current_architecture = 0;
5577 else
5578 current_architecture &= m68881 | m68851;
5579 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5580 control_regs = m68k_cpus[i].control_regs;
5581
5582 while (*input_line_pointer == '/')
5583 {
5584 ++input_line_pointer;
5585 s = input_line_pointer;
5586 /* We can't use get_symbol_name since the processor names are not
5587 proper symbols. */
5588 while (is_part_of_name (c = *input_line_pointer++))
5589 ;
5590 *--input_line_pointer = 0;
5591 if (strcmp (s, "68881") == 0)
5592 current_architecture |= m68881;
5593 else if (strcmp (s, "68851") == 0)
5594 current_architecture |= m68851;
5595 *input_line_pointer = c;
5596 }
5597 }
5598
5599 /* The MRI CHIP pseudo-op. */
5600
5601 static void
s_chip(int ignore ATTRIBUTE_UNUSED)5602 s_chip (int ignore ATTRIBUTE_UNUSED)
5603 {
5604 char *stop = NULL;
5605 char stopc;
5606
5607 if (flag_mri)
5608 stop = mri_comment_field (&stopc);
5609 mri_chip ();
5610 if (flag_mri)
5611 mri_comment_end (stop, stopc);
5612 demand_empty_rest_of_line ();
5613 }
5614
5615 /* The MRI FOPT pseudo-op. */
5616
5617 static void
s_fopt(int ignore ATTRIBUTE_UNUSED)5618 s_fopt (int ignore ATTRIBUTE_UNUSED)
5619 {
5620 SKIP_WHITESPACE ();
5621
5622 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5623 {
5624 int temp;
5625
5626 input_line_pointer += 3;
5627 temp = get_absolute_expression ();
5628 if (temp < 0 || temp > 7)
5629 as_bad (_("bad coprocessor id"));
5630 else
5631 m68k_float_copnum = COP0 + temp;
5632 }
5633 else
5634 {
5635 as_bad (_("unrecognized fopt option"));
5636 ignore_rest_of_line ();
5637 return;
5638 }
5639
5640 demand_empty_rest_of_line ();
5641 }
5642
5643 /* The structure used to handle the MRI OPT pseudo-op. */
5644
5645 struct opt_action
5646 {
5647 /* The name of the option. */
5648 const char *name;
5649
5650 /* If this is not NULL, just call this function. The first argument
5651 is the ARG field of this structure, the second argument is
5652 whether the option was negated. */
5653 void (*pfn) (int arg, int on);
5654
5655 /* If this is not NULL, and the PFN field is NULL, set the variable
5656 this points to. Set it to the ARG field if the option was not
5657 negated, and the NOTARG field otherwise. */
5658 int *pvar;
5659
5660 /* The value to pass to PFN or to assign to *PVAR. */
5661 int arg;
5662
5663 /* The value to assign to *PVAR if the option is negated. If PFN is
5664 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5665 the option may not be negated. */
5666 int notarg;
5667 };
5668
5669 /* The table used to handle the MRI OPT pseudo-op. */
5670
5671 static void skip_to_comma (int, int);
5672 static void opt_nest (int, int);
5673 static void opt_chip (int, int);
5674 static void opt_list (int, int);
5675 static void opt_list_symbols (int, int);
5676
5677 static const struct opt_action opt_table[] =
5678 {
5679 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5680
5681 /* We do relaxing, so there is little use for these options. */
5682 { "b", 0, 0, 0, 0 },
5683 { "brs", 0, 0, 0, 0 },
5684 { "brb", 0, 0, 0, 0 },
5685 { "brl", 0, 0, 0, 0 },
5686 { "brw", 0, 0, 0, 0 },
5687
5688 { "c", 0, 0, 0, 0 },
5689 { "cex", 0, 0, 0, 0 },
5690 { "case", 0, &symbols_case_sensitive, 1, 0 },
5691 { "cl", 0, 0, 0, 0 },
5692 { "cre", 0, 0, 0, 0 },
5693 { "d", 0, &flag_keep_locals, 1, 0 },
5694 { "e", 0, 0, 0, 0 },
5695 { "f", 0, &flag_short_refs, 1, 0 },
5696 { "frs", 0, &flag_short_refs, 1, 0 },
5697 { "frl", 0, &flag_short_refs, 0, 1 },
5698 { "g", 0, 0, 0, 0 },
5699 { "i", 0, 0, 0, 0 },
5700 { "m", 0, 0, 0, 0 },
5701 { "mex", 0, 0, 0, 0 },
5702 { "mc", 0, 0, 0, 0 },
5703 { "md", 0, 0, 0, 0 },
5704 { "nest", opt_nest, 0, 0, 0 },
5705 { "next", skip_to_comma, 0, 0, 0 },
5706 { "o", 0, 0, 0, 0 },
5707 { "old", 0, 0, 0, 0 },
5708 { "op", skip_to_comma, 0, 0, 0 },
5709 { "pco", 0, 0, 0, 0 },
5710 { "p", opt_chip, 0, 0, 0 },
5711 { "pcr", 0, 0, 0, 0 },
5712 { "pcs", 0, 0, 0, 0 },
5713 { "r", 0, 0, 0, 0 },
5714 { "quick", 0, &m68k_quick, 1, 0 },
5715 { "rel32", 0, &m68k_rel32, 1, 0 },
5716 { "s", opt_list, 0, 0, 0 },
5717 { "t", opt_list_symbols, 0, 0, 0 },
5718 { "w", 0, &flag_no_warnings, 0, 1 },
5719 { "x", 0, 0, 0, 0 }
5720 };
5721
5722 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5723
5724 /* The MRI OPT pseudo-op. */
5725
5726 static void
s_opt(int ignore ATTRIBUTE_UNUSED)5727 s_opt (int ignore ATTRIBUTE_UNUSED)
5728 {
5729 do
5730 {
5731 int t;
5732 char *s;
5733 char c;
5734 int i;
5735 const struct opt_action *o;
5736
5737 SKIP_WHITESPACE ();
5738
5739 t = 1;
5740 if (*input_line_pointer == '-')
5741 {
5742 ++input_line_pointer;
5743 t = 0;
5744 }
5745 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5746 {
5747 input_line_pointer += 2;
5748 t = 0;
5749 }
5750
5751 c = get_symbol_name (&s);
5752
5753 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5754 {
5755 if (strcasecmp (s, o->name) == 0)
5756 {
5757 if (o->pfn)
5758 {
5759 /* Restore input_line_pointer now in case the option
5760 takes arguments. */
5761 (void) restore_line_pointer (c);
5762 (*o->pfn) (o->arg, t);
5763 }
5764 else if (o->pvar != NULL)
5765 {
5766 if (! t && o->arg == o->notarg)
5767 as_bad (_("option `%s' may not be negated"), s);
5768 restore_line_pointer (c);
5769 *o->pvar = t ? o->arg : o->notarg;
5770 }
5771 else
5772 *input_line_pointer = c;
5773 break;
5774 }
5775 }
5776 if (i >= OPTCOUNT)
5777 {
5778 as_bad (_("option `%s' not recognized"), s);
5779 restore_line_pointer (c);
5780 }
5781 }
5782 while (*input_line_pointer++ == ',');
5783
5784 /* Move back to terminating character. */
5785 --input_line_pointer;
5786 demand_empty_rest_of_line ();
5787 }
5788
5789 /* Skip ahead to a comma. This is used for OPT options which we do
5790 not support and which take arguments. */
5791
5792 static void
skip_to_comma(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5793 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5794 {
5795 while (*input_line_pointer != ','
5796 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5797 ++input_line_pointer;
5798 }
5799
5800 /* Handle the OPT NEST=depth option. */
5801
5802 static void
opt_nest(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5803 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5804 {
5805 if (*input_line_pointer != '=')
5806 {
5807 as_bad (_("bad format of OPT NEST=depth"));
5808 return;
5809 }
5810
5811 ++input_line_pointer;
5812 max_macro_nest = get_absolute_expression ();
5813 }
5814
5815 /* Handle the OPT P=chip option. */
5816
5817 static void
opt_chip(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5818 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5819 {
5820 if (*input_line_pointer != '=')
5821 {
5822 /* This is just OPT P, which we do not support. */
5823 return;
5824 }
5825
5826 ++input_line_pointer;
5827 mri_chip ();
5828 }
5829
5830 /* Handle the OPT S option. */
5831
5832 static void
opt_list(int arg ATTRIBUTE_UNUSED,int on)5833 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5834 {
5835 listing_list (on);
5836 }
5837
5838 /* Handle the OPT T option. */
5839
5840 static void
opt_list_symbols(int arg ATTRIBUTE_UNUSED,int on)5841 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5842 {
5843 if (on)
5844 listing |= LISTING_SYMBOLS;
5845 else
5846 listing &= ~LISTING_SYMBOLS;
5847 }
5848
5849 /* Handle the MRI REG pseudo-op. */
5850
5851 static void
s_reg(int ignore ATTRIBUTE_UNUSED)5852 s_reg (int ignore ATTRIBUTE_UNUSED)
5853 {
5854 char *s;
5855 int c;
5856 struct m68k_op rop;
5857 int mask;
5858 char *stop = NULL;
5859 char stopc;
5860
5861 if (line_label == NULL)
5862 {
5863 as_bad (_("missing label"));
5864 ignore_rest_of_line ();
5865 return;
5866 }
5867
5868 if (flag_mri)
5869 stop = mri_comment_field (&stopc);
5870
5871 SKIP_WHITESPACE ();
5872
5873 s = input_line_pointer;
5874 while (ISALNUM (*input_line_pointer)
5875 #ifdef REGISTER_PREFIX
5876 || *input_line_pointer == REGISTER_PREFIX
5877 #endif
5878 || *input_line_pointer == '/'
5879 || *input_line_pointer == '-')
5880 ++input_line_pointer;
5881 c = *input_line_pointer;
5882 *input_line_pointer = '\0';
5883
5884 if (m68k_ip_op (s, &rop) != 0)
5885 {
5886 if (rop.error == NULL)
5887 as_bad (_("bad register list"));
5888 else
5889 as_bad (_("bad register list: %s"), rop.error);
5890 *input_line_pointer = c;
5891 ignore_rest_of_line ();
5892 return;
5893 }
5894
5895 *input_line_pointer = c;
5896
5897 if (rop.mode == REGLST)
5898 mask = rop.mask;
5899 else if (rop.mode == DREG)
5900 mask = 1 << (rop.reg - DATA0);
5901 else if (rop.mode == AREG)
5902 mask = 1 << (rop.reg - ADDR0 + 8);
5903 else if (rop.mode == FPREG)
5904 mask = 1 << (rop.reg - FP0 + 16);
5905 else if (rop.mode == CONTROL
5906 && rop.reg == FPI)
5907 mask = 1 << 24;
5908 else if (rop.mode == CONTROL
5909 && rop.reg == FPS)
5910 mask = 1 << 25;
5911 else if (rop.mode == CONTROL
5912 && rop.reg == FPC)
5913 mask = 1 << 26;
5914 else
5915 {
5916 as_bad (_("bad register list"));
5917 ignore_rest_of_line ();
5918 return;
5919 }
5920
5921 S_SET_SEGMENT (line_label, reg_section);
5922 S_SET_VALUE (line_label, ~mask);
5923 symbol_set_frag (line_label, &zero_address_frag);
5924
5925 if (flag_mri)
5926 mri_comment_end (stop, stopc);
5927
5928 demand_empty_rest_of_line ();
5929 }
5930
5931 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5932
5933 struct save_opts
5934 {
5935 struct save_opts *next;
5936 int abspcadd;
5937 int symbols_case_sensitive;
5938 int keep_locals;
5939 int short_refs;
5940 int architecture;
5941 const enum m68k_register *control_regs;
5942 int quick;
5943 int rel32;
5944 int listing;
5945 int no_warnings;
5946 /* FIXME: We don't save OPT S. */
5947 };
5948
5949 /* This variable holds the stack of saved options. */
5950
5951 static struct save_opts *save_stack;
5952
5953 /* The MRI SAVE pseudo-op. */
5954
5955 static void
s_save(int ignore ATTRIBUTE_UNUSED)5956 s_save (int ignore ATTRIBUTE_UNUSED)
5957 {
5958 struct save_opts *s;
5959
5960 s = XNEW (struct save_opts);
5961 s->abspcadd = m68k_abspcadd;
5962 s->symbols_case_sensitive = symbols_case_sensitive;
5963 s->keep_locals = flag_keep_locals;
5964 s->short_refs = flag_short_refs;
5965 s->architecture = current_architecture;
5966 s->control_regs = control_regs;
5967 s->quick = m68k_quick;
5968 s->rel32 = m68k_rel32;
5969 s->listing = listing;
5970 s->no_warnings = flag_no_warnings;
5971
5972 s->next = save_stack;
5973 save_stack = s;
5974
5975 demand_empty_rest_of_line ();
5976 }
5977
5978 /* The MRI RESTORE pseudo-op. */
5979
5980 static void
s_restore(int ignore ATTRIBUTE_UNUSED)5981 s_restore (int ignore ATTRIBUTE_UNUSED)
5982 {
5983 struct save_opts *s;
5984
5985 if (save_stack == NULL)
5986 {
5987 as_bad (_("restore without save"));
5988 ignore_rest_of_line ();
5989 return;
5990 }
5991
5992 s = save_stack;
5993 save_stack = s->next;
5994
5995 m68k_abspcadd = s->abspcadd;
5996 symbols_case_sensitive = s->symbols_case_sensitive;
5997 flag_keep_locals = s->keep_locals;
5998 flag_short_refs = s->short_refs;
5999 current_architecture = s->architecture;
6000 control_regs = s->control_regs;
6001 m68k_quick = s->quick;
6002 m68k_rel32 = s->rel32;
6003 listing = s->listing;
6004 flag_no_warnings = s->no_warnings;
6005
6006 free (s);
6007
6008 demand_empty_rest_of_line ();
6009 }
6010
6011 /* Types of MRI structured control directives. */
6012
6013 enum mri_control_type
6014 {
6015 mri_for,
6016 mri_if,
6017 mri_repeat,
6018 mri_while
6019 };
6020
6021 /* This structure is used to stack the MRI structured control
6022 directives. */
6023
6024 struct mri_control_info
6025 {
6026 /* The directive within which this one is enclosed. */
6027 struct mri_control_info *outer;
6028
6029 /* The type of directive. */
6030 enum mri_control_type type;
6031
6032 /* Whether an ELSE has been in an IF. */
6033 int else_seen;
6034
6035 /* The add or sub statement at the end of a FOR. */
6036 char *incr;
6037
6038 /* The label of the top of a FOR or REPEAT loop. */
6039 char *top;
6040
6041 /* The label to jump to for the next iteration, or the else
6042 expression of a conditional. */
6043 char *next;
6044
6045 /* The label to jump to to break out of the loop, or the label past
6046 the end of a conditional. */
6047 char *bottom;
6048 };
6049
6050 /* The stack of MRI structured control directives. */
6051
6052 static struct mri_control_info *mri_control_stack;
6053
6054 /* The current MRI structured control directive index number, used to
6055 generate label names. */
6056
6057 static int mri_control_index;
6058
6059 /* Assemble an instruction for an MRI structured control directive. */
6060
6061 static void
mri_assemble(char * str)6062 mri_assemble (char *str)
6063 {
6064 char *s;
6065
6066 /* md_assemble expects the opcode to be in lower case. */
6067 for (s = str; *s != ' ' && *s != '\0'; s++)
6068 *s = TOLOWER (*s);
6069
6070 md_assemble (str);
6071 }
6072
6073 /* Generate a new MRI label structured control directive label name. */
6074
6075 static char *
mri_control_label(void)6076 mri_control_label (void)
6077 {
6078 char *n;
6079
6080 n = XNEWVEC (char, 20);
6081 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6082 ++mri_control_index;
6083 return n;
6084 }
6085
6086 /* Create a new MRI structured control directive. */
6087
6088 static struct mri_control_info *
push_mri_control(enum mri_control_type type)6089 push_mri_control (enum mri_control_type type)
6090 {
6091 struct mri_control_info *n;
6092
6093 n = XNEW (struct mri_control_info);
6094
6095 n->type = type;
6096 n->else_seen = 0;
6097 if (type == mri_if || type == mri_while)
6098 n->top = NULL;
6099 else
6100 n->top = mri_control_label ();
6101 n->next = mri_control_label ();
6102 n->bottom = mri_control_label ();
6103
6104 n->outer = mri_control_stack;
6105 mri_control_stack = n;
6106
6107 return n;
6108 }
6109
6110 /* Pop off the stack of MRI structured control directives. */
6111
6112 static void
pop_mri_control(void)6113 pop_mri_control (void)
6114 {
6115 struct mri_control_info *n;
6116
6117 n = mri_control_stack;
6118 mri_control_stack = n->outer;
6119 free (n->top);
6120 free (n->next);
6121 free (n->bottom);
6122 free (n);
6123 }
6124
6125 /* Recognize a condition code in an MRI structured control expression. */
6126
6127 static int
parse_mri_condition(int * pcc)6128 parse_mri_condition (int *pcc)
6129 {
6130 char c1, c2;
6131
6132 know (*input_line_pointer == '<');
6133
6134 ++input_line_pointer;
6135 c1 = *input_line_pointer++;
6136 c2 = *input_line_pointer++;
6137
6138 if (*input_line_pointer != '>')
6139 {
6140 as_bad (_("syntax error in structured control directive"));
6141 return 0;
6142 }
6143
6144 ++input_line_pointer;
6145 SKIP_WHITESPACE ();
6146
6147 c1 = TOLOWER (c1);
6148 c2 = TOLOWER (c2);
6149
6150 *pcc = (c1 << 8) | c2;
6151
6152 return 1;
6153 }
6154
6155 /* Parse a single operand in an MRI structured control expression. */
6156
6157 static int
parse_mri_control_operand(int * pcc,char ** leftstart,char ** leftstop,char ** rightstart,char ** rightstop)6158 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6159 char **rightstart, char **rightstop)
6160 {
6161 char *s;
6162
6163 SKIP_WHITESPACE ();
6164
6165 *pcc = -1;
6166 *leftstart = NULL;
6167 *leftstop = NULL;
6168 *rightstart = NULL;
6169 *rightstop = NULL;
6170
6171 if (*input_line_pointer == '<')
6172 {
6173 /* It's just a condition code. */
6174 return parse_mri_condition (pcc);
6175 }
6176
6177 /* Look ahead for the condition code. */
6178 for (s = input_line_pointer; *s != '\0'; ++s)
6179 {
6180 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6181 break;
6182 }
6183 if (*s == '\0')
6184 {
6185 as_bad (_("missing condition code in structured control directive"));
6186 return 0;
6187 }
6188
6189 *leftstart = input_line_pointer;
6190 *leftstop = s;
6191 if (*leftstop > *leftstart
6192 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6193 --*leftstop;
6194
6195 input_line_pointer = s;
6196 if (! parse_mri_condition (pcc))
6197 return 0;
6198
6199 /* Look ahead for AND or OR or end of line. */
6200 for (s = input_line_pointer; *s != '\0'; ++s)
6201 {
6202 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6203 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6204 ^^^ ^^ */
6205 if ((s == input_line_pointer
6206 || *(s-1) == ' '
6207 || *(s-1) == '\t')
6208 && ((strncasecmp (s, "AND", 3) == 0
6209 && (s[3] == '.' || ! is_part_of_name (s[3])))
6210 || (strncasecmp (s, "OR", 2) == 0
6211 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6212 break;
6213 }
6214
6215 *rightstart = input_line_pointer;
6216 *rightstop = s;
6217 if (*rightstop > *rightstart
6218 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6219 --*rightstop;
6220
6221 input_line_pointer = s;
6222
6223 return 1;
6224 }
6225
6226 #define MCC(b1, b2) (((b1) << 8) | (b2))
6227
6228 /* Swap the sense of a condition. This changes the condition so that
6229 it generates the same result when the operands are swapped. */
6230
6231 static int
swap_mri_condition(int cc)6232 swap_mri_condition (int cc)
6233 {
6234 switch (cc)
6235 {
6236 case MCC ('h', 'i'): return MCC ('c', 's');
6237 case MCC ('l', 's'): return MCC ('c', 'c');
6238 /* <HS> is an alias for <CC>. */
6239 case MCC ('h', 's'):
6240 case MCC ('c', 'c'): return MCC ('l', 's');
6241 /* <LO> is an alias for <CS>. */
6242 case MCC ('l', 'o'):
6243 case MCC ('c', 's'): return MCC ('h', 'i');
6244 case MCC ('p', 'l'): return MCC ('m', 'i');
6245 case MCC ('m', 'i'): return MCC ('p', 'l');
6246 case MCC ('g', 'e'): return MCC ('l', 'e');
6247 case MCC ('l', 't'): return MCC ('g', 't');
6248 case MCC ('g', 't'): return MCC ('l', 't');
6249 case MCC ('l', 'e'): return MCC ('g', 'e');
6250 /* Issue a warning for conditions we can not swap. */
6251 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6252 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6253 case MCC ('v', 'c'):
6254 case MCC ('v', 's'):
6255 default :
6256 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6257 (char) (cc >> 8), (char) (cc));
6258 break;
6259 }
6260 return cc;
6261 }
6262
6263 /* Reverse the sense of a condition. */
6264
6265 static int
reverse_mri_condition(int cc)6266 reverse_mri_condition (int cc)
6267 {
6268 switch (cc)
6269 {
6270 case MCC ('h', 'i'): return MCC ('l', 's');
6271 case MCC ('l', 's'): return MCC ('h', 'i');
6272 /* <HS> is an alias for <CC> */
6273 case MCC ('h', 's'): return MCC ('l', 'o');
6274 case MCC ('c', 'c'): return MCC ('c', 's');
6275 /* <LO> is an alias for <CS> */
6276 case MCC ('l', 'o'): return MCC ('h', 's');
6277 case MCC ('c', 's'): return MCC ('c', 'c');
6278 case MCC ('n', 'e'): return MCC ('e', 'q');
6279 case MCC ('e', 'q'): return MCC ('n', 'e');
6280 case MCC ('v', 'c'): return MCC ('v', 's');
6281 case MCC ('v', 's'): return MCC ('v', 'c');
6282 case MCC ('p', 'l'): return MCC ('m', 'i');
6283 case MCC ('m', 'i'): return MCC ('p', 'l');
6284 case MCC ('g', 'e'): return MCC ('l', 't');
6285 case MCC ('l', 't'): return MCC ('g', 'e');
6286 case MCC ('g', 't'): return MCC ('l', 'e');
6287 case MCC ('l', 'e'): return MCC ('g', 't');
6288 }
6289 return cc;
6290 }
6291
6292 /* Build an MRI structured control expression. This generates test
6293 and branch instructions. It goes to TRUELAB if the condition is
6294 true, and to FALSELAB if the condition is false. Exactly one of
6295 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6296 is the size qualifier for the expression. EXTENT is the size to
6297 use for the branch. */
6298
6299 static void
build_mri_control_operand(int qual,int cc,char * leftstart,char * leftstop,char * rightstart,char * rightstop,const char * truelab,const char * falselab,int extent)6300 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6301 char *rightstart, char *rightstop,
6302 const char *truelab, const char *falselab,
6303 int extent)
6304 {
6305 char *buf;
6306 char *s;
6307
6308 if (leftstart != NULL)
6309 {
6310 struct m68k_op leftop, rightop;
6311 char c;
6312
6313 /* Swap the compare operands, if necessary, to produce a legal
6314 m68k compare instruction. Comparing a register operand with
6315 a non-register operand requires the register to be on the
6316 right (cmp, cmpa). Comparing an immediate value with
6317 anything requires the immediate value to be on the left
6318 (cmpi). */
6319
6320 c = *leftstop;
6321 *leftstop = '\0';
6322 (void) m68k_ip_op (leftstart, &leftop);
6323 *leftstop = c;
6324
6325 c = *rightstop;
6326 *rightstop = '\0';
6327 (void) m68k_ip_op (rightstart, &rightop);
6328 *rightstop = c;
6329
6330 if (rightop.mode == IMMED
6331 || ((leftop.mode == DREG || leftop.mode == AREG)
6332 && (rightop.mode != DREG && rightop.mode != AREG)))
6333 {
6334 char *temp;
6335
6336 /* Correct conditional handling:
6337 if #1 <lt> d0 then ;means if (1 < d0)
6338 ...
6339 endi
6340
6341 should assemble to:
6342
6343 cmp #1,d0 if we do *not* swap the operands
6344 bgt true we need the swapped condition!
6345 ble false
6346 true:
6347 ...
6348 false:
6349 */
6350 temp = leftstart;
6351 leftstart = rightstart;
6352 rightstart = temp;
6353 temp = leftstop;
6354 leftstop = rightstop;
6355 rightstop = temp;
6356 }
6357 else
6358 {
6359 cc = swap_mri_condition (cc);
6360 }
6361 }
6362
6363 if (truelab == NULL)
6364 {
6365 cc = reverse_mri_condition (cc);
6366 truelab = falselab;
6367 }
6368
6369 if (leftstart != NULL)
6370 {
6371 buf = XNEWVEC (char, (20
6372 + (leftstop - leftstart)
6373 + (rightstop - rightstart)));
6374 s = buf;
6375 *s++ = 'c';
6376 *s++ = 'm';
6377 *s++ = 'p';
6378 if (qual != '\0')
6379 *s++ = TOLOWER (qual);
6380 *s++ = ' ';
6381 memcpy (s, leftstart, leftstop - leftstart);
6382 s += leftstop - leftstart;
6383 *s++ = ',';
6384 memcpy (s, rightstart, rightstop - rightstart);
6385 s += rightstop - rightstart;
6386 *s = '\0';
6387 mri_assemble (buf);
6388 free (buf);
6389 }
6390
6391 buf = XNEWVEC (char, 20 + strlen (truelab));
6392 s = buf;
6393 *s++ = 'b';
6394 *s++ = cc >> 8;
6395 *s++ = cc & 0xff;
6396 if (extent != '\0')
6397 *s++ = TOLOWER (extent);
6398 *s++ = ' ';
6399 strcpy (s, truelab);
6400 mri_assemble (buf);
6401 free (buf);
6402 }
6403
6404 /* Parse an MRI structured control expression. This generates test
6405 and branch instructions. STOP is where the expression ends. It
6406 goes to TRUELAB if the condition is true, and to FALSELAB if the
6407 condition is false. Exactly one of TRUELAB and FALSELAB will be
6408 NULL, meaning to fall through. QUAL is the size qualifier for the
6409 expression. EXTENT is the size to use for the branch. */
6410
6411 static void
parse_mri_control_expression(char * stop,int qual,const char * truelab,const char * falselab,int extent)6412 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6413 const char *falselab, int extent)
6414 {
6415 int c;
6416 int cc;
6417 char *leftstart;
6418 char *leftstop;
6419 char *rightstart;
6420 char *rightstop;
6421
6422 c = *stop;
6423 *stop = '\0';
6424
6425 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6426 &rightstart, &rightstop))
6427 {
6428 *stop = c;
6429 return;
6430 }
6431
6432 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6433 {
6434 const char *flab;
6435
6436 if (falselab != NULL)
6437 flab = falselab;
6438 else
6439 flab = mri_control_label ();
6440
6441 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6442 rightstop, (const char *) NULL, flab, extent);
6443
6444 input_line_pointer += 3;
6445 if (*input_line_pointer != '.'
6446 || input_line_pointer[1] == '\0')
6447 qual = '\0';
6448 else
6449 {
6450 qual = input_line_pointer[1];
6451 input_line_pointer += 2;
6452 }
6453
6454 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6455 &rightstart, &rightstop))
6456 {
6457 *stop = c;
6458 return;
6459 }
6460
6461 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6462 rightstop, truelab, falselab, extent);
6463
6464 if (falselab == NULL)
6465 colon (flab);
6466 }
6467 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6468 {
6469 const char *tlab;
6470
6471 if (truelab != NULL)
6472 tlab = truelab;
6473 else
6474 tlab = mri_control_label ();
6475
6476 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6477 rightstop, tlab, (const char *) NULL, extent);
6478
6479 input_line_pointer += 2;
6480 if (*input_line_pointer != '.'
6481 || input_line_pointer[1] == '\0')
6482 qual = '\0';
6483 else
6484 {
6485 qual = input_line_pointer[1];
6486 input_line_pointer += 2;
6487 }
6488
6489 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6490 &rightstart, &rightstop))
6491 {
6492 *stop = c;
6493 return;
6494 }
6495
6496 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6497 rightstop, truelab, falselab, extent);
6498
6499 if (truelab == NULL)
6500 colon (tlab);
6501 }
6502 else
6503 {
6504 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6505 rightstop, truelab, falselab, extent);
6506 }
6507
6508 *stop = c;
6509 if (input_line_pointer != stop)
6510 as_bad (_("syntax error in structured control directive"));
6511 }
6512
6513 /* Handle the MRI IF pseudo-op. This may be a structured control
6514 directive, or it may be a regular assembler conditional, depending
6515 on its operands. */
6516
6517 static void
s_mri_if(int qual)6518 s_mri_if (int qual)
6519 {
6520 char *s;
6521 int c;
6522 struct mri_control_info *n;
6523
6524 /* A structured control directive must end with THEN with an
6525 optional qualifier. */
6526 s = input_line_pointer;
6527 /* We only accept '*' as introduction of comments if preceded by white space
6528 or at first column of a line (I think this can't actually happen here?)
6529 This is important when assembling:
6530 if d0 <ne> 12(a0,d0*2) then
6531 if d0 <ne> #CONST*20 then. */
6532 while (! (is_end_of_line[(unsigned char) *s]
6533 || (flag_mri
6534 && *s == '*'
6535 && (s == input_line_pointer
6536 || *(s-1) == ' '
6537 || *(s-1) == '\t'))))
6538 ++s;
6539 --s;
6540 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6541 --s;
6542
6543 if (s - input_line_pointer > 1
6544 && s[-1] == '.')
6545 s -= 2;
6546
6547 if (s - input_line_pointer < 3
6548 || strncasecmp (s - 3, "THEN", 4) != 0)
6549 {
6550 if (qual != '\0')
6551 {
6552 as_bad (_("missing then"));
6553 ignore_rest_of_line ();
6554 return;
6555 }
6556
6557 /* It's a conditional. */
6558 s_if (O_ne);
6559 return;
6560 }
6561
6562 /* Since this might be a conditional if, this pseudo-op will be
6563 called even if we are supported to be ignoring input. Double
6564 check now. Clobber *input_line_pointer so that ignore_input
6565 thinks that this is not a special pseudo-op. */
6566 c = *input_line_pointer;
6567 *input_line_pointer = 0;
6568 if (ignore_input ())
6569 {
6570 *input_line_pointer = c;
6571 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6572 ++input_line_pointer;
6573 demand_empty_rest_of_line ();
6574 return;
6575 }
6576 *input_line_pointer = c;
6577
6578 n = push_mri_control (mri_if);
6579
6580 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6581 n->next, s[1] == '.' ? s[2] : '\0');
6582
6583 if (s[1] == '.')
6584 input_line_pointer = s + 3;
6585 else
6586 input_line_pointer = s + 1;
6587
6588 if (flag_mri)
6589 {
6590 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6591 ++input_line_pointer;
6592 }
6593
6594 demand_empty_rest_of_line ();
6595 }
6596
6597 /* Handle the MRI else pseudo-op. If we are currently doing an MRI
6598 structured IF, associate the ELSE with the IF. Otherwise, assume
6599 it is a conditional else. */
6600
6601 static void
s_mri_else(int qual)6602 s_mri_else (int qual)
6603 {
6604 int c;
6605 char *buf;
6606 char q[2];
6607
6608 if (qual == '\0'
6609 && (mri_control_stack == NULL
6610 || mri_control_stack->type != mri_if
6611 || mri_control_stack->else_seen))
6612 {
6613 s_else (0);
6614 return;
6615 }
6616
6617 c = *input_line_pointer;
6618 *input_line_pointer = 0;
6619 if (ignore_input ())
6620 {
6621 *input_line_pointer = c;
6622 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6623 ++input_line_pointer;
6624 demand_empty_rest_of_line ();
6625 return;
6626 }
6627 *input_line_pointer = c;
6628
6629 if (mri_control_stack == NULL
6630 || mri_control_stack->type != mri_if
6631 || mri_control_stack->else_seen)
6632 {
6633 as_bad (_("else without matching if"));
6634 ignore_rest_of_line ();
6635 return;
6636 }
6637
6638 mri_control_stack->else_seen = 1;
6639
6640 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
6641 q[0] = TOLOWER (qual);
6642 q[1] = '\0';
6643 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6644 mri_assemble (buf);
6645 free (buf);
6646
6647 colon (mri_control_stack->next);
6648
6649 if (flag_mri)
6650 {
6651 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6652 ++input_line_pointer;
6653 }
6654
6655 demand_empty_rest_of_line ();
6656 }
6657
6658 /* Handle the MRI ENDI pseudo-op. */
6659
6660 static void
s_mri_endi(int ignore ATTRIBUTE_UNUSED)6661 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6662 {
6663 if (mri_control_stack == NULL
6664 || mri_control_stack->type != mri_if)
6665 {
6666 as_bad (_("endi without matching if"));
6667 ignore_rest_of_line ();
6668 return;
6669 }
6670
6671 /* ignore_input will not return true for ENDI, so we don't need to
6672 worry about checking it again here. */
6673
6674 if (! mri_control_stack->else_seen)
6675 colon (mri_control_stack->next);
6676 colon (mri_control_stack->bottom);
6677
6678 pop_mri_control ();
6679
6680 if (flag_mri)
6681 {
6682 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6683 ++input_line_pointer;
6684 }
6685
6686 demand_empty_rest_of_line ();
6687 }
6688
6689 /* Handle the MRI BREAK pseudo-op. */
6690
6691 static void
s_mri_break(int extent)6692 s_mri_break (int extent)
6693 {
6694 struct mri_control_info *n;
6695 char *buf;
6696 char ex[2];
6697
6698 n = mri_control_stack;
6699 while (n != NULL
6700 && n->type != mri_for
6701 && n->type != mri_repeat
6702 && n->type != mri_while)
6703 n = n->outer;
6704 if (n == NULL)
6705 {
6706 as_bad (_("break outside of structured loop"));
6707 ignore_rest_of_line ();
6708 return;
6709 }
6710
6711 buf = XNEWVEC (char, 20 + strlen (n->bottom));
6712 ex[0] = TOLOWER (extent);
6713 ex[1] = '\0';
6714 sprintf (buf, "bra%s %s", ex, n->bottom);
6715 mri_assemble (buf);
6716 free (buf);
6717
6718 if (flag_mri)
6719 {
6720 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6721 ++input_line_pointer;
6722 }
6723
6724 demand_empty_rest_of_line ();
6725 }
6726
6727 /* Handle the MRI NEXT pseudo-op. */
6728
6729 static void
s_mri_next(int extent)6730 s_mri_next (int extent)
6731 {
6732 struct mri_control_info *n;
6733 char *buf;
6734 char ex[2];
6735
6736 n = mri_control_stack;
6737 while (n != NULL
6738 && n->type != mri_for
6739 && n->type != mri_repeat
6740 && n->type != mri_while)
6741 n = n->outer;
6742 if (n == NULL)
6743 {
6744 as_bad (_("next outside of structured loop"));
6745 ignore_rest_of_line ();
6746 return;
6747 }
6748
6749 buf = XNEWVEC (char, 20 + strlen (n->next));
6750 ex[0] = TOLOWER (extent);
6751 ex[1] = '\0';
6752 sprintf (buf, "bra%s %s", ex, n->next);
6753 mri_assemble (buf);
6754 free (buf);
6755
6756 if (flag_mri)
6757 {
6758 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6759 ++input_line_pointer;
6760 }
6761
6762 demand_empty_rest_of_line ();
6763 }
6764
6765 /* Handle the MRI FOR pseudo-op. */
6766
6767 static void
s_mri_for(int qual)6768 s_mri_for (int qual)
6769 {
6770 const char *varstart, *varstop;
6771 const char *initstart, *initstop;
6772 const char *endstart, *endstop;
6773 const char *bystart, *bystop;
6774 int up;
6775 int by;
6776 int extent;
6777 struct mri_control_info *n;
6778 char *buf;
6779 char *s;
6780 char ex[2];
6781
6782 /* The syntax is
6783 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6784 */
6785
6786 SKIP_WHITESPACE ();
6787 varstart = input_line_pointer;
6788
6789 /* Look for the '='. */
6790 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6791 && *input_line_pointer != '=')
6792 ++input_line_pointer;
6793 if (*input_line_pointer != '=')
6794 {
6795 as_bad (_("missing ="));
6796 ignore_rest_of_line ();
6797 return;
6798 }
6799
6800 varstop = input_line_pointer;
6801 if (varstop > varstart
6802 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6803 --varstop;
6804
6805 ++input_line_pointer;
6806
6807 initstart = input_line_pointer;
6808
6809 /* Look for TO or DOWNTO. */
6810 up = 1;
6811 initstop = NULL;
6812 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6813 {
6814 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6815 && ! is_part_of_name (input_line_pointer[2]))
6816 {
6817 initstop = input_line_pointer;
6818 input_line_pointer += 2;
6819 break;
6820 }
6821 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6822 && ! is_part_of_name (input_line_pointer[6]))
6823 {
6824 initstop = input_line_pointer;
6825 up = 0;
6826 input_line_pointer += 6;
6827 break;
6828 }
6829 ++input_line_pointer;
6830 }
6831 if (initstop == NULL)
6832 {
6833 as_bad (_("missing to or downto"));
6834 ignore_rest_of_line ();
6835 return;
6836 }
6837 if (initstop > initstart
6838 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6839 --initstop;
6840
6841 SKIP_WHITESPACE ();
6842 endstart = input_line_pointer;
6843
6844 /* Look for BY or DO. */
6845 by = 0;
6846 endstop = NULL;
6847 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6848 {
6849 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6850 && ! is_part_of_name (input_line_pointer[2]))
6851 {
6852 endstop = input_line_pointer;
6853 by = 1;
6854 input_line_pointer += 2;
6855 break;
6856 }
6857 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6858 && (input_line_pointer[2] == '.'
6859 || ! is_part_of_name (input_line_pointer[2])))
6860 {
6861 endstop = input_line_pointer;
6862 input_line_pointer += 2;
6863 break;
6864 }
6865 ++input_line_pointer;
6866 }
6867 if (endstop == NULL)
6868 {
6869 as_bad (_("missing do"));
6870 ignore_rest_of_line ();
6871 return;
6872 }
6873 if (endstop > endstart
6874 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6875 --endstop;
6876
6877 if (! by)
6878 {
6879 bystart = "#1";
6880 bystop = bystart + 2;
6881 }
6882 else
6883 {
6884 SKIP_WHITESPACE ();
6885 bystart = input_line_pointer;
6886
6887 /* Look for DO. */
6888 bystop = NULL;
6889 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6890 {
6891 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6892 && (input_line_pointer[2] == '.'
6893 || ! is_part_of_name (input_line_pointer[2])))
6894 {
6895 bystop = input_line_pointer;
6896 input_line_pointer += 2;
6897 break;
6898 }
6899 ++input_line_pointer;
6900 }
6901 if (bystop == NULL)
6902 {
6903 as_bad (_("missing do"));
6904 ignore_rest_of_line ();
6905 return;
6906 }
6907 if (bystop > bystart
6908 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6909 --bystop;
6910 }
6911
6912 if (*input_line_pointer != '.')
6913 extent = '\0';
6914 else
6915 {
6916 extent = input_line_pointer[1];
6917 input_line_pointer += 2;
6918 }
6919
6920 /* We have fully parsed the FOR operands. Now build the loop. */
6921 n = push_mri_control (mri_for);
6922
6923 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
6924
6925 /* Move init,var. */
6926 s = buf;
6927 *s++ = 'm';
6928 *s++ = 'o';
6929 *s++ = 'v';
6930 *s++ = 'e';
6931 if (qual != '\0')
6932 *s++ = TOLOWER (qual);
6933 *s++ = ' ';
6934 memcpy (s, initstart, initstop - initstart);
6935 s += initstop - initstart;
6936 *s++ = ',';
6937 memcpy (s, varstart, varstop - varstart);
6938 s += varstop - varstart;
6939 *s = '\0';
6940 mri_assemble (buf);
6941
6942 colon (n->top);
6943
6944 /* cmp end,var. */
6945 s = buf;
6946 *s++ = 'c';
6947 *s++ = 'm';
6948 *s++ = 'p';
6949 if (qual != '\0')
6950 *s++ = TOLOWER (qual);
6951 *s++ = ' ';
6952 memcpy (s, endstart, endstop - endstart);
6953 s += endstop - endstart;
6954 *s++ = ',';
6955 memcpy (s, varstart, varstop - varstart);
6956 s += varstop - varstart;
6957 *s = '\0';
6958 mri_assemble (buf);
6959
6960 /* bcc bottom. */
6961 ex[0] = TOLOWER (extent);
6962 ex[1] = '\0';
6963 if (up)
6964 sprintf (buf, "blt%s %s", ex, n->bottom);
6965 else
6966 sprintf (buf, "bgt%s %s", ex, n->bottom);
6967 mri_assemble (buf);
6968
6969 /* Put together the add or sub instruction used by ENDF. */
6970 s = buf;
6971 if (up)
6972 strcpy (s, "add");
6973 else
6974 strcpy (s, "sub");
6975 s += 3;
6976 if (qual != '\0')
6977 *s++ = TOLOWER (qual);
6978 *s++ = ' ';
6979 memcpy (s, bystart, bystop - bystart);
6980 s += bystop - bystart;
6981 *s++ = ',';
6982 memcpy (s, varstart, varstop - varstart);
6983 s += varstop - varstart;
6984 *s = '\0';
6985 n->incr = buf;
6986
6987 if (flag_mri)
6988 {
6989 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6990 ++input_line_pointer;
6991 }
6992
6993 demand_empty_rest_of_line ();
6994 }
6995
6996 /* Handle the MRI ENDF pseudo-op. */
6997
6998 static void
s_mri_endf(int ignore ATTRIBUTE_UNUSED)6999 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7000 {
7001 if (mri_control_stack == NULL
7002 || mri_control_stack->type != mri_for)
7003 {
7004 as_bad (_("endf without for"));
7005 ignore_rest_of_line ();
7006 return;
7007 }
7008
7009 colon (mri_control_stack->next);
7010
7011 mri_assemble (mri_control_stack->incr);
7012
7013 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7014 mri_assemble (mri_control_stack->incr);
7015
7016 free (mri_control_stack->incr);
7017
7018 colon (mri_control_stack->bottom);
7019
7020 pop_mri_control ();
7021
7022 if (flag_mri)
7023 {
7024 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7025 ++input_line_pointer;
7026 }
7027
7028 demand_empty_rest_of_line ();
7029 }
7030
7031 /* Handle the MRI REPEAT pseudo-op. */
7032
7033 static void
s_mri_repeat(int ignore ATTRIBUTE_UNUSED)7034 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7035 {
7036 struct mri_control_info *n;
7037
7038 n = push_mri_control (mri_repeat);
7039 colon (n->top);
7040 if (flag_mri)
7041 {
7042 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7043 ++input_line_pointer;
7044 }
7045 demand_empty_rest_of_line ();
7046 }
7047
7048 /* Handle the MRI UNTIL pseudo-op. */
7049
7050 static void
s_mri_until(int qual)7051 s_mri_until (int qual)
7052 {
7053 char *s;
7054
7055 if (mri_control_stack == NULL
7056 || mri_control_stack->type != mri_repeat)
7057 {
7058 as_bad (_("until without repeat"));
7059 ignore_rest_of_line ();
7060 return;
7061 }
7062
7063 colon (mri_control_stack->next);
7064
7065 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7066 ;
7067
7068 parse_mri_control_expression (s, qual, (const char *) NULL,
7069 mri_control_stack->top, '\0');
7070
7071 colon (mri_control_stack->bottom);
7072
7073 input_line_pointer = s;
7074
7075 pop_mri_control ();
7076
7077 if (flag_mri)
7078 {
7079 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7080 ++input_line_pointer;
7081 }
7082
7083 demand_empty_rest_of_line ();
7084 }
7085
7086 /* Handle the MRI WHILE pseudo-op. */
7087
7088 static void
s_mri_while(int qual)7089 s_mri_while (int qual)
7090 {
7091 char *s;
7092
7093 struct mri_control_info *n;
7094
7095 s = input_line_pointer;
7096 /* We only accept '*' as introduction of comments if preceded by white space
7097 or at first column of a line (I think this can't actually happen here?)
7098 This is important when assembling:
7099 while d0 <ne> 12(a0,d0*2) do
7100 while d0 <ne> #CONST*20 do. */
7101 while (! (is_end_of_line[(unsigned char) *s]
7102 || (flag_mri
7103 && *s == '*'
7104 && (s == input_line_pointer
7105 || *(s-1) == ' '
7106 || *(s-1) == '\t'))))
7107 s++;
7108 --s;
7109 while (*s == ' ' || *s == '\t')
7110 --s;
7111 if (s - input_line_pointer > 1
7112 && s[-1] == '.')
7113 s -= 2;
7114 if (s - input_line_pointer < 2
7115 || strncasecmp (s - 1, "DO", 2) != 0)
7116 {
7117 as_bad (_("missing do"));
7118 ignore_rest_of_line ();
7119 return;
7120 }
7121
7122 n = push_mri_control (mri_while);
7123
7124 colon (n->next);
7125
7126 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7127 s[1] == '.' ? s[2] : '\0');
7128
7129 input_line_pointer = s + 1;
7130 if (*input_line_pointer == '.')
7131 input_line_pointer += 2;
7132
7133 if (flag_mri)
7134 {
7135 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7136 ++input_line_pointer;
7137 }
7138
7139 demand_empty_rest_of_line ();
7140 }
7141
7142 /* Handle the MRI ENDW pseudo-op. */
7143
7144 static void
s_mri_endw(int ignore ATTRIBUTE_UNUSED)7145 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7146 {
7147 char *buf;
7148
7149 if (mri_control_stack == NULL
7150 || mri_control_stack->type != mri_while)
7151 {
7152 as_bad (_("endw without while"));
7153 ignore_rest_of_line ();
7154 return;
7155 }
7156
7157 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
7158 sprintf (buf, "bra %s", mri_control_stack->next);
7159 mri_assemble (buf);
7160 free (buf);
7161
7162 colon (mri_control_stack->bottom);
7163
7164 pop_mri_control ();
7165
7166 if (flag_mri)
7167 {
7168 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7169 ++input_line_pointer;
7170 }
7171
7172 demand_empty_rest_of_line ();
7173 }
7174
7175 /* Parse a .cpu directive. */
7176
7177 static void
s_m68k_cpu(int ignored ATTRIBUTE_UNUSED)7178 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7179 {
7180 char saved_char;
7181 char *name;
7182
7183 if (initialized)
7184 {
7185 as_bad (_("already assembled instructions"));
7186 ignore_rest_of_line ();
7187 return;
7188 }
7189
7190 name = input_line_pointer;
7191 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7192 input_line_pointer++;
7193 saved_char = *input_line_pointer;
7194 *input_line_pointer = 0;
7195
7196 m68k_set_cpu (name, 1, 0);
7197
7198 *input_line_pointer = saved_char;
7199 demand_empty_rest_of_line ();
7200 return;
7201 }
7202
7203 /* Parse a .arch directive. */
7204
7205 static void
s_m68k_arch(int ignored ATTRIBUTE_UNUSED)7206 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7207 {
7208 char saved_char;
7209 char *name;
7210
7211 if (initialized)
7212 {
7213 as_bad (_("already assembled instructions"));
7214 ignore_rest_of_line ();
7215 return;
7216 }
7217
7218 name = input_line_pointer;
7219 while (*input_line_pointer && *input_line_pointer != ','
7220 && !ISSPACE (*input_line_pointer))
7221 input_line_pointer++;
7222 saved_char = *input_line_pointer;
7223 *input_line_pointer = 0;
7224
7225 if (m68k_set_arch (name, 1, 0))
7226 {
7227 /* Scan extensions. */
7228 do
7229 {
7230 *input_line_pointer++ = saved_char;
7231 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7232 break;
7233 name = input_line_pointer;
7234 while (*input_line_pointer && *input_line_pointer != ','
7235 && !ISSPACE (*input_line_pointer))
7236 input_line_pointer++;
7237 saved_char = *input_line_pointer;
7238 *input_line_pointer = 0;
7239 }
7240 while (m68k_set_extension (name, 1, 0));
7241 }
7242
7243 *input_line_pointer = saved_char;
7244 demand_empty_rest_of_line ();
7245 return;
7246 }
7247
7248 /* Lookup a cpu name in TABLE and return the slot found. Return NULL
7249 if none is found, the caller is responsible for emitting an error
7250 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7251 cpu name, if it begins with a '6' (possibly skipping an intervening
7252 'c'. We also allow a 'c' in the same place. if NEGATED is
7253 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7254 the option is indeed negated. */
7255
7256 static const struct m68k_cpu *
m68k_lookup_cpu(const char * arg,const struct m68k_cpu * table,int allow_m,int * negated)7257 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7258 int allow_m, int *negated)
7259 {
7260 /* allow negated value? */
7261 if (negated)
7262 {
7263 *negated = 0;
7264
7265 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7266 {
7267 arg += 3;
7268 *negated = 1;
7269 }
7270 }
7271
7272 /* Remove 'm' or 'mc' prefix from 68k variants. */
7273 if (allow_m)
7274 {
7275 if (arg[0] == 'm')
7276 {
7277 if (arg[1] == '6' || arg[1] == '5')
7278 arg += 1;
7279 else if (arg[1] == 'c' && arg[2] == '6')
7280 arg += 2;
7281 }
7282 }
7283 else if (arg[0] == 'c' && arg[1] == '6')
7284 arg += 1;
7285
7286 for (; table->name; table++)
7287 if (!strcmp (arg, table->name))
7288 {
7289 if (table->alias < -1 || table->alias > 1)
7290 as_bad (_("`%s' is deprecated, use `%s'"),
7291 table->name, table[table->alias < 0 ? 1 : -1].name);
7292 return table;
7293 }
7294 return 0;
7295 }
7296
7297 /* Set the cpu, issuing errors if it is unrecognized. */
7298
7299 static int
m68k_set_cpu(char const * name,int allow_m,int silent)7300 m68k_set_cpu (char const *name, int allow_m, int silent)
7301 {
7302 const struct m68k_cpu *cpu;
7303
7304 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7305
7306 if (!cpu)
7307 {
7308 if (!silent)
7309 as_bad (_("cpu `%s' unrecognized"), name);
7310 return 0;
7311 }
7312 selected_cpu = cpu;
7313 return 1;
7314 }
7315
7316 /* Set the architecture, issuing errors if it is unrecognized. */
7317
7318 static int
m68k_set_arch(char const * name,int allow_m,int silent)7319 m68k_set_arch (char const *name, int allow_m, int silent)
7320 {
7321 const struct m68k_cpu *arch;
7322
7323 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7324
7325 if (!arch)
7326 {
7327 if (!silent)
7328 as_bad (_("architecture `%s' unrecognized"), name);
7329 return 0;
7330 }
7331 selected_arch = arch;
7332 return 1;
7333 }
7334
7335 /* Set the architecture extension, issuing errors if it is
7336 unrecognized, or invalid */
7337
7338 static int
m68k_set_extension(char const * name,int allow_m,int silent)7339 m68k_set_extension (char const *name, int allow_m, int silent)
7340 {
7341 int negated;
7342 const struct m68k_cpu *ext;
7343
7344 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7345
7346 if (!ext)
7347 {
7348 if (!silent)
7349 as_bad (_("extension `%s' unrecognized"), name);
7350 return 0;
7351 }
7352
7353 if (negated)
7354 not_current_architecture |= (ext->control_regs
7355 ? *(unsigned *)ext->control_regs: ext->arch);
7356 else
7357 current_architecture |= ext->arch;
7358 return 1;
7359 }
7360
7361 /* md_parse_option
7362 Invocation line includes a switch not recognized by the base assembler.
7363 */
7364
7365 const char *md_shortopts = "lSA:m:kQ:V";
7366
7367 struct option md_longopts[] = {
7368 #define OPTION_PIC (OPTION_MD_BASE)
7369 {"pic", no_argument, NULL, OPTION_PIC},
7370 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7371 {"register-prefix-optional", no_argument, NULL,
7372 OPTION_REGISTER_PREFIX_OPTIONAL},
7373 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7374 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7375 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7376 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7377 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7378 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7379 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7380 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7381 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7382 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7383 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7384 {"pcrel", no_argument, NULL, OPTION_PCREL},
7385 {NULL, no_argument, NULL, 0}
7386 };
7387 size_t md_longopts_size = sizeof (md_longopts);
7388
7389 int
md_parse_option(int c,const char * arg)7390 md_parse_option (int c, const char *arg)
7391 {
7392 switch (c)
7393 {
7394 case 'l': /* -l means keep external to 2 bit offset
7395 rather than 16 bit one. */
7396 flag_short_refs = 1;
7397 break;
7398
7399 case 'S': /* -S means that jbsr's always turn into
7400 jsr's. */
7401 flag_long_jumps = 1;
7402 break;
7403
7404 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7405 branches into absolute jumps. */
7406 flag_keep_pcrel = 1;
7407 break;
7408
7409 case OPTION_PIC:
7410 case 'k':
7411 flag_want_pic = 1;
7412 break; /* -pic, Position Independent Code. */
7413
7414 case OPTION_REGISTER_PREFIX_OPTIONAL:
7415 flag_reg_prefix_optional = 1;
7416 reg_prefix_optional_seen = 1;
7417 break;
7418
7419 /* -V: SVR4 argument to print version ID. */
7420 case 'V':
7421 print_version_id ();
7422 break;
7423
7424 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7425 should be emitted or not. FIXME: Not implemented. */
7426 case 'Q':
7427 break;
7428
7429 case OPTION_BITWISE_OR:
7430 {
7431 char *n, *t;
7432 const char *s;
7433
7434 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
7435 t = n;
7436 for (s = m68k_comment_chars; *s != '\0'; s++)
7437 if (*s != '|')
7438 *t++ = *s;
7439 *t = '\0';
7440 m68k_comment_chars = n;
7441 }
7442 break;
7443
7444 case OPTION_BASE_SIZE_DEFAULT_16:
7445 m68k_index_width_default = SIZE_WORD;
7446 break;
7447
7448 case OPTION_BASE_SIZE_DEFAULT_32:
7449 m68k_index_width_default = SIZE_LONG;
7450 break;
7451
7452 case OPTION_DISP_SIZE_DEFAULT_16:
7453 m68k_rel32 = 0;
7454 m68k_rel32_from_cmdline = 1;
7455 break;
7456
7457 case OPTION_DISP_SIZE_DEFAULT_32:
7458 m68k_rel32 = 1;
7459 m68k_rel32_from_cmdline = 1;
7460 break;
7461
7462 case 'A':
7463 #if WARN_DEPRECATED
7464 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7465 arg, arg));
7466 #endif
7467 /* Intentional fall-through. */
7468 case 'm':
7469 if (startswith (arg, "arch="))
7470 m68k_set_arch (arg + 5, 1, 0);
7471 else if (startswith (arg, "cpu="))
7472 m68k_set_cpu (arg + 4, 1, 0);
7473 else if (m68k_set_extension (arg, 0, 1))
7474 ;
7475 else if (m68k_set_arch (arg, 0, 1))
7476 ;
7477 else if (m68k_set_cpu (arg, 0, 1))
7478 ;
7479 else if (startswith (arg, "lcfix"))
7480 lcfix = true;
7481 else
7482 return 0;
7483 break;
7484
7485 default:
7486 return 0;
7487 }
7488
7489 return 1;
7490 }
7491
7492 /* Setup tables from the selected arch and/or cpu */
7493
7494 static void
m68k_init_arch(void)7495 m68k_init_arch (void)
7496 {
7497 if (not_current_architecture & current_architecture)
7498 {
7499 as_bad (_("architecture features both enabled and disabled"));
7500 not_current_architecture &= ~current_architecture;
7501 }
7502 if (selected_arch)
7503 {
7504 current_architecture |= selected_arch->arch;
7505 control_regs = selected_arch->control_regs;
7506 }
7507 else
7508 current_architecture |= selected_cpu->arch;
7509
7510 current_architecture &= ~not_current_architecture;
7511
7512 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7513 {
7514 /* Determine which float is really meant. */
7515 if (current_architecture & (m68k_mask & ~m68881))
7516 current_architecture ^= cfloat;
7517 else
7518 current_architecture ^= m68881;
7519 }
7520
7521 if (selected_cpu)
7522 {
7523 control_regs = selected_cpu->control_regs;
7524 if (current_architecture & ~selected_cpu->arch)
7525 {
7526 as_bad (_("selected processor does not have all features of selected architecture"));
7527 current_architecture
7528 = selected_cpu->arch & ~not_current_architecture;
7529 }
7530 }
7531
7532 if ((current_architecture & m68k_mask)
7533 && (current_architecture & ~m68k_mask))
7534 {
7535 as_bad (_ ("m68k and cf features both selected"));
7536 if (current_architecture & m68k_mask)
7537 current_architecture &= m68k_mask;
7538 else
7539 current_architecture &= ~m68k_mask;
7540 }
7541
7542 /* Permit m68881 specification with all cpus; those that can't work
7543 with a coprocessor could be doing emulation. */
7544 if (current_architecture & m68851)
7545 {
7546 if (current_architecture & m68040)
7547 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7548 }
7549 /* What other incompatibilities could we check for? */
7550
7551 if (cpu_of_arch (current_architecture) < m68020
7552 || arch_coldfire_p (current_architecture))
7553 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7554
7555 initialized = 1;
7556 }
7557
7558 void
md_show_usage(FILE * stream)7559 md_show_usage (FILE *stream)
7560 {
7561 const char *default_cpu = TARGET_CPU;
7562 int i;
7563
7564 /* Get the canonical name for the default target CPU. */
7565 if (*default_cpu == 'm')
7566 default_cpu++;
7567 for (i = 0; m68k_cpus[i].name; i++)
7568 {
7569 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7570 {
7571 while (m68k_cpus[i].alias > 0)
7572 i--;
7573 while (m68k_cpus[i].alias < 0)
7574 i++;
7575 default_cpu = m68k_cpus[i].name;
7576 }
7577 }
7578
7579 fprintf (stream, _("\
7580 -march=<arch> set architecture\n\
7581 -mcpu=<cpu> set cpu [default %s]\n\
7582 -mlcfix compatability with lc040 nop before f-line\n\
7583 "), default_cpu);
7584 for (i = 0; m68k_extensions[i].name; i++)
7585 fprintf (stream, _("\
7586 -m[no-]%-16s enable/disable %s architecture extension\n\
7587 "), m68k_extensions[i].name,
7588 m68k_extensions[i].alias > 0 ? " ColdFire"
7589 : m68k_extensions[i].alias < 0 ? " m68k" : "");
7590
7591 fprintf (stream, _("\
7592 -l use 1 word for refs to undefined symbols [default 2]\n\
7593 -pic, -k generate position independent code\n\
7594 -S turn jbsr into jsr\n\
7595 --pcrel never turn PC-relative branches into absolute jumps\n\
7596 --register-prefix-optional\n\
7597 recognize register names without prefix character\n\
7598 --bitwise-or do not treat `|' as a comment character\n\
7599 --base-size-default-16 base reg without size is 16 bits\n\
7600 --base-size-default-32 base reg without size is 32 bits (default)\n\
7601 --disp-size-default-16 displacement with unknown size is 16 bits\n\
7602 --disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7603 "));
7604
7605 fprintf (stream, _("Architecture variants are: "));
7606 for (i = 0; m68k_archs[i].name; i++)
7607 {
7608 if (i)
7609 fprintf (stream, " | ");
7610 fprintf (stream, "%s", m68k_archs[i].name);
7611 }
7612 fprintf (stream, "\n");
7613
7614 fprintf (stream, _("Processor variants are: "));
7615 for (i = 0; m68k_cpus[i].name; i++)
7616 {
7617 if (i)
7618 fprintf (stream, " | ");
7619 fprintf (stream, "%s", m68k_cpus[i].name);
7620 }
7621 fprintf (stream, _("\n"));
7622 }
7623
7624 #ifdef TEST2
7625
7626 /* TEST2: Test md_assemble() */
7627 /* Warning, this routine probably doesn't work anymore. */
7628 int
main(void)7629 main (void)
7630 {
7631 struct m68k_it the_ins;
7632 char buf[120];
7633 char *cp;
7634 int n;
7635
7636 m68k_ip_begin ();
7637 for (;;)
7638 {
7639 if (!gets (buf) || !*buf)
7640 break;
7641 if (buf[0] == '|' || buf[1] == '.')
7642 continue;
7643 for (cp = buf; *cp; cp++)
7644 if (*cp == '\t')
7645 *cp = ' ';
7646 if (is_label (buf))
7647 continue;
7648 memset (&the_ins, '\0', sizeof (the_ins));
7649 m68k_ip (&the_ins, buf);
7650 if (the_ins.error)
7651 {
7652 printf (_("Error %s in %s\n"), the_ins.error, buf);
7653 }
7654 else
7655 {
7656 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7657 for (n = 0; n < the_ins.numo; n++)
7658 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7659 printf (" ");
7660 print_the_insn (&the_ins.opcode[0], stdout);
7661 (void) putchar ('\n');
7662 }
7663 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7664 {
7665 if (the_ins.operands[n].error)
7666 {
7667 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7668 continue;
7669 }
7670 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7671 the_ins.operands[n].reg);
7672 if (the_ins.operands[n].b_const)
7673 printf ("Constant: '%.*s', ",
7674 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7675 the_ins.operands[n].b_const);
7676 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7677 the_ins.operands[n].isiz, the_ins.operands[n].imul);
7678 if (the_ins.operands[n].b_iadd)
7679 printf ("Iadd: '%.*s',",
7680 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7681 the_ins.operands[n].b_iadd);
7682 putchar ('\n');
7683 }
7684 }
7685 m68k_ip_end ();
7686 return 0;
7687 }
7688
7689 int
is_label(char * str)7690 is_label (char *str)
7691 {
7692 while (*str == ' ')
7693 str++;
7694 while (*str && *str != ' ')
7695 str++;
7696 if (str[-1] == ':' || str[1] == '=')
7697 return 1;
7698 return 0;
7699 }
7700
7701 #endif
7702
7703 /* Possible states for relaxation:
7704
7705 0 0 branch offset byte (bra, etc)
7706 0 1 word
7707 0 2 long
7708
7709 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7710 1 1 word
7711 1 2 long
7712
7713 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7714 2 1 word-long
7715 2 2 long-word
7716 2 3 long-long
7717
7718 */
7719
7720 /* We have no need to default values of symbols. */
7721
7722 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)7723 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7724 {
7725 return 0;
7726 }
7727
7728 /* Round up a section size to the appropriate boundary. */
7729 valueT
md_section_align(segT segment ATTRIBUTE_UNUSED,valueT size)7730 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7731 {
7732 return size;
7733 }
7734
7735 /* Exactly what point is a PC-relative offset relative TO?
7736 On the 68k, it is relative to the address of the first extension
7737 word. The difference between the addresses of the offset and the
7738 first extension word is stored in fx_pcrel_adjust. */
7739 long
md_pcrel_from(fixS * fixP)7740 md_pcrel_from (fixS *fixP)
7741 {
7742 int adjust;
7743
7744 adjust = fixP->fx_pcrel_adjust;
7745 if (adjust == 64)
7746 adjust = -1;
7747 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7748 }
7749
7750 void
m68k_elf_final_processing(void)7751 m68k_elf_final_processing (void)
7752 {
7753 unsigned flags = 0;
7754
7755 if (arch_coldfire_fpu (current_architecture))
7756 flags |= EF_M68K_CFV4E;
7757 /* Set file-specific flags if this is a cpu32 processor. */
7758 if (cpu_of_arch (current_architecture) & cpu32)
7759 flags |= EF_M68K_CPU32;
7760 else if (cpu_of_arch (current_architecture) & fido_a)
7761 flags |= EF_M68K_FIDO;
7762 else if ((cpu_of_arch (current_architecture) & m68000up)
7763 && !(cpu_of_arch (current_architecture) & m68020up))
7764 flags |= EF_M68K_M68000;
7765
7766 if (current_architecture & mcfisa_a)
7767 {
7768 static const unsigned isa_features[][2] =
7769 {
7770 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7771 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7772 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7773 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7774 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7775 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7776 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7777 {0,0},
7778 };
7779 static const unsigned mac_features[][2] =
7780 {
7781 {EF_M68K_CF_MAC, mcfmac},
7782 {EF_M68K_CF_EMAC, mcfemac},
7783 {0,0},
7784 };
7785 unsigned ix;
7786 unsigned pattern;
7787
7788 pattern = (current_architecture
7789 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7790 for (ix = 0; isa_features[ix][1]; ix++)
7791 {
7792 if (pattern == isa_features[ix][1])
7793 {
7794 flags |= isa_features[ix][0];
7795 break;
7796 }
7797 }
7798 if (!isa_features[ix][1])
7799 {
7800 cf_bad:
7801 as_warn (_("Not a defined coldfire architecture"));
7802 }
7803 else
7804 {
7805 if (current_architecture & cfloat)
7806 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7807
7808 pattern = current_architecture & (mcfmac|mcfemac);
7809 if (pattern)
7810 {
7811 for (ix = 0; mac_features[ix][1]; ix++)
7812 {
7813 if (pattern == mac_features[ix][1])
7814 {
7815 flags |= mac_features[ix][0];
7816 break;
7817 }
7818 }
7819 if (!mac_features[ix][1])
7820 goto cf_bad;
7821 }
7822 }
7823 }
7824 elf_elfheader (stdoutput)->e_flags |= flags;
7825 }
7826
7827 /* Parse @TLSLDO and return the desired relocation. */
7828 static bfd_reloc_code_real_type
m68k_elf_suffix(char ** str_p,expressionS * exp_p)7829 m68k_elf_suffix (char **str_p, expressionS *exp_p)
7830 {
7831 char ident[20];
7832 char *str = *str_p;
7833 char *str2;
7834 int ch;
7835 int len;
7836
7837 if (*str++ != '@')
7838 return BFD_RELOC_UNUSED;
7839
7840 for (ch = *str, str2 = ident;
7841 (str2 < ident + sizeof (ident) - 1
7842 && (ISALNUM (ch) || ch == '@'));
7843 ch = *++str)
7844 {
7845 *str2++ = ch;
7846 }
7847
7848 *str2 = '\0';
7849 len = str2 - ident;
7850
7851 if (startswith (ident, "TLSLDO")
7852 && len == 6)
7853 {
7854 /* Now check for identifier@suffix+constant. */
7855 if (*str == '-' || *str == '+')
7856 {
7857 char *orig_line = input_line_pointer;
7858 expressionS new_exp;
7859
7860 input_line_pointer = str;
7861 expression (&new_exp);
7862 if (new_exp.X_op == O_constant)
7863 {
7864 exp_p->X_add_number += new_exp.X_add_number;
7865 str = input_line_pointer;
7866 }
7867
7868 if (&input_line_pointer != str_p)
7869 input_line_pointer = orig_line;
7870 }
7871 *str_p = str;
7872
7873 return BFD_RELOC_68K_TLS_LDO32;
7874 }
7875
7876 return BFD_RELOC_UNUSED;
7877 }
7878
7879 /* Handles .long <tls_symbol>+0x8000 debug info.
7880 Clobbers input_line_pointer, checks end-of-line.
7881 Adapted from tc-ppc.c:ppc_elf_cons. */
7882 static void
m68k_elf_cons(int nbytes)7883 m68k_elf_cons (int nbytes /* 4=.long */)
7884 {
7885 if (is_it_end_of_statement ())
7886 {
7887 demand_empty_rest_of_line ();
7888 return;
7889 }
7890
7891 do
7892 {
7893 expressionS exp;
7894 bfd_reloc_code_real_type reloc;
7895
7896 expression (&exp);
7897 if (exp.X_op == O_symbol
7898 && *input_line_pointer == '@'
7899 && (reloc = m68k_elf_suffix (&input_line_pointer,
7900 &exp)) != BFD_RELOC_UNUSED)
7901 {
7902 reloc_howto_type *reloc_howto;
7903 int size;
7904
7905 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7906 size = bfd_get_reloc_size (reloc_howto);
7907
7908 if (size > nbytes)
7909 {
7910 as_bad (ngettext ("%s relocations do not fit in %u byte",
7911 "%s relocations do not fit in %u bytes",
7912 nbytes),
7913 reloc_howto->name, nbytes);
7914 }
7915 else
7916 {
7917 char *p;
7918 int offset;
7919
7920 p = frag_more (nbytes);
7921 offset = 0;
7922 if (target_big_endian)
7923 offset = nbytes - size;
7924 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7925 &exp, 0, reloc);
7926 }
7927 }
7928 else
7929 emit_expr (&exp, (unsigned int) nbytes);
7930 }
7931 while (*input_line_pointer++ == ',');
7932
7933 /* Put terminator back into stream. */
7934 input_line_pointer--;
7935 demand_empty_rest_of_line ();
7936 }
7937
7938 /* Parse a .gnu_attribute directive. */
7939 static void
m68k_elf_gnu_attribute(int ignored ATTRIBUTE_UNUSED)7940 m68k_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED)
7941 {
7942 int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU);
7943
7944 /* Check validity of defined m68k tags. */
7945 if (tag == Tag_GNU_M68K_ABI_FP)
7946 {
7947 unsigned int val;
7948
7949 val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag);
7950
7951 if (tag == Tag_GNU_M68K_ABI_FP && val > 2)
7952 as_warn (_("unknown .gnu_attribute value"));
7953 }
7954 }
7955
7956 int
tc_m68k_regname_to_dw2regnum(const char * regname)7957 tc_m68k_regname_to_dw2regnum (const char *regname)
7958 {
7959 unsigned int regnum;
7960 static const char *const regnames[] =
7961 {
7962 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7963 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7964 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7965 "pc"
7966 };
7967
7968 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7969 if (strcmp (regname, regnames[regnum]) == 0)
7970 return regnum;
7971
7972 return -1;
7973 }
7974
7975 void
tc_m68k_frame_initial_instructions(void)7976 tc_m68k_frame_initial_instructions (void)
7977 {
7978 static int sp_regno = -1;
7979
7980 if (sp_regno < 0)
7981 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7982
7983 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7984 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7985 }
7986
7987 /* Check and emit error if broken-word handling has failed to fix up a
7988 case-table. This is called from write.c, after doing everything it
7989 knows about how to handle broken words. */
7990
7991 void
tc_m68k_check_adjusted_broken_word(offsetT new_offset,struct broken_word * brokwP)7992 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
7993 {
7994 if (new_offset > 32767 || new_offset < -32768)
7995 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
7996 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
7997 (long) new_offset);
7998 }
7999
8000