1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_R (instr_info *, int, int);
78 static bool OP_M (instr_info *, int, int);
79 static bool OP_VEX (instr_info *, int, int);
80 static bool OP_VexR (instr_info *, int, int);
81 static bool OP_VexW (instr_info *, int, int);
82 static bool OP_Rounding (instr_info *, int, int);
83 static bool OP_REG_VexI4 (instr_info *, int, int);
84 static bool OP_VexI4 (instr_info *, int, int);
85 static bool OP_0f07 (instr_info *, int, int);
86 static bool OP_Monitor (instr_info *, int, int);
87 static bool OP_Mwait (instr_info *, int, int);
88
89 static bool PCLMUL_Fixup (instr_info *, int, int);
90 static bool VPCMP_Fixup (instr_info *, int, int);
91 static bool VPCOM_Fixup (instr_info *, int, int);
92 static bool NOP_Fixup (instr_info *, int, int);
93 static bool OP_3DNowSuffix (instr_info *, int, int);
94 static bool CMP_Fixup (instr_info *, int, int);
95 static bool REP_Fixup (instr_info *, int, int);
96 static bool SEP_Fixup (instr_info *, int, int);
97 static bool BND_Fixup (instr_info *, int, int);
98 static bool NOTRACK_Fixup (instr_info *, int, int);
99 static bool HLE_Fixup1 (instr_info *, int, int);
100 static bool HLE_Fixup2 (instr_info *, int, int);
101 static bool HLE_Fixup3 (instr_info *, int, int);
102 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
103 static bool XMM_Fixup (instr_info *, int, int);
104 static bool FXSAVE_Fixup (instr_info *, int, int);
105 static bool MOVSXD_Fixup (instr_info *, int, int);
106 static bool DistinctDest_Fixup (instr_info *, int, int);
107 static bool PREFETCHI_Fixup (instr_info *, int, int);
108 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
109 static bool JMPABS_Fixup (instr_info *, int, int);
110
111 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
112 enum disassembler_style,
113 const char *, ...);
114
115 /* This character is used to encode style information within the output
116 buffers. See oappend_insert_style for more details. */
117 #define STYLE_MARKER_CHAR '\002'
118
119 /* The maximum operand buffer size. */
120 #define MAX_OPERAND_BUFFER_SIZE 128
121
122 enum address_mode
123 {
124 mode_16bit,
125 mode_32bit,
126 mode_64bit
127 };
128
129 static const char *prefix_name (enum address_mode, uint8_t, int);
130
131 enum x86_64_isa
132 {
133 amd64 = 1,
134 intel64
135 };
136
137 enum evex_type
138 {
139 evex_default = 0,
140 evex_from_legacy,
141 evex_from_vex,
142 };
143
144 struct instr_info
145 {
146 enum address_mode address_mode;
147
148 /* Flags for the prefixes for the current instruction. See below. */
149 int prefixes;
150
151 /* REX prefix the current instruction. See below. */
152 uint8_t rex;
153 /* Bits of REX we've already used. */
154 uint8_t rex_used;
155
156 /* Record W R4 X4 B4 bits for rex2. */
157 unsigned char rex2;
158 /* Bits of rex2 we've already used. */
159 unsigned char rex2_used;
160 unsigned char rex2_payload;
161
162 bool need_modrm;
163 unsigned char need_vex;
164 bool has_sib;
165
166 /* Flags for ins->prefixes which we somehow handled when printing the
167 current instruction. */
168 int used_prefixes;
169
170 /* Flags for EVEX bits which we somehow handled when printing the
171 current instruction. */
172 int evex_used;
173
174 char obuf[MAX_OPERAND_BUFFER_SIZE];
175 char *obufp;
176 char *mnemonicendp;
177 const uint8_t *start_codep;
178 uint8_t *codep;
179 const uint8_t *end_codep;
180 unsigned char nr_prefixes;
181 signed char last_lock_prefix;
182 signed char last_repz_prefix;
183 signed char last_repnz_prefix;
184 signed char last_data_prefix;
185 signed char last_addr_prefix;
186 signed char last_rex_prefix;
187 signed char last_rex2_prefix;
188 signed char last_seg_prefix;
189 signed char fwait_prefix;
190 /* The active segment register prefix. */
191 unsigned char active_seg_prefix;
192
193 #define MAX_CODE_LENGTH 15
194 /* We can up to 14 ins->prefixes since the maximum instruction length is
195 15bytes. */
196 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
197 disassemble_info *info;
198
199 struct
200 {
201 int mod;
202 int reg;
203 int rm;
204 }
205 modrm;
206
207 struct
208 {
209 int scale;
210 int index;
211 int base;
212 }
213 sib;
214
215 struct
216 {
217 int register_specifier;
218 int length;
219 int prefix;
220 int mask_register_specifier;
221 int ll;
222 bool w;
223 bool evex;
224 bool v;
225 bool zeroing;
226 bool b;
227 bool no_broadcast;
228 bool nf;
229 }
230 vex;
231
232 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
233 #define nd b
234
235 enum evex_type evex_type;
236
237 /* Remember if the current op is a jump instruction. */
238 bool op_is_jump;
239
240 bool two_source_ops;
241
242 /* Record whether EVEX masking is used incorrectly. */
243 bool illegal_masking;
244
245 /* Record whether the modrm byte has been skipped. */
246 bool has_skipped_modrm;
247
248 unsigned char op_ad;
249 signed char op_index[MAX_OPERANDS];
250 bool op_riprel[MAX_OPERANDS];
251 char *op_out[MAX_OPERANDS];
252 bfd_vma op_address[MAX_OPERANDS];
253 bfd_vma start_pc;
254
255 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
256 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
257 * section of the "Virtual 8086 Mode" chapter.)
258 * 'pc' should be the address of this instruction, it will
259 * be used to print the target address if this is a relative jump or call
260 * The function returns the length of this instruction in bytes.
261 */
262 char intel_syntax;
263 bool intel_mnemonic;
264 char open_char;
265 char close_char;
266 char separator_char;
267 char scale_char;
268
269 enum x86_64_isa isa64;
270 };
271
272 struct dis_private {
273 bfd_vma insn_start;
274 int orig_sizeflag;
275
276 /* Indexes first byte not fetched. */
277 unsigned int fetched;
278 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
279 };
280
281 /* Mark parts used in the REX prefix. When we are testing for
282 empty prefix (for 8bit register REX extension), just mask it
283 out. Otherwise test for REX bit is excuse for existence of REX
284 only in case value is nonzero. */
285 #define USED_REX(value) \
286 { \
287 if (value) \
288 { \
289 if (ins->rex & value) \
290 ins->rex_used |= (value) | REX_OPCODE; \
291 if (ins->rex2 & value) \
292 { \
293 ins->rex2_used |= (value); \
294 ins->rex_used |= REX_OPCODE; \
295 } \
296 } \
297 else \
298 ins->rex_used |= REX_OPCODE; \
299 }
300
301
302 #define EVEX_b_used 1
303 #define EVEX_len_used 2
304
305
306 /* {rex2} is not printed when the REX2_SPECIAL is set. */
307 #define REX2_SPECIAL 16
308
309 /* Flags stored in PREFIXES. */
310 #define PREFIX_REPZ 1
311 #define PREFIX_REPNZ 2
312 #define PREFIX_CS 4
313 #define PREFIX_SS 8
314 #define PREFIX_DS 0x10
315 #define PREFIX_ES 0x20
316 #define PREFIX_FS 0x40
317 #define PREFIX_GS 0x80
318 #define PREFIX_LOCK 0x100
319 #define PREFIX_DATA 0x200
320 #define PREFIX_ADDR 0x400
321 #define PREFIX_FWAIT 0x800
322 #define PREFIX_REX2 0x1000
323 #define PREFIX_NP_OR_DATA 0x2000
324 #define NO_PREFIX 0x4000
325
326 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
327 to ADDR (exclusive) are valid. Returns true for success, false
328 on error. */
329 static bool
fetch_code(struct disassemble_info * info,const uint8_t * until)330 fetch_code (struct disassemble_info *info, const uint8_t *until)
331 {
332 int status = -1;
333 struct dis_private *priv = info->private_data;
334 bfd_vma start = priv->insn_start + priv->fetched;
335 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
336 ptrdiff_t needed = until - fetch_end;
337
338 if (needed <= 0)
339 return true;
340
341 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
342 status = (*info->read_memory_func) (start, fetch_end, needed, info);
343 if (status != 0)
344 {
345 /* If we did manage to read at least one byte, then
346 print_insn_i386 will do something sensible. Otherwise, print
347 an error. We do that here because this is where we know
348 STATUS. */
349 if (!priv->fetched)
350 (*info->memory_error_func) (status, start, info);
351 return false;
352 }
353
354 priv->fetched += needed;
355 return true;
356 }
357
358 static bool
fetch_modrm(instr_info * ins)359 fetch_modrm (instr_info *ins)
360 {
361 if (!fetch_code (ins->info, ins->codep + 1))
362 return false;
363
364 ins->modrm.mod = (*ins->codep >> 6) & 3;
365 ins->modrm.reg = (*ins->codep >> 3) & 7;
366 ins->modrm.rm = *ins->codep & 7;
367
368 return true;
369 }
370
371 static int
fetch_error(const instr_info * ins)372 fetch_error (const instr_info *ins)
373 {
374 /* Getting here means we tried for data but didn't get it. That
375 means we have an incomplete instruction of some sort. Just
376 print the first byte as a prefix or a .byte pseudo-op. */
377 const struct dis_private *priv = ins->info->private_data;
378 const char *name = NULL;
379
380 if (ins->codep <= priv->the_buffer)
381 return -1;
382
383 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
384 name = prefix_name (ins->address_mode, priv->the_buffer[0],
385 priv->orig_sizeflag);
386 if (name != NULL)
387 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
388 else
389 {
390 /* Just print the first byte as a .byte instruction. */
391 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
392 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
393 (unsigned int) priv->the_buffer[0]);
394 }
395
396 return 1;
397 }
398
399 /* Possible values for prefix requirement. */
400 #define PREFIX_IGNORED_SHIFT 16
401 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
402 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
403 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
404 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
405 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
406 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
407
408 /* Opcode prefixes. */
409 #define PREFIX_OPCODE (PREFIX_REPZ \
410 | PREFIX_REPNZ \
411 | PREFIX_DATA)
412
413 /* Prefixes ignored. */
414 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
415 | PREFIX_IGNORED_REPNZ \
416 | PREFIX_IGNORED_DATA)
417
418 #define XX { NULL, 0 }
419 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
420
421 #define Eb { OP_E, b_mode }
422 #define Ebnd { OP_E, bnd_mode }
423 #define EbS { OP_E, b_swap_mode }
424 #define EbndS { OP_E, bnd_swap_mode }
425 #define Ev { OP_E, v_mode }
426 #define Eva { OP_E, va_mode }
427 #define Ev_bnd { OP_E, v_bnd_mode }
428 #define EvS { OP_E, v_swap_mode }
429 #define Ed { OP_E, d_mode }
430 #define Edq { OP_E, dq_mode }
431 #define Edb { OP_E, db_mode }
432 #define Edw { OP_E, dw_mode }
433 #define Eq { OP_E, q_mode }
434 #define indirEv { OP_indirE, indir_v_mode }
435 #define indirEp { OP_indirE, f_mode }
436 #define stackEv { OP_E, stack_v_mode }
437 #define Em { OP_E, m_mode }
438 #define Ew { OP_E, w_mode }
439 #define M { OP_M, 0 } /* lea, lgdt, etc. */
440 #define Ma { OP_M, a_mode }
441 #define Mb { OP_M, b_mode }
442 #define Md { OP_M, d_mode }
443 #define Mdq { OP_M, dq_mode }
444 #define Mo { OP_M, o_mode }
445 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
446 #define Mq { OP_M, q_mode }
447 #define Mv { OP_M, v_mode }
448 #define Mv_bnd { OP_M, v_bndmk_mode }
449 #define Mw { OP_M, w_mode }
450 #define Mx { OP_M, x_mode }
451 #define Mxmm { OP_M, xmm_mode }
452 #define Mymm { OP_M, ymm_mode }
453 #define Gb { OP_G, b_mode }
454 #define Gbnd { OP_G, bnd_mode }
455 #define Gv { OP_G, v_mode }
456 #define Gd { OP_G, d_mode }
457 #define Gdq { OP_G, dq_mode }
458 #define Gq { OP_G, q_mode }
459 #define Gm { OP_G, m_mode }
460 #define Gva { OP_G, va_mode }
461 #define Gw { OP_G, w_mode }
462 #define Ib { OP_I, b_mode }
463 #define sIb { OP_sI, b_mode } /* sign extened byte */
464 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
465 #define Iv { OP_I, v_mode }
466 #define sIv { OP_sI, v_mode }
467 #define Iv64 { OP_I64, v_mode }
468 #define Id { OP_I, d_mode }
469 #define Iw { OP_I, w_mode }
470 #define I1 { OP_I, const_1_mode }
471 #define Jb { OP_J, b_mode }
472 #define Jv { OP_J, v_mode }
473 #define Jdqw { OP_J, dqw_mode }
474 #define Cm { OP_C, m_mode }
475 #define Dm { OP_D, m_mode }
476 #define Td { OP_T, d_mode }
477 #define Skip_MODRM { OP_Skip_MODRM, 0 }
478
479 #define RMeAX { OP_REG, eAX_reg }
480 #define RMeBX { OP_REG, eBX_reg }
481 #define RMeCX { OP_REG, eCX_reg }
482 #define RMeDX { OP_REG, eDX_reg }
483 #define RMeSP { OP_REG, eSP_reg }
484 #define RMeBP { OP_REG, eBP_reg }
485 #define RMeSI { OP_REG, eSI_reg }
486 #define RMeDI { OP_REG, eDI_reg }
487 #define RMrAX { OP_REG, rAX_reg }
488 #define RMrBX { OP_REG, rBX_reg }
489 #define RMrCX { OP_REG, rCX_reg }
490 #define RMrDX { OP_REG, rDX_reg }
491 #define RMrSP { OP_REG, rSP_reg }
492 #define RMrBP { OP_REG, rBP_reg }
493 #define RMrSI { OP_REG, rSI_reg }
494 #define RMrDI { OP_REG, rDI_reg }
495 #define RMAL { OP_REG, al_reg }
496 #define RMCL { OP_REG, cl_reg }
497 #define RMDL { OP_REG, dl_reg }
498 #define RMBL { OP_REG, bl_reg }
499 #define RMAH { OP_REG, ah_reg }
500 #define RMCH { OP_REG, ch_reg }
501 #define RMDH { OP_REG, dh_reg }
502 #define RMBH { OP_REG, bh_reg }
503 #define RMAX { OP_REG, ax_reg }
504 #define RMDX { OP_REG, dx_reg }
505
506 #define eAX { OP_IMREG, eAX_reg }
507 #define AL { OP_IMREG, al_reg }
508 #define CL { OP_IMREG, cl_reg }
509 #define zAX { OP_IMREG, z_mode_ax_reg }
510 #define indirDX { OP_IMREG, indir_dx_reg }
511
512 #define Sw { OP_SEG, w_mode }
513 #define Sv { OP_SEG, v_mode }
514 #define Ap { OP_DIR, 0 }
515 #define Ob { OP_OFF64, b_mode }
516 #define Ov { OP_OFF64, v_mode }
517 #define Xb { OP_DSreg, eSI_reg }
518 #define Xv { OP_DSreg, eSI_reg }
519 #define Xz { OP_DSreg, eSI_reg }
520 #define Yb { OP_ESreg, eDI_reg }
521 #define Yv { OP_ESreg, eDI_reg }
522 #define DSBX { OP_DSreg, eBX_reg }
523
524 #define es { OP_REG, es_reg }
525 #define ss { OP_REG, ss_reg }
526 #define cs { OP_REG, cs_reg }
527 #define ds { OP_REG, ds_reg }
528 #define fs { OP_REG, fs_reg }
529 #define gs { OP_REG, gs_reg }
530
531 #define MX { OP_MMX, 0 }
532 #define XM { OP_XMM, 0 }
533 #define XMScalar { OP_XMM, scalar_mode }
534 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
535 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
536 #define XMM { OP_XMM, xmm_mode }
537 #define TMM { OP_XMM, tmm_mode }
538 #define XMxmmq { OP_XMM, xmmq_mode }
539 #define EM { OP_EM, v_mode }
540 #define EMS { OP_EM, v_swap_mode }
541 #define EMd { OP_EM, d_mode }
542 #define EMx { OP_EM, x_mode }
543 #define EXbwUnit { OP_EX, bw_unit_mode }
544 #define EXb { OP_EX, b_mode }
545 #define EXw { OP_EX, w_mode }
546 #define EXd { OP_EX, d_mode }
547 #define EXdS { OP_EX, d_swap_mode }
548 #define EXwS { OP_EX, w_swap_mode }
549 #define EXq { OP_EX, q_mode }
550 #define EXqS { OP_EX, q_swap_mode }
551 #define EXdq { OP_EX, dq_mode }
552 #define EXx { OP_EX, x_mode }
553 #define EXxh { OP_EX, xh_mode }
554 #define EXxS { OP_EX, x_swap_mode }
555 #define EXxmm { OP_EX, xmm_mode }
556 #define EXymm { OP_EX, ymm_mode }
557 #define EXxmmq { OP_EX, xmmq_mode }
558 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
559 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
560 #define EXxmmdw { OP_EX, xmmdw_mode }
561 #define EXxmmqd { OP_EX, xmmqd_mode }
562 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
563 #define EXymmq { OP_EX, ymmq_mode }
564 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
565 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
566 #define Rd { OP_R, d_mode }
567 #define Rdq { OP_R, dq_mode }
568 #define Rq { OP_R, q_mode }
569 #define Nq { OP_R, q_mm_mode }
570 #define Ux { OP_R, x_mode }
571 #define Uxmm { OP_R, xmm_mode }
572 #define Rxmmq { OP_R, xmmq_mode }
573 #define Rymm { OP_R, ymm_mode }
574 #define Rtmm { OP_R, tmm_mode }
575 #define EMCq { OP_EMC, q_mode }
576 #define MXC { OP_MXC, 0 }
577 #define OPSUF { OP_3DNowSuffix, 0 }
578 #define SEP { SEP_Fixup, 0 }
579 #define CMP { CMP_Fixup, 0 }
580 #define XMM0 { XMM_Fixup, 0 }
581 #define FXSAVE { FXSAVE_Fixup, 0 }
582
583 #define Vex { OP_VEX, x_mode }
584 #define VexW { OP_VexW, x_mode }
585 #define VexScalar { OP_VEX, scalar_mode }
586 #define VexScalarR { OP_VexR, scalar_mode }
587 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
588 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
589 #define VexGdq { OP_VEX, dq_mode }
590 #define VexGb { OP_VEX, b_mode }
591 #define VexGv { OP_VEX, v_mode }
592 #define VexTmm { OP_VEX, tmm_mode }
593 #define XMVexI4 { OP_REG_VexI4, x_mode }
594 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
595 #define VexI4 { OP_VexI4, 0 }
596 #define PCLMUL { PCLMUL_Fixup, 0 }
597 #define VPCMP { VPCMP_Fixup, 0 }
598 #define VPCOM { VPCOM_Fixup, 0 }
599
600 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
601 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
602 #define EXxEVexS { OP_Rounding, evex_sae_mode }
603
604 #define MaskG { OP_G, mask_mode }
605 #define MaskE { OP_E, mask_mode }
606 #define MaskR { OP_R, mask_mode }
607 #define MaskBDE { OP_E, mask_bd_mode }
608 #define MaskVex { OP_VEX, mask_mode }
609
610 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
611 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
612
613 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
614
615 /* Used handle "rep" prefix for string instructions. */
616 #define Xbr { REP_Fixup, eSI_reg }
617 #define Xvr { REP_Fixup, eSI_reg }
618 #define Ybr { REP_Fixup, eDI_reg }
619 #define Yvr { REP_Fixup, eDI_reg }
620 #define Yzr { REP_Fixup, eDI_reg }
621 #define indirDXr { REP_Fixup, indir_dx_reg }
622 #define ALr { REP_Fixup, al_reg }
623 #define eAXr { REP_Fixup, eAX_reg }
624
625 /* Used handle HLE prefix for lockable instructions. */
626 #define Ebh1 { HLE_Fixup1, b_mode }
627 #define Evh1 { HLE_Fixup1, v_mode }
628 #define Ebh2 { HLE_Fixup2, b_mode }
629 #define Evh2 { HLE_Fixup2, v_mode }
630 #define Ebh3 { HLE_Fixup3, b_mode }
631 #define Evh3 { HLE_Fixup3, v_mode }
632
633 #define BND { BND_Fixup, 0 }
634 #define NOTRACK { NOTRACK_Fixup, 0 }
635
636 #define cond_jump_flag { NULL, cond_jump_mode }
637 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
638
639 /* bits in sizeflag */
640 #define SUFFIX_ALWAYS 4
641 #define AFLAG 2
642 #define DFLAG 1
643
644 enum
645 {
646 /* byte operand */
647 b_mode = 1,
648 /* byte operand with operand swapped */
649 b_swap_mode,
650 /* byte operand, sign extend like 'T' suffix */
651 b_T_mode,
652 /* operand size depends on prefixes */
653 v_mode,
654 /* operand size depends on prefixes with operand swapped */
655 v_swap_mode,
656 /* operand size depends on address prefix */
657 va_mode,
658 /* word operand */
659 w_mode,
660 /* double word operand */
661 d_mode,
662 /* word operand with operand swapped */
663 w_swap_mode,
664 /* double word operand with operand swapped */
665 d_swap_mode,
666 /* quad word operand */
667 q_mode,
668 /* 8-byte MM operand */
669 q_mm_mode,
670 /* quad word operand with operand swapped */
671 q_swap_mode,
672 /* ten-byte operand */
673 t_mode,
674 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
675 broadcast enabled. */
676 x_mode,
677 /* Similar to x_mode, but with different EVEX mem shifts. */
678 evex_x_gscat_mode,
679 /* Similar to x_mode, but with yet different EVEX mem shifts. */
680 bw_unit_mode,
681 /* Similar to x_mode, but with disabled broadcast. */
682 evex_x_nobcst_mode,
683 /* Similar to x_mode, but with operands swapped and disabled broadcast
684 in EVEX. */
685 x_swap_mode,
686 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
687 broadcast of 16bit enabled. */
688 xh_mode,
689 /* 16-byte XMM operand */
690 xmm_mode,
691 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
692 memory operand (depending on vector length). Broadcast isn't
693 allowed. */
694 xmmq_mode,
695 /* Same as xmmq_mode, but broadcast is allowed. */
696 evex_half_bcst_xmmq_mode,
697 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
698 memory operand (depending on vector length). 16bit broadcast. */
699 evex_half_bcst_xmmqh_mode,
700 /* 16-byte XMM, word, double word or quad word operand. */
701 xmmdw_mode,
702 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
703 xmmqd_mode,
704 /* 16-byte XMM, double word, quad word operand or xmm word operand.
705 16bit broadcast. */
706 evex_half_bcst_xmmqdh_mode,
707 /* 32-byte YMM operand */
708 ymm_mode,
709 /* quad word, ymmword or zmmword memory operand. */
710 ymmq_mode,
711 /* TMM operand */
712 tmm_mode,
713 /* d_mode in 32bit, q_mode in 64bit mode. */
714 m_mode,
715 /* pair of v_mode operands */
716 a_mode,
717 cond_jump_mode,
718 loop_jcxz_mode,
719 movsxd_mode,
720 v_bnd_mode,
721 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
722 v_bndmk_mode,
723 /* operand size depends on REX.W / VEX.W. */
724 dq_mode,
725 /* Displacements like v_mode without considering Intel64 ISA. */
726 dqw_mode,
727 /* bounds operand */
728 bnd_mode,
729 /* bounds operand with operand swapped */
730 bnd_swap_mode,
731 /* 4- or 6-byte pointer operand */
732 f_mode,
733 const_1_mode,
734 /* v_mode for indirect branch opcodes. */
735 indir_v_mode,
736 /* v_mode for stack-related opcodes. */
737 stack_v_mode,
738 /* non-quad operand size depends on prefixes */
739 z_mode,
740 /* 16-byte operand */
741 o_mode,
742 /* registers like d_mode, memory like b_mode. */
743 db_mode,
744 /* registers like d_mode, memory like w_mode. */
745 dw_mode,
746
747 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
748 vex_vsib_d_w_dq_mode,
749 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
750 vex_vsib_q_w_dq_mode,
751 /* mandatory non-vector SIB. */
752 vex_sibmem_mode,
753
754 /* scalar, ignore vector length. */
755 scalar_mode,
756
757 /* Static rounding. */
758 evex_rounding_mode,
759 /* Static rounding, 64-bit mode only. */
760 evex_rounding_64_mode,
761 /* Supress all exceptions. */
762 evex_sae_mode,
763
764 /* Mask register operand. */
765 mask_mode,
766 /* Mask register operand. */
767 mask_bd_mode,
768
769 es_reg,
770 cs_reg,
771 ss_reg,
772 ds_reg,
773 fs_reg,
774 gs_reg,
775
776 eAX_reg,
777 eCX_reg,
778 eDX_reg,
779 eBX_reg,
780 eSP_reg,
781 eBP_reg,
782 eSI_reg,
783 eDI_reg,
784
785 al_reg,
786 cl_reg,
787 dl_reg,
788 bl_reg,
789 ah_reg,
790 ch_reg,
791 dh_reg,
792 bh_reg,
793
794 ax_reg,
795 cx_reg,
796 dx_reg,
797 bx_reg,
798 sp_reg,
799 bp_reg,
800 si_reg,
801 di_reg,
802
803 rAX_reg,
804 rCX_reg,
805 rDX_reg,
806 rBX_reg,
807 rSP_reg,
808 rBP_reg,
809 rSI_reg,
810 rDI_reg,
811
812 z_mode_ax_reg,
813 indir_dx_reg
814 };
815
816 enum
817 {
818 FLOATCODE = 1,
819 USE_REG_TABLE,
820 USE_MOD_TABLE,
821 USE_RM_TABLE,
822 USE_PREFIX_TABLE,
823 USE_X86_64_TABLE,
824 USE_X86_64_EVEX_FROM_VEX_TABLE,
825 USE_X86_64_EVEX_PFX_TABLE,
826 USE_X86_64_EVEX_W_TABLE,
827 USE_X86_64_EVEX_MEM_W_TABLE,
828 USE_3BYTE_TABLE,
829 USE_XOP_8F_TABLE,
830 USE_VEX_C4_TABLE,
831 USE_VEX_C5_TABLE,
832 USE_VEX_LEN_TABLE,
833 USE_VEX_W_TABLE,
834 USE_EVEX_TABLE,
835 USE_EVEX_LEN_TABLE
836 };
837
838 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
839
840 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
841 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
842 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
843 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
844 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
845 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
846 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
847 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
848 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
849 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
850 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
851 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
852 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
853 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
854 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
855 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
856 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
857 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
858 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
859
860 enum
861 {
862 REG_80 = 0,
863 REG_81,
864 REG_83,
865 REG_8F,
866 REG_C0,
867 REG_C1,
868 REG_C6,
869 REG_C7,
870 REG_D0,
871 REG_D1,
872 REG_D2,
873 REG_D3,
874 REG_F6,
875 REG_F7,
876 REG_FE,
877 REG_FF,
878 REG_0F00,
879 REG_0F01,
880 REG_0F0D,
881 REG_0F18,
882 REG_0F1C_P_0_MOD_0,
883 REG_0F1E_P_1_MOD_3,
884 REG_0F38D8_PREFIX_1,
885 REG_0F3A0F_P_1,
886 REG_0F71,
887 REG_0F72,
888 REG_0F73,
889 REG_0FA6,
890 REG_0FA7,
891 REG_0FAE,
892 REG_0FBA,
893 REG_0FC7,
894 REG_VEX_0F71,
895 REG_VEX_0F72,
896 REG_VEX_0F73,
897 REG_VEX_0FAE,
898 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
899 REG_VEX_0F38F3_L_0_P_0,
900 REG_VEX_MAP7_F8_L_0_W_0,
901
902 REG_XOP_09_01_L_0,
903 REG_XOP_09_02_L_0,
904 REG_XOP_09_12_L_0,
905 REG_XOP_0A_12_L_0,
906
907 REG_EVEX_0F71,
908 REG_EVEX_0F72,
909 REG_EVEX_0F73,
910 REG_EVEX_0F38C6_L_2,
911 REG_EVEX_0F38C7_L_2,
912 REG_EVEX_MAP4_80,
913 REG_EVEX_MAP4_81,
914 REG_EVEX_MAP4_83,
915 REG_EVEX_MAP4_8F,
916 REG_EVEX_MAP4_F6,
917 REG_EVEX_MAP4_F7,
918 REG_EVEX_MAP4_FE,
919 REG_EVEX_MAP4_FF,
920 };
921
922 enum
923 {
924 MOD_62_32BIT = 0,
925 MOD_C4_32BIT,
926 MOD_C5_32BIT,
927 MOD_0F01_REG_0,
928 MOD_0F01_REG_1,
929 MOD_0F01_REG_2,
930 MOD_0F01_REG_3,
931 MOD_0F01_REG_5,
932 MOD_0F01_REG_7,
933 MOD_0F12_PREFIX_0,
934 MOD_0F16_PREFIX_0,
935 MOD_0F18_REG_0,
936 MOD_0F18_REG_1,
937 MOD_0F18_REG_2,
938 MOD_0F18_REG_3,
939 MOD_0F18_REG_6,
940 MOD_0F18_REG_7,
941 MOD_0F1A_PREFIX_0,
942 MOD_0F1B_PREFIX_0,
943 MOD_0F1B_PREFIX_1,
944 MOD_0F1C_PREFIX_0,
945 MOD_0F1E_PREFIX_1,
946 MOD_0FAE_REG_0,
947 MOD_0FAE_REG_1,
948 MOD_0FAE_REG_2,
949 MOD_0FAE_REG_3,
950 MOD_0FAE_REG_4,
951 MOD_0FAE_REG_5,
952 MOD_0FAE_REG_6,
953 MOD_0FAE_REG_7,
954 MOD_0FC7_REG_6,
955 MOD_0FC7_REG_7,
956 MOD_0F38DC_PREFIX_1,
957 MOD_0F38F8,
958
959 MOD_VEX_0F3849_X86_64_L_0_W_0,
960
961 MOD_EVEX_MAP4_F8_P_1,
962 MOD_EVEX_MAP4_F8_P_3,
963 };
964
965 enum
966 {
967 RM_C6_REG_7 = 0,
968 RM_C7_REG_7,
969 RM_0F01_REG_0,
970 RM_0F01_REG_1,
971 RM_0F01_REG_2,
972 RM_0F01_REG_3,
973 RM_0F01_REG_5_MOD_3,
974 RM_0F01_REG_7_MOD_3,
975 RM_0F1E_P_1_MOD_3_REG_7,
976 RM_0FAE_REG_6_MOD_3_P_0,
977 RM_0FAE_REG_7_MOD_3,
978 RM_0F3A0F_P_1_R_0,
979
980 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
981 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
982 };
983
984 enum
985 {
986 PREFIX_90 = 0,
987 PREFIX_0F00_REG_6_X86_64,
988 PREFIX_0F01_REG_0_MOD_3_RM_6,
989 PREFIX_0F01_REG_0_MOD_3_RM_7,
990 PREFIX_0F01_REG_1_RM_2,
991 PREFIX_0F01_REG_1_RM_4,
992 PREFIX_0F01_REG_1_RM_5,
993 PREFIX_0F01_REG_1_RM_6,
994 PREFIX_0F01_REG_1_RM_7,
995 PREFIX_0F01_REG_3_RM_1,
996 PREFIX_0F01_REG_5_MOD_0,
997 PREFIX_0F01_REG_5_MOD_3_RM_0,
998 PREFIX_0F01_REG_5_MOD_3_RM_1,
999 PREFIX_0F01_REG_5_MOD_3_RM_2,
1000 PREFIX_0F01_REG_5_MOD_3_RM_4,
1001 PREFIX_0F01_REG_5_MOD_3_RM_5,
1002 PREFIX_0F01_REG_5_MOD_3_RM_6,
1003 PREFIX_0F01_REG_5_MOD_3_RM_7,
1004 PREFIX_0F01_REG_7_MOD_3_RM_2,
1005 PREFIX_0F01_REG_7_MOD_3_RM_5,
1006 PREFIX_0F01_REG_7_MOD_3_RM_6,
1007 PREFIX_0F01_REG_7_MOD_3_RM_7,
1008 PREFIX_0F09,
1009 PREFIX_0F10,
1010 PREFIX_0F11,
1011 PREFIX_0F12,
1012 PREFIX_0F16,
1013 PREFIX_0F18_REG_6_MOD_0_X86_64,
1014 PREFIX_0F18_REG_7_MOD_0_X86_64,
1015 PREFIX_0F1A,
1016 PREFIX_0F1B,
1017 PREFIX_0F1C,
1018 PREFIX_0F1E,
1019 PREFIX_0F2A,
1020 PREFIX_0F2B,
1021 PREFIX_0F2C,
1022 PREFIX_0F2D,
1023 PREFIX_0F2E,
1024 PREFIX_0F2F,
1025 PREFIX_0F51,
1026 PREFIX_0F52,
1027 PREFIX_0F53,
1028 PREFIX_0F58,
1029 PREFIX_0F59,
1030 PREFIX_0F5A,
1031 PREFIX_0F5B,
1032 PREFIX_0F5C,
1033 PREFIX_0F5D,
1034 PREFIX_0F5E,
1035 PREFIX_0F5F,
1036 PREFIX_0F60,
1037 PREFIX_0F61,
1038 PREFIX_0F62,
1039 PREFIX_0F6F,
1040 PREFIX_0F70,
1041 PREFIX_0F78,
1042 PREFIX_0F79,
1043 PREFIX_0F7C,
1044 PREFIX_0F7D,
1045 PREFIX_0F7E,
1046 PREFIX_0F7F,
1047 PREFIX_0FAE_REG_0_MOD_3,
1048 PREFIX_0FAE_REG_1_MOD_3,
1049 PREFIX_0FAE_REG_2_MOD_3,
1050 PREFIX_0FAE_REG_3_MOD_3,
1051 PREFIX_0FAE_REG_4_MOD_0,
1052 PREFIX_0FAE_REG_4_MOD_3,
1053 PREFIX_0FAE_REG_5_MOD_3,
1054 PREFIX_0FAE_REG_6_MOD_0,
1055 PREFIX_0FAE_REG_6_MOD_3,
1056 PREFIX_0FAE_REG_7_MOD_0,
1057 PREFIX_0FB8,
1058 PREFIX_0FBC,
1059 PREFIX_0FBD,
1060 PREFIX_0FC2,
1061 PREFIX_0FC7_REG_6_MOD_0,
1062 PREFIX_0FC7_REG_6_MOD_3,
1063 PREFIX_0FC7_REG_7_MOD_3,
1064 PREFIX_0FD0,
1065 PREFIX_0FD6,
1066 PREFIX_0FE6,
1067 PREFIX_0FE7,
1068 PREFIX_0FF0,
1069 PREFIX_0FF7,
1070 PREFIX_0F38D8,
1071 PREFIX_0F38DC,
1072 PREFIX_0F38DD,
1073 PREFIX_0F38DE,
1074 PREFIX_0F38DF,
1075 PREFIX_0F38F0,
1076 PREFIX_0F38F1,
1077 PREFIX_0F38F6,
1078 PREFIX_0F38F8_M_0,
1079 PREFIX_0F38F8_M_1_X86_64,
1080 PREFIX_0F38FA,
1081 PREFIX_0F38FB,
1082 PREFIX_0F38FC,
1083 PREFIX_0F3A0F,
1084 PREFIX_VEX_0F12,
1085 PREFIX_VEX_0F16,
1086 PREFIX_VEX_0F2A,
1087 PREFIX_VEX_0F2C,
1088 PREFIX_VEX_0F2D,
1089 PREFIX_VEX_0F41_L_1_W_0,
1090 PREFIX_VEX_0F41_L_1_W_1,
1091 PREFIX_VEX_0F42_L_1_W_0,
1092 PREFIX_VEX_0F42_L_1_W_1,
1093 PREFIX_VEX_0F44_L_0_W_0,
1094 PREFIX_VEX_0F44_L_0_W_1,
1095 PREFIX_VEX_0F45_L_1_W_0,
1096 PREFIX_VEX_0F45_L_1_W_1,
1097 PREFIX_VEX_0F46_L_1_W_0,
1098 PREFIX_VEX_0F46_L_1_W_1,
1099 PREFIX_VEX_0F47_L_1_W_0,
1100 PREFIX_VEX_0F47_L_1_W_1,
1101 PREFIX_VEX_0F4A_L_1_W_0,
1102 PREFIX_VEX_0F4A_L_1_W_1,
1103 PREFIX_VEX_0F4B_L_1_W_0,
1104 PREFIX_VEX_0F4B_L_1_W_1,
1105 PREFIX_VEX_0F6F,
1106 PREFIX_VEX_0F70,
1107 PREFIX_VEX_0F7E,
1108 PREFIX_VEX_0F7F,
1109 PREFIX_VEX_0F90_L_0_W_0,
1110 PREFIX_VEX_0F90_L_0_W_1,
1111 PREFIX_VEX_0F91_L_0_W_0,
1112 PREFIX_VEX_0F91_L_0_W_1,
1113 PREFIX_VEX_0F92_L_0_W_0,
1114 PREFIX_VEX_0F92_L_0_W_1,
1115 PREFIX_VEX_0F93_L_0_W_0,
1116 PREFIX_VEX_0F93_L_0_W_1,
1117 PREFIX_VEX_0F98_L_0_W_0,
1118 PREFIX_VEX_0F98_L_0_W_1,
1119 PREFIX_VEX_0F99_L_0_W_0,
1120 PREFIX_VEX_0F99_L_0_W_1,
1121 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1122 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1123 PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1124 PREFIX_VEX_0F3850_W_0,
1125 PREFIX_VEX_0F3851_W_0,
1126 PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1127 PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1128 PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1129 PREFIX_VEX_0F3872,
1130 PREFIX_VEX_0F38B0_W_0,
1131 PREFIX_VEX_0F38B1_W_0,
1132 PREFIX_VEX_0F38D2_W_0,
1133 PREFIX_VEX_0F38D3_W_0,
1134 PREFIX_VEX_0F38CB,
1135 PREFIX_VEX_0F38CC,
1136 PREFIX_VEX_0F38CD,
1137 PREFIX_VEX_0F38DA_W_0,
1138 PREFIX_VEX_0F38F2_L_0,
1139 PREFIX_VEX_0F38F3_L_0,
1140 PREFIX_VEX_0F38F5_L_0,
1141 PREFIX_VEX_0F38F6_L_0,
1142 PREFIX_VEX_0F38F7_L_0,
1143 PREFIX_VEX_0F3AF0_L_0,
1144 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1145
1146 PREFIX_EVEX_0F5B,
1147 PREFIX_EVEX_0F6F,
1148 PREFIX_EVEX_0F70,
1149 PREFIX_EVEX_0F78,
1150 PREFIX_EVEX_0F79,
1151 PREFIX_EVEX_0F7A,
1152 PREFIX_EVEX_0F7B,
1153 PREFIX_EVEX_0F7E,
1154 PREFIX_EVEX_0F7F,
1155 PREFIX_EVEX_0FC2,
1156 PREFIX_EVEX_0FE6,
1157 PREFIX_EVEX_0F3810,
1158 PREFIX_EVEX_0F3811,
1159 PREFIX_EVEX_0F3812,
1160 PREFIX_EVEX_0F3813,
1161 PREFIX_EVEX_0F3814,
1162 PREFIX_EVEX_0F3815,
1163 PREFIX_EVEX_0F3820,
1164 PREFIX_EVEX_0F3821,
1165 PREFIX_EVEX_0F3822,
1166 PREFIX_EVEX_0F3823,
1167 PREFIX_EVEX_0F3824,
1168 PREFIX_EVEX_0F3825,
1169 PREFIX_EVEX_0F3826,
1170 PREFIX_EVEX_0F3827,
1171 PREFIX_EVEX_0F3828,
1172 PREFIX_EVEX_0F3829,
1173 PREFIX_EVEX_0F382A,
1174 PREFIX_EVEX_0F3830,
1175 PREFIX_EVEX_0F3831,
1176 PREFIX_EVEX_0F3832,
1177 PREFIX_EVEX_0F3833,
1178 PREFIX_EVEX_0F3834,
1179 PREFIX_EVEX_0F3835,
1180 PREFIX_EVEX_0F3838,
1181 PREFIX_EVEX_0F3839,
1182 PREFIX_EVEX_0F383A,
1183 PREFIX_EVEX_0F3852,
1184 PREFIX_EVEX_0F3853,
1185 PREFIX_EVEX_0F3868,
1186 PREFIX_EVEX_0F3872,
1187 PREFIX_EVEX_0F389A,
1188 PREFIX_EVEX_0F389B,
1189 PREFIX_EVEX_0F38AA,
1190 PREFIX_EVEX_0F38AB,
1191
1192 PREFIX_EVEX_0F3A08,
1193 PREFIX_EVEX_0F3A0A,
1194 PREFIX_EVEX_0F3A26,
1195 PREFIX_EVEX_0F3A27,
1196 PREFIX_EVEX_0F3A56,
1197 PREFIX_EVEX_0F3A57,
1198 PREFIX_EVEX_0F3A66,
1199 PREFIX_EVEX_0F3A67,
1200 PREFIX_EVEX_0F3AC2,
1201
1202 PREFIX_EVEX_MAP4_40,
1203 PREFIX_EVEX_MAP4_41,
1204 PREFIX_EVEX_MAP4_42,
1205 PREFIX_EVEX_MAP4_43,
1206 PREFIX_EVEX_MAP4_44,
1207 PREFIX_EVEX_MAP4_45,
1208 PREFIX_EVEX_MAP4_46,
1209 PREFIX_EVEX_MAP4_47,
1210 PREFIX_EVEX_MAP4_48,
1211 PREFIX_EVEX_MAP4_49,
1212 PREFIX_EVEX_MAP4_4A,
1213 PREFIX_EVEX_MAP4_4B,
1214 PREFIX_EVEX_MAP4_4C,
1215 PREFIX_EVEX_MAP4_4D,
1216 PREFIX_EVEX_MAP4_4E,
1217 PREFIX_EVEX_MAP4_4F,
1218 PREFIX_EVEX_MAP4_F0,
1219 PREFIX_EVEX_MAP4_F1,
1220 PREFIX_EVEX_MAP4_F2,
1221 PREFIX_EVEX_MAP4_F8,
1222
1223 PREFIX_EVEX_MAP5_10,
1224 PREFIX_EVEX_MAP5_11,
1225 PREFIX_EVEX_MAP5_1D,
1226 PREFIX_EVEX_MAP5_2A,
1227 PREFIX_EVEX_MAP5_2C,
1228 PREFIX_EVEX_MAP5_2D,
1229 PREFIX_EVEX_MAP5_2E,
1230 PREFIX_EVEX_MAP5_2F,
1231 PREFIX_EVEX_MAP5_51,
1232 PREFIX_EVEX_MAP5_58,
1233 PREFIX_EVEX_MAP5_59,
1234 PREFIX_EVEX_MAP5_5A,
1235 PREFIX_EVEX_MAP5_5B,
1236 PREFIX_EVEX_MAP5_5C,
1237 PREFIX_EVEX_MAP5_5D,
1238 PREFIX_EVEX_MAP5_5E,
1239 PREFIX_EVEX_MAP5_5F,
1240 PREFIX_EVEX_MAP5_78,
1241 PREFIX_EVEX_MAP5_79,
1242 PREFIX_EVEX_MAP5_7A,
1243 PREFIX_EVEX_MAP5_7B,
1244 PREFIX_EVEX_MAP5_7C,
1245 PREFIX_EVEX_MAP5_7D,
1246
1247 PREFIX_EVEX_MAP6_13,
1248 PREFIX_EVEX_MAP6_56,
1249 PREFIX_EVEX_MAP6_57,
1250 PREFIX_EVEX_MAP6_D6,
1251 PREFIX_EVEX_MAP6_D7,
1252 };
1253
1254 enum
1255 {
1256 X86_64_06 = 0,
1257 X86_64_07,
1258 X86_64_0E,
1259 X86_64_16,
1260 X86_64_17,
1261 X86_64_1E,
1262 X86_64_1F,
1263 X86_64_27,
1264 X86_64_2F,
1265 X86_64_37,
1266 X86_64_3F,
1267 X86_64_60,
1268 X86_64_61,
1269 X86_64_62,
1270 X86_64_63,
1271 X86_64_6D,
1272 X86_64_6F,
1273 X86_64_82,
1274 X86_64_9A,
1275 X86_64_C2,
1276 X86_64_C3,
1277 X86_64_C4,
1278 X86_64_C5,
1279 X86_64_CE,
1280 X86_64_D4,
1281 X86_64_D5,
1282 X86_64_E8,
1283 X86_64_E9,
1284 X86_64_EA,
1285 X86_64_0F00_REG_6,
1286 X86_64_0F01_REG_0,
1287 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1288 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1289 X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1290 X86_64_0F01_REG_1,
1291 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1292 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1293 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1294 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1295 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1296 X86_64_0F01_REG_2,
1297 X86_64_0F01_REG_3,
1298 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1299 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1300 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1301 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1302 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1303 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1304 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1305 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1306 X86_64_0F18_REG_6_MOD_0,
1307 X86_64_0F18_REG_7_MOD_0,
1308 X86_64_0F24,
1309 X86_64_0F26,
1310 X86_64_0F38F8_M_1,
1311 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1312
1313 X86_64_VEX_0F3849,
1314 X86_64_VEX_0F384B,
1315 X86_64_VEX_0F385C,
1316 X86_64_VEX_0F385E,
1317 X86_64_VEX_0F386C,
1318 X86_64_VEX_0F38E0,
1319 X86_64_VEX_0F38E1,
1320 X86_64_VEX_0F38E2,
1321 X86_64_VEX_0F38E3,
1322 X86_64_VEX_0F38E4,
1323 X86_64_VEX_0F38E5,
1324 X86_64_VEX_0F38E6,
1325 X86_64_VEX_0F38E7,
1326 X86_64_VEX_0F38E8,
1327 X86_64_VEX_0F38E9,
1328 X86_64_VEX_0F38EA,
1329 X86_64_VEX_0F38EB,
1330 X86_64_VEX_0F38EC,
1331 X86_64_VEX_0F38ED,
1332 X86_64_VEX_0F38EE,
1333 X86_64_VEX_0F38EF,
1334
1335 X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1336 };
1337
1338 enum
1339 {
1340 THREE_BYTE_0F38 = 0,
1341 THREE_BYTE_0F3A
1342 };
1343
1344 enum
1345 {
1346 XOP_08 = 0,
1347 XOP_09,
1348 XOP_0A
1349 };
1350
1351 enum
1352 {
1353 VEX_0F = 0,
1354 VEX_0F38,
1355 VEX_0F3A,
1356 VEX_MAP7,
1357 };
1358
1359 enum
1360 {
1361 EVEX_0F = 0,
1362 EVEX_0F38,
1363 EVEX_0F3A,
1364 EVEX_MAP4,
1365 EVEX_MAP5,
1366 EVEX_MAP6,
1367 EVEX_MAP7,
1368 };
1369
1370 enum
1371 {
1372 VEX_LEN_0F12_P_0 = 0,
1373 VEX_LEN_0F12_P_2,
1374 VEX_LEN_0F13,
1375 VEX_LEN_0F16_P_0,
1376 VEX_LEN_0F16_P_2,
1377 VEX_LEN_0F17,
1378 VEX_LEN_0F41,
1379 VEX_LEN_0F42,
1380 VEX_LEN_0F44,
1381 VEX_LEN_0F45,
1382 VEX_LEN_0F46,
1383 VEX_LEN_0F47,
1384 VEX_LEN_0F4A,
1385 VEX_LEN_0F4B,
1386 VEX_LEN_0F6E,
1387 VEX_LEN_0F77,
1388 VEX_LEN_0F7E_P_1,
1389 VEX_LEN_0F7E_P_2,
1390 VEX_LEN_0F90,
1391 VEX_LEN_0F91,
1392 VEX_LEN_0F92,
1393 VEX_LEN_0F93,
1394 VEX_LEN_0F98,
1395 VEX_LEN_0F99,
1396 VEX_LEN_0FAE_R_2,
1397 VEX_LEN_0FAE_R_3,
1398 VEX_LEN_0FC4,
1399 VEX_LEN_0FD6,
1400 VEX_LEN_0F3816,
1401 VEX_LEN_0F3819,
1402 VEX_LEN_0F381A,
1403 VEX_LEN_0F3836,
1404 VEX_LEN_0F3841,
1405 VEX_LEN_0F3849_X86_64,
1406 VEX_LEN_0F384B_X86_64,
1407 VEX_LEN_0F385A,
1408 VEX_LEN_0F385C_X86_64,
1409 VEX_LEN_0F385E_X86_64,
1410 VEX_LEN_0F386C_X86_64,
1411 VEX_LEN_0F38CB_P_3_W_0,
1412 VEX_LEN_0F38CC_P_3_W_0,
1413 VEX_LEN_0F38CD_P_3_W_0,
1414 VEX_LEN_0F38DA_W_0_P_0,
1415 VEX_LEN_0F38DA_W_0_P_2,
1416 VEX_LEN_0F38DB,
1417 VEX_LEN_0F38F2,
1418 VEX_LEN_0F38F3,
1419 VEX_LEN_0F38F5,
1420 VEX_LEN_0F38F6,
1421 VEX_LEN_0F38F7,
1422 VEX_LEN_0F3A00,
1423 VEX_LEN_0F3A01,
1424 VEX_LEN_0F3A06,
1425 VEX_LEN_0F3A14,
1426 VEX_LEN_0F3A15,
1427 VEX_LEN_0F3A16,
1428 VEX_LEN_0F3A17,
1429 VEX_LEN_0F3A18,
1430 VEX_LEN_0F3A19,
1431 VEX_LEN_0F3A20,
1432 VEX_LEN_0F3A21,
1433 VEX_LEN_0F3A22,
1434 VEX_LEN_0F3A30,
1435 VEX_LEN_0F3A31,
1436 VEX_LEN_0F3A32,
1437 VEX_LEN_0F3A33,
1438 VEX_LEN_0F3A38,
1439 VEX_LEN_0F3A39,
1440 VEX_LEN_0F3A41,
1441 VEX_LEN_0F3A46,
1442 VEX_LEN_0F3A60,
1443 VEX_LEN_0F3A61,
1444 VEX_LEN_0F3A62,
1445 VEX_LEN_0F3A63,
1446 VEX_LEN_0F3ADE_W_0,
1447 VEX_LEN_0F3ADF,
1448 VEX_LEN_0F3AF0,
1449 VEX_LEN_MAP7_F8,
1450 VEX_LEN_XOP_08_85,
1451 VEX_LEN_XOP_08_86,
1452 VEX_LEN_XOP_08_87,
1453 VEX_LEN_XOP_08_8E,
1454 VEX_LEN_XOP_08_8F,
1455 VEX_LEN_XOP_08_95,
1456 VEX_LEN_XOP_08_96,
1457 VEX_LEN_XOP_08_97,
1458 VEX_LEN_XOP_08_9E,
1459 VEX_LEN_XOP_08_9F,
1460 VEX_LEN_XOP_08_A3,
1461 VEX_LEN_XOP_08_A6,
1462 VEX_LEN_XOP_08_B6,
1463 VEX_LEN_XOP_08_C0,
1464 VEX_LEN_XOP_08_C1,
1465 VEX_LEN_XOP_08_C2,
1466 VEX_LEN_XOP_08_C3,
1467 VEX_LEN_XOP_08_CC,
1468 VEX_LEN_XOP_08_CD,
1469 VEX_LEN_XOP_08_CE,
1470 VEX_LEN_XOP_08_CF,
1471 VEX_LEN_XOP_08_EC,
1472 VEX_LEN_XOP_08_ED,
1473 VEX_LEN_XOP_08_EE,
1474 VEX_LEN_XOP_08_EF,
1475 VEX_LEN_XOP_09_01,
1476 VEX_LEN_XOP_09_02,
1477 VEX_LEN_XOP_09_12,
1478 VEX_LEN_XOP_09_82_W_0,
1479 VEX_LEN_XOP_09_83_W_0,
1480 VEX_LEN_XOP_09_90,
1481 VEX_LEN_XOP_09_91,
1482 VEX_LEN_XOP_09_92,
1483 VEX_LEN_XOP_09_93,
1484 VEX_LEN_XOP_09_94,
1485 VEX_LEN_XOP_09_95,
1486 VEX_LEN_XOP_09_96,
1487 VEX_LEN_XOP_09_97,
1488 VEX_LEN_XOP_09_98,
1489 VEX_LEN_XOP_09_99,
1490 VEX_LEN_XOP_09_9A,
1491 VEX_LEN_XOP_09_9B,
1492 VEX_LEN_XOP_09_C1,
1493 VEX_LEN_XOP_09_C2,
1494 VEX_LEN_XOP_09_C3,
1495 VEX_LEN_XOP_09_C6,
1496 VEX_LEN_XOP_09_C7,
1497 VEX_LEN_XOP_09_CB,
1498 VEX_LEN_XOP_09_D1,
1499 VEX_LEN_XOP_09_D2,
1500 VEX_LEN_XOP_09_D3,
1501 VEX_LEN_XOP_09_D6,
1502 VEX_LEN_XOP_09_D7,
1503 VEX_LEN_XOP_09_DB,
1504 VEX_LEN_XOP_09_E1,
1505 VEX_LEN_XOP_09_E2,
1506 VEX_LEN_XOP_09_E3,
1507 VEX_LEN_XOP_0A_12,
1508 };
1509
1510 enum
1511 {
1512 EVEX_LEN_0F3816 = 0,
1513 EVEX_LEN_0F3819,
1514 EVEX_LEN_0F381A,
1515 EVEX_LEN_0F381B,
1516 EVEX_LEN_0F3836,
1517 EVEX_LEN_0F385A,
1518 EVEX_LEN_0F385B,
1519 EVEX_LEN_0F38C6,
1520 EVEX_LEN_0F38C7,
1521 EVEX_LEN_0F3A00,
1522 EVEX_LEN_0F3A01,
1523 EVEX_LEN_0F3A18,
1524 EVEX_LEN_0F3A19,
1525 EVEX_LEN_0F3A1A,
1526 EVEX_LEN_0F3A1B,
1527 EVEX_LEN_0F3A23,
1528 EVEX_LEN_0F3A38,
1529 EVEX_LEN_0F3A39,
1530 EVEX_LEN_0F3A3A,
1531 EVEX_LEN_0F3A3B,
1532 EVEX_LEN_0F3A43
1533 };
1534
1535 enum
1536 {
1537 VEX_W_0F41_L_1 = 0,
1538 VEX_W_0F42_L_1,
1539 VEX_W_0F44_L_0,
1540 VEX_W_0F45_L_1,
1541 VEX_W_0F46_L_1,
1542 VEX_W_0F47_L_1,
1543 VEX_W_0F4A_L_1,
1544 VEX_W_0F4B_L_1,
1545 VEX_W_0F90_L_0,
1546 VEX_W_0F91_L_0,
1547 VEX_W_0F92_L_0,
1548 VEX_W_0F93_L_0,
1549 VEX_W_0F98_L_0,
1550 VEX_W_0F99_L_0,
1551 VEX_W_0F380C,
1552 VEX_W_0F380D,
1553 VEX_W_0F380E,
1554 VEX_W_0F380F,
1555 VEX_W_0F3813,
1556 VEX_W_0F3816_L_1,
1557 VEX_W_0F3818,
1558 VEX_W_0F3819_L_1,
1559 VEX_W_0F381A_L_1,
1560 VEX_W_0F382C,
1561 VEX_W_0F382D,
1562 VEX_W_0F382E,
1563 VEX_W_0F382F,
1564 VEX_W_0F3836,
1565 VEX_W_0F3846,
1566 VEX_W_0F3849_X86_64_L_0,
1567 VEX_W_0F384B_X86_64_L_0,
1568 VEX_W_0F3850,
1569 VEX_W_0F3851,
1570 VEX_W_0F3852,
1571 VEX_W_0F3853,
1572 VEX_W_0F3858,
1573 VEX_W_0F3859,
1574 VEX_W_0F385A_L_0,
1575 VEX_W_0F385C_X86_64_L_0,
1576 VEX_W_0F385E_X86_64_L_0,
1577 VEX_W_0F386C_X86_64_L_0,
1578 VEX_W_0F3872_P_1,
1579 VEX_W_0F3878,
1580 VEX_W_0F3879,
1581 VEX_W_0F38B0,
1582 VEX_W_0F38B1,
1583 VEX_W_0F38B4,
1584 VEX_W_0F38B5,
1585 VEX_W_0F38CB_P_3,
1586 VEX_W_0F38CC_P_3,
1587 VEX_W_0F38CD_P_3,
1588 VEX_W_0F38CF,
1589 VEX_W_0F38D2,
1590 VEX_W_0F38D3,
1591 VEX_W_0F38DA,
1592 VEX_W_0F3A00_L_1,
1593 VEX_W_0F3A01_L_1,
1594 VEX_W_0F3A02,
1595 VEX_W_0F3A04,
1596 VEX_W_0F3A05,
1597 VEX_W_0F3A06_L_1,
1598 VEX_W_0F3A18_L_1,
1599 VEX_W_0F3A19_L_1,
1600 VEX_W_0F3A1D,
1601 VEX_W_0F3A38_L_1,
1602 VEX_W_0F3A39_L_1,
1603 VEX_W_0F3A46_L_1,
1604 VEX_W_0F3A4A,
1605 VEX_W_0F3A4B,
1606 VEX_W_0F3A4C,
1607 VEX_W_0F3ACE,
1608 VEX_W_0F3ACF,
1609 VEX_W_0F3ADE,
1610 VEX_W_MAP7_F8_L_0,
1611
1612 VEX_W_XOP_08_85_L_0,
1613 VEX_W_XOP_08_86_L_0,
1614 VEX_W_XOP_08_87_L_0,
1615 VEX_W_XOP_08_8E_L_0,
1616 VEX_W_XOP_08_8F_L_0,
1617 VEX_W_XOP_08_95_L_0,
1618 VEX_W_XOP_08_96_L_0,
1619 VEX_W_XOP_08_97_L_0,
1620 VEX_W_XOP_08_9E_L_0,
1621 VEX_W_XOP_08_9F_L_0,
1622 VEX_W_XOP_08_A6_L_0,
1623 VEX_W_XOP_08_B6_L_0,
1624 VEX_W_XOP_08_C0_L_0,
1625 VEX_W_XOP_08_C1_L_0,
1626 VEX_W_XOP_08_C2_L_0,
1627 VEX_W_XOP_08_C3_L_0,
1628 VEX_W_XOP_08_CC_L_0,
1629 VEX_W_XOP_08_CD_L_0,
1630 VEX_W_XOP_08_CE_L_0,
1631 VEX_W_XOP_08_CF_L_0,
1632 VEX_W_XOP_08_EC_L_0,
1633 VEX_W_XOP_08_ED_L_0,
1634 VEX_W_XOP_08_EE_L_0,
1635 VEX_W_XOP_08_EF_L_0,
1636
1637 VEX_W_XOP_09_80,
1638 VEX_W_XOP_09_81,
1639 VEX_W_XOP_09_82,
1640 VEX_W_XOP_09_83,
1641 VEX_W_XOP_09_C1_L_0,
1642 VEX_W_XOP_09_C2_L_0,
1643 VEX_W_XOP_09_C3_L_0,
1644 VEX_W_XOP_09_C6_L_0,
1645 VEX_W_XOP_09_C7_L_0,
1646 VEX_W_XOP_09_CB_L_0,
1647 VEX_W_XOP_09_D1_L_0,
1648 VEX_W_XOP_09_D2_L_0,
1649 VEX_W_XOP_09_D3_L_0,
1650 VEX_W_XOP_09_D6_L_0,
1651 VEX_W_XOP_09_D7_L_0,
1652 VEX_W_XOP_09_DB_L_0,
1653 VEX_W_XOP_09_E1_L_0,
1654 VEX_W_XOP_09_E2_L_0,
1655 VEX_W_XOP_09_E3_L_0,
1656
1657 EVEX_W_0F5B_P_0,
1658 EVEX_W_0F62,
1659 EVEX_W_0F66,
1660 EVEX_W_0F6A,
1661 EVEX_W_0F6B,
1662 EVEX_W_0F6C,
1663 EVEX_W_0F6D,
1664 EVEX_W_0F6F_P_1,
1665 EVEX_W_0F6F_P_2,
1666 EVEX_W_0F6F_P_3,
1667 EVEX_W_0F70_P_2,
1668 EVEX_W_0F72_R_2,
1669 EVEX_W_0F72_R_6,
1670 EVEX_W_0F73_R_2,
1671 EVEX_W_0F73_R_6,
1672 EVEX_W_0F76,
1673 EVEX_W_0F78_P_0,
1674 EVEX_W_0F78_P_2,
1675 EVEX_W_0F79_P_0,
1676 EVEX_W_0F79_P_2,
1677 EVEX_W_0F7A_P_1,
1678 EVEX_W_0F7A_P_2,
1679 EVEX_W_0F7A_P_3,
1680 EVEX_W_0F7B_P_2,
1681 EVEX_W_0F7E_P_1,
1682 EVEX_W_0F7F_P_1,
1683 EVEX_W_0F7F_P_2,
1684 EVEX_W_0F7F_P_3,
1685 EVEX_W_0FD2,
1686 EVEX_W_0FD3,
1687 EVEX_W_0FD4,
1688 EVEX_W_0FD6,
1689 EVEX_W_0FE6_P_1,
1690 EVEX_W_0FE7,
1691 EVEX_W_0FF2,
1692 EVEX_W_0FF3,
1693 EVEX_W_0FF4,
1694 EVEX_W_0FFA,
1695 EVEX_W_0FFB,
1696 EVEX_W_0FFE,
1697
1698 EVEX_W_0F3810_P_1,
1699 EVEX_W_0F3810_P_2,
1700 EVEX_W_0F3811_P_1,
1701 EVEX_W_0F3811_P_2,
1702 EVEX_W_0F3812_P_1,
1703 EVEX_W_0F3812_P_2,
1704 EVEX_W_0F3813_P_1,
1705 EVEX_W_0F3814_P_1,
1706 EVEX_W_0F3815_P_1,
1707 EVEX_W_0F3819_L_n,
1708 EVEX_W_0F381A_L_n,
1709 EVEX_W_0F381B_L_2,
1710 EVEX_W_0F381E,
1711 EVEX_W_0F381F,
1712 EVEX_W_0F3820_P_1,
1713 EVEX_W_0F3821_P_1,
1714 EVEX_W_0F3822_P_1,
1715 EVEX_W_0F3823_P_1,
1716 EVEX_W_0F3824_P_1,
1717 EVEX_W_0F3825_P_1,
1718 EVEX_W_0F3825_P_2,
1719 EVEX_W_0F3828_P_2,
1720 EVEX_W_0F3829_P_2,
1721 EVEX_W_0F382A_P_1,
1722 EVEX_W_0F382A_P_2,
1723 EVEX_W_0F382B,
1724 EVEX_W_0F3830_P_1,
1725 EVEX_W_0F3831_P_1,
1726 EVEX_W_0F3832_P_1,
1727 EVEX_W_0F3833_P_1,
1728 EVEX_W_0F3834_P_1,
1729 EVEX_W_0F3835_P_1,
1730 EVEX_W_0F3835_P_2,
1731 EVEX_W_0F3837,
1732 EVEX_W_0F383A_P_1,
1733 EVEX_W_0F3859,
1734 EVEX_W_0F385A_L_n,
1735 EVEX_W_0F385B_L_2,
1736 EVEX_W_0F3870,
1737 EVEX_W_0F3872_P_2,
1738 EVEX_W_0F387A,
1739 EVEX_W_0F387B,
1740 EVEX_W_0F3883,
1741
1742 EVEX_W_0F3A18_L_n,
1743 EVEX_W_0F3A19_L_n,
1744 EVEX_W_0F3A1A_L_2,
1745 EVEX_W_0F3A1B_L_2,
1746 EVEX_W_0F3A21,
1747 EVEX_W_0F3A23_L_n,
1748 EVEX_W_0F3A38_L_n,
1749 EVEX_W_0F3A39_L_n,
1750 EVEX_W_0F3A3A_L_2,
1751 EVEX_W_0F3A3B_L_2,
1752 EVEX_W_0F3A42,
1753 EVEX_W_0F3A43_L_n,
1754 EVEX_W_0F3A70,
1755 EVEX_W_0F3A72,
1756
1757 EVEX_W_MAP4_8F_R_0,
1758 EVEX_W_MAP4_F8_P1_M_1,
1759 EVEX_W_MAP4_F8_P3_M_1,
1760 EVEX_W_MAP4_FF_R_6,
1761
1762 EVEX_W_MAP5_5B_P_0,
1763 EVEX_W_MAP5_7A_P_3,
1764 };
1765
1766 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1767
1768 struct dis386 {
1769 const char *name;
1770 struct
1771 {
1772 op_rtn rtn;
1773 int bytemode;
1774 } op[MAX_OPERANDS];
1775 unsigned int prefix_requirement;
1776 };
1777
1778 /* Upper case letters in the instruction names here are macros.
1779 'A' => print 'b' if no (suitable) register operand or suffix_always is true
1780 'B' => print 'b' if suffix_always is true
1781 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1782 size prefix
1783 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1784 suffix_always is true
1785 'E' => print 'e' if 32-bit form of jcxz
1786 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1787 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1788 'H' => print ",pt" or ",pn" branch hint
1789 'I' unused.
1790 'J' unused.
1791 'K' => print 'd' or 'q' if rex prefix is present.
1792 'L' => print 'l' or 'q' if suffix_always is true
1793 'M' => print 'r' if intel_mnemonic is false.
1794 'N' => print 'n' if instruction has no wait "prefix"
1795 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1796 'P' => behave as 'T' except with register operand outside of suffix_always
1797 mode
1798 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1799 suffix_always is true
1800 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1801 'S' => print 'w', 'l' or 'q' if suffix_always is true
1802 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1803 prefix or if suffix_always is true.
1804 'U' unused.
1805 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1806 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1807 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1808 'Y' => no output, mark EVEX.aaa != 0 as bad.
1809 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1810 '!' => change condition from true to false or from false to true.
1811 '%' => add 1 upper case letter to the macro.
1812 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1813 prefix or suffix_always is true (lcall/ljmp).
1814 '@' => in 64bit mode for Intel64 ISA or if instruction
1815 has no operand sizing prefix, print 'q' if suffix_always is true or
1816 nothing otherwise; behave as 'P' in all other cases
1817
1818 2 upper case letter macros:
1819 "XY" => print 'x' or 'y' if suffix_always is true or no register
1820 operands and no broadcast.
1821 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1822 register operands and no broadcast.
1823 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1824 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1825 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1826 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1827 "XV" => print "{vex} " pseudo prefix
1828 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1829 is used by an EVEX-encoded (AVX512VL) instruction.
1830 "ME" => print "{evex} " pseudo prefix for ins->modrm.mod != 3,if no
1831 EVEX-specific functionality is used by an EVEX-encoded (AVX512VL)
1832 instruction.
1833 "NF" => print "{nf} " pseudo prefix when EVEX.NF = 1 and print "{evex} "
1834 pseudo prefix when instructions without NF, EGPR and VVVV,
1835 "ZU" => print 'zu' if EVEX.ZU=1.
1836 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1837 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1838 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1839 being false, or no operand at all in 64bit mode, or if suffix_always
1840 is true.
1841 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1842 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1843 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1844 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1845 "BW" => print 'b' or 'w' depending on the VEX.W bit
1846 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1847 an operand size prefix, or suffix_always is true. print
1848 'q' if rex prefix is present.
1849
1850 Many of the above letters print nothing in Intel mode. See "putop"
1851 for the details.
1852
1853 Braces '{' and '}', and vertical bars '|', indicate alternative
1854 mnemonic strings for AT&T and Intel. */
1855
1856 static const struct dis386 dis386[] = {
1857 /* 00 */
1858 { "addB", { Ebh1, Gb }, 0 },
1859 { "addS", { Evh1, Gv }, 0 },
1860 { "addB", { Gb, EbS }, 0 },
1861 { "addS", { Gv, EvS }, 0 },
1862 { "addB", { AL, Ib }, 0 },
1863 { "addS", { eAX, Iv }, 0 },
1864 { X86_64_TABLE (X86_64_06) },
1865 { X86_64_TABLE (X86_64_07) },
1866 /* 08 */
1867 { "orB", { Ebh1, Gb }, 0 },
1868 { "orS", { Evh1, Gv }, 0 },
1869 { "orB", { Gb, EbS }, 0 },
1870 { "orS", { Gv, EvS }, 0 },
1871 { "orB", { AL, Ib }, 0 },
1872 { "orS", { eAX, Iv }, 0 },
1873 { X86_64_TABLE (X86_64_0E) },
1874 { Bad_Opcode }, /* 0x0f extended opcode escape */
1875 /* 10 */
1876 { "adcB", { Ebh1, Gb }, 0 },
1877 { "adcS", { Evh1, Gv }, 0 },
1878 { "adcB", { Gb, EbS }, 0 },
1879 { "adcS", { Gv, EvS }, 0 },
1880 { "adcB", { AL, Ib }, 0 },
1881 { "adcS", { eAX, Iv }, 0 },
1882 { X86_64_TABLE (X86_64_16) },
1883 { X86_64_TABLE (X86_64_17) },
1884 /* 18 */
1885 { "sbbB", { Ebh1, Gb }, 0 },
1886 { "sbbS", { Evh1, Gv }, 0 },
1887 { "sbbB", { Gb, EbS }, 0 },
1888 { "sbbS", { Gv, EvS }, 0 },
1889 { "sbbB", { AL, Ib }, 0 },
1890 { "sbbS", { eAX, Iv }, 0 },
1891 { X86_64_TABLE (X86_64_1E) },
1892 { X86_64_TABLE (X86_64_1F) },
1893 /* 20 */
1894 { "andB", { Ebh1, Gb }, 0 },
1895 { "andS", { Evh1, Gv }, 0 },
1896 { "andB", { Gb, EbS }, 0 },
1897 { "andS", { Gv, EvS }, 0 },
1898 { "andB", { AL, Ib }, 0 },
1899 { "andS", { eAX, Iv }, 0 },
1900 { Bad_Opcode }, /* SEG ES prefix */
1901 { X86_64_TABLE (X86_64_27) },
1902 /* 28 */
1903 { "subB", { Ebh1, Gb }, 0 },
1904 { "subS", { Evh1, Gv }, 0 },
1905 { "subB", { Gb, EbS }, 0 },
1906 { "subS", { Gv, EvS }, 0 },
1907 { "subB", { AL, Ib }, 0 },
1908 { "subS", { eAX, Iv }, 0 },
1909 { Bad_Opcode }, /* SEG CS prefix */
1910 { X86_64_TABLE (X86_64_2F) },
1911 /* 30 */
1912 { "xorB", { Ebh1, Gb }, 0 },
1913 { "xorS", { Evh1, Gv }, 0 },
1914 { "xorB", { Gb, EbS }, 0 },
1915 { "xorS", { Gv, EvS }, 0 },
1916 { "xorB", { AL, Ib }, 0 },
1917 { "xorS", { eAX, Iv }, 0 },
1918 { Bad_Opcode }, /* SEG SS prefix */
1919 { X86_64_TABLE (X86_64_37) },
1920 /* 38 */
1921 { "cmpB", { Eb, Gb }, 0 },
1922 { "cmpS", { Ev, Gv }, 0 },
1923 { "cmpB", { Gb, EbS }, 0 },
1924 { "cmpS", { Gv, EvS }, 0 },
1925 { "cmpB", { AL, Ib }, 0 },
1926 { "cmpS", { eAX, Iv }, 0 },
1927 { Bad_Opcode }, /* SEG DS prefix */
1928 { X86_64_TABLE (X86_64_3F) },
1929 /* 40 */
1930 { "inc{S|}", { RMeAX }, 0 },
1931 { "inc{S|}", { RMeCX }, 0 },
1932 { "inc{S|}", { RMeDX }, 0 },
1933 { "inc{S|}", { RMeBX }, 0 },
1934 { "inc{S|}", { RMeSP }, 0 },
1935 { "inc{S|}", { RMeBP }, 0 },
1936 { "inc{S|}", { RMeSI }, 0 },
1937 { "inc{S|}", { RMeDI }, 0 },
1938 /* 48 */
1939 { "dec{S|}", { RMeAX }, 0 },
1940 { "dec{S|}", { RMeCX }, 0 },
1941 { "dec{S|}", { RMeDX }, 0 },
1942 { "dec{S|}", { RMeBX }, 0 },
1943 { "dec{S|}", { RMeSP }, 0 },
1944 { "dec{S|}", { RMeBP }, 0 },
1945 { "dec{S|}", { RMeSI }, 0 },
1946 { "dec{S|}", { RMeDI }, 0 },
1947 /* 50 */
1948 { "push!P", { RMrAX }, 0 },
1949 { "push!P", { RMrCX }, 0 },
1950 { "push!P", { RMrDX }, 0 },
1951 { "push!P", { RMrBX }, 0 },
1952 { "push!P", { RMrSP }, 0 },
1953 { "push!P", { RMrBP }, 0 },
1954 { "push!P", { RMrSI }, 0 },
1955 { "push!P", { RMrDI }, 0 },
1956 /* 58 */
1957 { "pop!P", { RMrAX }, 0 },
1958 { "pop!P", { RMrCX }, 0 },
1959 { "pop!P", { RMrDX }, 0 },
1960 { "pop!P", { RMrBX }, 0 },
1961 { "pop!P", { RMrSP }, 0 },
1962 { "pop!P", { RMrBP }, 0 },
1963 { "pop!P", { RMrSI }, 0 },
1964 { "pop!P", { RMrDI }, 0 },
1965 /* 60 */
1966 { X86_64_TABLE (X86_64_60) },
1967 { X86_64_TABLE (X86_64_61) },
1968 { X86_64_TABLE (X86_64_62) },
1969 { X86_64_TABLE (X86_64_63) },
1970 { Bad_Opcode }, /* seg fs */
1971 { Bad_Opcode }, /* seg gs */
1972 { Bad_Opcode }, /* op size prefix */
1973 { Bad_Opcode }, /* adr size prefix */
1974 /* 68 */
1975 { "pushP", { sIv }, 0 },
1976 { "imulS", { Gv, Ev, Iv }, 0 },
1977 { "pushP", { sIbT }, 0 },
1978 { "imulS", { Gv, Ev, sIb }, 0 },
1979 { "ins{b|}", { Ybr, indirDX }, 0 },
1980 { X86_64_TABLE (X86_64_6D) },
1981 { "outs{b|}", { indirDXr, Xb }, 0 },
1982 { X86_64_TABLE (X86_64_6F) },
1983 /* 70 */
1984 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1985 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1986 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1987 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1988 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1989 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1990 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1991 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1992 /* 78 */
1993 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1994 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1995 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1996 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1997 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1998 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1999 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2000 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2001 /* 80 */
2002 { REG_TABLE (REG_80) },
2003 { REG_TABLE (REG_81) },
2004 { X86_64_TABLE (X86_64_82) },
2005 { REG_TABLE (REG_83) },
2006 { "testB", { Eb, Gb }, 0 },
2007 { "testS", { Ev, Gv }, 0 },
2008 { "xchgB", { Ebh2, Gb }, 0 },
2009 { "xchgS", { Evh2, Gv }, 0 },
2010 /* 88 */
2011 { "movB", { Ebh3, Gb }, 0 },
2012 { "movS", { Evh3, Gv }, 0 },
2013 { "movB", { Gb, EbS }, 0 },
2014 { "movS", { Gv, EvS }, 0 },
2015 { "movD", { Sv, Sw }, 0 },
2016 { "leaS", { Gv, M }, 0 },
2017 { "movD", { Sw, Sv }, 0 },
2018 { REG_TABLE (REG_8F) },
2019 /* 90 */
2020 { PREFIX_TABLE (PREFIX_90) },
2021 { "xchgS", { RMeCX, eAX }, 0 },
2022 { "xchgS", { RMeDX, eAX }, 0 },
2023 { "xchgS", { RMeBX, eAX }, 0 },
2024 { "xchgS", { RMeSP, eAX }, 0 },
2025 { "xchgS", { RMeBP, eAX }, 0 },
2026 { "xchgS", { RMeSI, eAX }, 0 },
2027 { "xchgS", { RMeDI, eAX }, 0 },
2028 /* 98 */
2029 { "cW{t|}R", { XX }, 0 },
2030 { "cR{t|}O", { XX }, 0 },
2031 { X86_64_TABLE (X86_64_9A) },
2032 { Bad_Opcode }, /* fwait */
2033 { "pushfP", { XX }, 0 },
2034 { "popfP", { XX }, 0 },
2035 { "sahf", { XX }, 0 },
2036 { "lahf", { XX }, 0 },
2037 /* a0 */
2038 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL },
2039 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2040 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL },
2041 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2042 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2043 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2044 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2045 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2046 /* a8 */
2047 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2048 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2049 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2050 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2051 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2052 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2053 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL },
2054 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2055 /* b0 */
2056 { "movB", { RMAL, Ib }, 0 },
2057 { "movB", { RMCL, Ib }, 0 },
2058 { "movB", { RMDL, Ib }, 0 },
2059 { "movB", { RMBL, Ib }, 0 },
2060 { "movB", { RMAH, Ib }, 0 },
2061 { "movB", { RMCH, Ib }, 0 },
2062 { "movB", { RMDH, Ib }, 0 },
2063 { "movB", { RMBH, Ib }, 0 },
2064 /* b8 */
2065 { "mov%LV", { RMeAX, Iv64 }, 0 },
2066 { "mov%LV", { RMeCX, Iv64 }, 0 },
2067 { "mov%LV", { RMeDX, Iv64 }, 0 },
2068 { "mov%LV", { RMeBX, Iv64 }, 0 },
2069 { "mov%LV", { RMeSP, Iv64 }, 0 },
2070 { "mov%LV", { RMeBP, Iv64 }, 0 },
2071 { "mov%LV", { RMeSI, Iv64 }, 0 },
2072 { "mov%LV", { RMeDI, Iv64 }, 0 },
2073 /* c0 */
2074 { REG_TABLE (REG_C0) },
2075 { REG_TABLE (REG_C1) },
2076 { X86_64_TABLE (X86_64_C2) },
2077 { X86_64_TABLE (X86_64_C3) },
2078 { X86_64_TABLE (X86_64_C4) },
2079 { X86_64_TABLE (X86_64_C5) },
2080 { REG_TABLE (REG_C6) },
2081 { REG_TABLE (REG_C7) },
2082 /* c8 */
2083 { "enterP", { Iw, Ib }, 0 },
2084 { "leaveP", { XX }, 0 },
2085 { "{l|}ret{|f}%LP", { Iw }, 0 },
2086 { "{l|}ret{|f}%LP", { XX }, 0 },
2087 { "int3", { XX }, 0 },
2088 { "int", { Ib }, 0 },
2089 { X86_64_TABLE (X86_64_CE) },
2090 { "iret%LP", { XX }, 0 },
2091 /* d0 */
2092 { REG_TABLE (REG_D0) },
2093 { REG_TABLE (REG_D1) },
2094 { REG_TABLE (REG_D2) },
2095 { REG_TABLE (REG_D3) },
2096 { X86_64_TABLE (X86_64_D4) },
2097 { X86_64_TABLE (X86_64_D5) },
2098 { Bad_Opcode },
2099 { "xlat", { DSBX }, 0 },
2100 /* d8 */
2101 { FLOAT },
2102 { FLOAT },
2103 { FLOAT },
2104 { FLOAT },
2105 { FLOAT },
2106 { FLOAT },
2107 { FLOAT },
2108 { FLOAT },
2109 /* e0 */
2110 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2111 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2112 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2113 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2114 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2115 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2116 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL },
2117 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2118 /* e8 */
2119 { X86_64_TABLE (X86_64_E8) },
2120 { X86_64_TABLE (X86_64_E9) },
2121 { X86_64_TABLE (X86_64_EA) },
2122 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL },
2123 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2124 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2125 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2126 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2127 /* f0 */
2128 { Bad_Opcode }, /* lock prefix */
2129 { "int1", { XX }, 0 },
2130 { Bad_Opcode }, /* repne */
2131 { Bad_Opcode }, /* repz */
2132 { "hlt", { XX }, 0 },
2133 { "cmc", { XX }, 0 },
2134 { REG_TABLE (REG_F6) },
2135 { REG_TABLE (REG_F7) },
2136 /* f8 */
2137 { "clc", { XX }, 0 },
2138 { "stc", { XX }, 0 },
2139 { "cli", { XX }, 0 },
2140 { "sti", { XX }, 0 },
2141 { "cld", { XX }, 0 },
2142 { "std", { XX }, 0 },
2143 { REG_TABLE (REG_FE) },
2144 { REG_TABLE (REG_FF) },
2145 };
2146
2147 static const struct dis386 dis386_twobyte[] = {
2148 /* 00 */
2149 { REG_TABLE (REG_0F00 ) },
2150 { REG_TABLE (REG_0F01 ) },
2151 { "larS", { Gv, Sv }, 0 },
2152 { "lslS", { Gv, Sv }, 0 },
2153 { Bad_Opcode },
2154 { "syscall", { XX }, 0 },
2155 { "clts", { XX }, 0 },
2156 { "sysret%LQ", { XX }, 0 },
2157 /* 08 */
2158 { "invd", { XX }, 0 },
2159 { PREFIX_TABLE (PREFIX_0F09) },
2160 { Bad_Opcode },
2161 { "ud2", { XX }, 0 },
2162 { Bad_Opcode },
2163 { REG_TABLE (REG_0F0D) },
2164 { "femms", { XX }, 0 },
2165 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2166 /* 10 */
2167 { PREFIX_TABLE (PREFIX_0F10) },
2168 { PREFIX_TABLE (PREFIX_0F11) },
2169 { PREFIX_TABLE (PREFIX_0F12) },
2170 { "movlpX", { Mq, XM }, PREFIX_OPCODE },
2171 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2172 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2173 { PREFIX_TABLE (PREFIX_0F16) },
2174 { "movhpX", { Mq, XM }, PREFIX_OPCODE },
2175 /* 18 */
2176 { REG_TABLE (REG_0F18) },
2177 { "nopQ", { Ev }, 0 },
2178 { PREFIX_TABLE (PREFIX_0F1A) },
2179 { PREFIX_TABLE (PREFIX_0F1B) },
2180 { PREFIX_TABLE (PREFIX_0F1C) },
2181 { "nopQ", { Ev }, 0 },
2182 { PREFIX_TABLE (PREFIX_0F1E) },
2183 { "nopQ", { Ev }, 0 },
2184 /* 20 */
2185 { "movZ", { Em, Cm }, 0 },
2186 { "movZ", { Em, Dm }, 0 },
2187 { "movZ", { Cm, Em }, 0 },
2188 { "movZ", { Dm, Em }, 0 },
2189 { X86_64_TABLE (X86_64_0F24) },
2190 { Bad_Opcode },
2191 { X86_64_TABLE (X86_64_0F26) },
2192 { Bad_Opcode },
2193 /* 28 */
2194 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2195 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2196 { PREFIX_TABLE (PREFIX_0F2A) },
2197 { PREFIX_TABLE (PREFIX_0F2B) },
2198 { PREFIX_TABLE (PREFIX_0F2C) },
2199 { PREFIX_TABLE (PREFIX_0F2D) },
2200 { PREFIX_TABLE (PREFIX_0F2E) },
2201 { PREFIX_TABLE (PREFIX_0F2F) },
2202 /* 30 */
2203 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL },
2204 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL },
2205 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL },
2206 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL },
2207 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL },
2208 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2209 { Bad_Opcode },
2210 { "getsec", { XX }, 0 },
2211 /* 38 */
2212 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2213 { Bad_Opcode },
2214 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2215 { Bad_Opcode },
2216 { Bad_Opcode },
2217 { Bad_Opcode },
2218 { Bad_Opcode },
2219 { Bad_Opcode },
2220 /* 40 */
2221 { "cmovoS", { Gv, Ev }, 0 },
2222 { "cmovnoS", { Gv, Ev }, 0 },
2223 { "cmovbS", { Gv, Ev }, 0 },
2224 { "cmovaeS", { Gv, Ev }, 0 },
2225 { "cmoveS", { Gv, Ev }, 0 },
2226 { "cmovneS", { Gv, Ev }, 0 },
2227 { "cmovbeS", { Gv, Ev }, 0 },
2228 { "cmovaS", { Gv, Ev }, 0 },
2229 /* 48 */
2230 { "cmovsS", { Gv, Ev }, 0 },
2231 { "cmovnsS", { Gv, Ev }, 0 },
2232 { "cmovpS", { Gv, Ev }, 0 },
2233 { "cmovnpS", { Gv, Ev }, 0 },
2234 { "cmovlS", { Gv, Ev }, 0 },
2235 { "cmovgeS", { Gv, Ev }, 0 },
2236 { "cmovleS", { Gv, Ev }, 0 },
2237 { "cmovgS", { Gv, Ev }, 0 },
2238 /* 50 */
2239 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE },
2240 { PREFIX_TABLE (PREFIX_0F51) },
2241 { PREFIX_TABLE (PREFIX_0F52) },
2242 { PREFIX_TABLE (PREFIX_0F53) },
2243 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2244 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2245 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2246 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2247 /* 58 */
2248 { PREFIX_TABLE (PREFIX_0F58) },
2249 { PREFIX_TABLE (PREFIX_0F59) },
2250 { PREFIX_TABLE (PREFIX_0F5A) },
2251 { PREFIX_TABLE (PREFIX_0F5B) },
2252 { PREFIX_TABLE (PREFIX_0F5C) },
2253 { PREFIX_TABLE (PREFIX_0F5D) },
2254 { PREFIX_TABLE (PREFIX_0F5E) },
2255 { PREFIX_TABLE (PREFIX_0F5F) },
2256 /* 60 */
2257 { PREFIX_TABLE (PREFIX_0F60) },
2258 { PREFIX_TABLE (PREFIX_0F61) },
2259 { PREFIX_TABLE (PREFIX_0F62) },
2260 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2261 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2262 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2263 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2264 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2265 /* 68 */
2266 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2267 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2268 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2269 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2270 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2271 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2272 { "movK", { MX, Edq }, PREFIX_OPCODE },
2273 { PREFIX_TABLE (PREFIX_0F6F) },
2274 /* 70 */
2275 { PREFIX_TABLE (PREFIX_0F70) },
2276 { REG_TABLE (REG_0F71) },
2277 { REG_TABLE (REG_0F72) },
2278 { REG_TABLE (REG_0F73) },
2279 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2280 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2281 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2282 { "emms", { XX }, PREFIX_OPCODE },
2283 /* 78 */
2284 { PREFIX_TABLE (PREFIX_0F78) },
2285 { PREFIX_TABLE (PREFIX_0F79) },
2286 { Bad_Opcode },
2287 { Bad_Opcode },
2288 { PREFIX_TABLE (PREFIX_0F7C) },
2289 { PREFIX_TABLE (PREFIX_0F7D) },
2290 { PREFIX_TABLE (PREFIX_0F7E) },
2291 { PREFIX_TABLE (PREFIX_0F7F) },
2292 /* 80 */
2293 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2294 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2295 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2296 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2297 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2298 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2299 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2300 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2301 /* 88 */
2302 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2303 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2304 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2305 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2306 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2307 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2308 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2309 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2310 /* 90 */
2311 { "seto", { Eb }, 0 },
2312 { "setno", { Eb }, 0 },
2313 { "setb", { Eb }, 0 },
2314 { "setae", { Eb }, 0 },
2315 { "sete", { Eb }, 0 },
2316 { "setne", { Eb }, 0 },
2317 { "setbe", { Eb }, 0 },
2318 { "seta", { Eb }, 0 },
2319 /* 98 */
2320 { "sets", { Eb }, 0 },
2321 { "setns", { Eb }, 0 },
2322 { "setp", { Eb }, 0 },
2323 { "setnp", { Eb }, 0 },
2324 { "setl", { Eb }, 0 },
2325 { "setge", { Eb }, 0 },
2326 { "setle", { Eb }, 0 },
2327 { "setg", { Eb }, 0 },
2328 /* a0 */
2329 { "pushP", { fs }, 0 },
2330 { "popP", { fs }, 0 },
2331 { "cpuid", { XX }, 0 },
2332 { "btS", { Ev, Gv }, 0 },
2333 { "shldS", { Ev, Gv, Ib }, 0 },
2334 { "shldS", { Ev, Gv, CL }, 0 },
2335 { REG_TABLE (REG_0FA6) },
2336 { REG_TABLE (REG_0FA7) },
2337 /* a8 */
2338 { "pushP", { gs }, 0 },
2339 { "popP", { gs }, 0 },
2340 { "rsm", { XX }, 0 },
2341 { "btsS", { Evh1, Gv }, 0 },
2342 { "shrdS", { Ev, Gv, Ib }, 0 },
2343 { "shrdS", { Ev, Gv, CL }, 0 },
2344 { REG_TABLE (REG_0FAE) },
2345 { "imulS", { Gv, Ev }, 0 },
2346 /* b0 */
2347 { "cmpxchgB", { Ebh1, Gb }, 0 },
2348 { "cmpxchgS", { Evh1, Gv }, 0 },
2349 { "lssS", { Gv, Mp }, 0 },
2350 { "btrS", { Evh1, Gv }, 0 },
2351 { "lfsS", { Gv, Mp }, 0 },
2352 { "lgsS", { Gv, Mp }, 0 },
2353 { "movz{bR|x}", { Gv, Eb }, 0 },
2354 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2355 /* b8 */
2356 { PREFIX_TABLE (PREFIX_0FB8) },
2357 { "ud1S", { Gv, Ev }, 0 },
2358 { REG_TABLE (REG_0FBA) },
2359 { "btcS", { Evh1, Gv }, 0 },
2360 { PREFIX_TABLE (PREFIX_0FBC) },
2361 { PREFIX_TABLE (PREFIX_0FBD) },
2362 { "movs{bR|x}", { Gv, Eb }, 0 },
2363 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2364 /* c0 */
2365 { "xaddB", { Ebh1, Gb }, 0 },
2366 { "xaddS", { Evh1, Gv }, 0 },
2367 { PREFIX_TABLE (PREFIX_0FC2) },
2368 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE },
2369 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2370 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE },
2371 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2372 { REG_TABLE (REG_0FC7) },
2373 /* c8 */
2374 { "bswap", { RMeAX }, 0 },
2375 { "bswap", { RMeCX }, 0 },
2376 { "bswap", { RMeDX }, 0 },
2377 { "bswap", { RMeBX }, 0 },
2378 { "bswap", { RMeSP }, 0 },
2379 { "bswap", { RMeBP }, 0 },
2380 { "bswap", { RMeSI }, 0 },
2381 { "bswap", { RMeDI }, 0 },
2382 /* d0 */
2383 { PREFIX_TABLE (PREFIX_0FD0) },
2384 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2385 { "psrld", { MX, EM }, PREFIX_OPCODE },
2386 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2387 { "paddq", { MX, EM }, PREFIX_OPCODE },
2388 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2389 { PREFIX_TABLE (PREFIX_0FD6) },
2390 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE },
2391 /* d8 */
2392 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2393 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2394 { "pminub", { MX, EM }, PREFIX_OPCODE },
2395 { "pand", { MX, EM }, PREFIX_OPCODE },
2396 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2397 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2398 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2399 { "pandn", { MX, EM }, PREFIX_OPCODE },
2400 /* e0 */
2401 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2402 { "psraw", { MX, EM }, PREFIX_OPCODE },
2403 { "psrad", { MX, EM }, PREFIX_OPCODE },
2404 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2405 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2406 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2407 { PREFIX_TABLE (PREFIX_0FE6) },
2408 { PREFIX_TABLE (PREFIX_0FE7) },
2409 /* e8 */
2410 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2411 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2412 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2413 { "por", { MX, EM }, PREFIX_OPCODE },
2414 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2415 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2416 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2417 { "pxor", { MX, EM }, PREFIX_OPCODE },
2418 /* f0 */
2419 { PREFIX_TABLE (PREFIX_0FF0) },
2420 { "psllw", { MX, EM }, PREFIX_OPCODE },
2421 { "pslld", { MX, EM }, PREFIX_OPCODE },
2422 { "psllq", { MX, EM }, PREFIX_OPCODE },
2423 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2424 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2425 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2426 { PREFIX_TABLE (PREFIX_0FF7) },
2427 /* f8 */
2428 { "psubb", { MX, EM }, PREFIX_OPCODE },
2429 { "psubw", { MX, EM }, PREFIX_OPCODE },
2430 { "psubd", { MX, EM }, PREFIX_OPCODE },
2431 { "psubq", { MX, EM }, PREFIX_OPCODE },
2432 { "paddb", { MX, EM }, PREFIX_OPCODE },
2433 { "paddw", { MX, EM }, PREFIX_OPCODE },
2434 { "paddd", { MX, EM }, PREFIX_OPCODE },
2435 { "ud0S", { Gv, Ev }, 0 },
2436 };
2437
2438 static const bool onebyte_has_modrm[256] = {
2439 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2440 /* ------------------------------- */
2441 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2442 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2443 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2444 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2445 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2446 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2447 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2448 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2449 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2450 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2451 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2452 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2453 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2454 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2455 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2456 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2457 /* ------------------------------- */
2458 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2459 };
2460
2461 static const bool twobyte_has_modrm[256] = {
2462 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2463 /* ------------------------------- */
2464 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2465 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2466 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2467 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2468 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2469 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2470 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2471 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2472 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2473 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2474 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2475 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2476 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2477 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2478 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2479 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2480 /* ------------------------------- */
2481 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2482 };
2483
2484
2485 struct op
2486 {
2487 const char *name;
2488 unsigned int len;
2489 };
2490
2491 /* If we are accessing mod/rm/reg without need_modrm set, then the
2492 values are stale. Hitting this abort likely indicates that you
2493 need to update onebyte_has_modrm or twobyte_has_modrm. */
2494 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2495
2496 static const char intel_index16[][6] = {
2497 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2498 };
2499
2500 static const char att_names64[][8] = {
2501 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2502 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2503 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2504 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2505 };
2506 static const char att_names32[][8] = {
2507 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2508 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2509 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2510 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2511 };
2512 static const char att_names16[][8] = {
2513 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2514 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2515 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2516 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2517 };
2518 static const char att_names8[][8] = {
2519 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2520 };
2521 static const char att_names8rex[][8] = {
2522 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2523 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2524 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2525 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2526 };
2527 static const char att_names_seg[][4] = {
2528 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2529 };
2530 static const char att_index64[] = "%riz";
2531 static const char att_index32[] = "%eiz";
2532 static const char att_index16[][8] = {
2533 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2534 };
2535
2536 static const char att_names_mm[][8] = {
2537 "%mm0", "%mm1", "%mm2", "%mm3",
2538 "%mm4", "%mm5", "%mm6", "%mm7"
2539 };
2540
2541 static const char att_names_bnd[][8] = {
2542 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2543 };
2544
2545 static const char att_names_xmm[][8] = {
2546 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2547 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2548 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2549 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2550 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2551 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2552 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2553 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2554 };
2555
2556 static const char att_names_ymm[][8] = {
2557 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2558 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2559 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2560 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2561 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2562 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2563 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2564 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2565 };
2566
2567 static const char att_names_zmm[][8] = {
2568 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2569 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2570 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2571 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2572 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2573 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2574 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2575 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2576 };
2577
2578 static const char att_names_tmm[][8] = {
2579 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2580 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2581 };
2582
2583 static const char att_names_mask[][8] = {
2584 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2585 };
2586
2587 static const char *const names_rounding[] =
2588 {
2589 "{rn-",
2590 "{rd-",
2591 "{ru-",
2592 "{rz-"
2593 };
2594
2595 static const struct dis386 reg_table[][8] = {
2596 /* REG_80 */
2597 {
2598 { "addA", { Ebh1, Ib }, 0 },
2599 { "orA", { Ebh1, Ib }, 0 },
2600 { "adcA", { Ebh1, Ib }, 0 },
2601 { "sbbA", { Ebh1, Ib }, 0 },
2602 { "andA", { Ebh1, Ib }, 0 },
2603 { "subA", { Ebh1, Ib }, 0 },
2604 { "xorA", { Ebh1, Ib }, 0 },
2605 { "cmpA", { Eb, Ib }, 0 },
2606 },
2607 /* REG_81 */
2608 {
2609 { "addQ", { Evh1, Iv }, 0 },
2610 { "orQ", { Evh1, Iv }, 0 },
2611 { "adcQ", { Evh1, Iv }, 0 },
2612 { "sbbQ", { Evh1, Iv }, 0 },
2613 { "andQ", { Evh1, Iv }, 0 },
2614 { "subQ", { Evh1, Iv }, 0 },
2615 { "xorQ", { Evh1, Iv }, 0 },
2616 { "cmpQ", { Ev, Iv }, 0 },
2617 },
2618 /* REG_83 */
2619 {
2620 { "addQ", { Evh1, sIb }, 0 },
2621 { "orQ", { Evh1, sIb }, 0 },
2622 { "adcQ", { Evh1, sIb }, 0 },
2623 { "sbbQ", { Evh1, sIb }, 0 },
2624 { "andQ", { Evh1, sIb }, 0 },
2625 { "subQ", { Evh1, sIb }, 0 },
2626 { "xorQ", { Evh1, sIb }, 0 },
2627 { "cmpQ", { Ev, sIb }, 0 },
2628 },
2629 /* REG_8F */
2630 {
2631 { "pop{P|}", { stackEv }, 0 },
2632 { XOP_8F_TABLE () },
2633 { Bad_Opcode },
2634 { Bad_Opcode },
2635 { Bad_Opcode },
2636 { XOP_8F_TABLE () },
2637 },
2638 /* REG_C0 */
2639 {
2640 { "%NFrolA", { VexGb, Eb, Ib }, NO_PREFIX },
2641 { "%NFrorA", { VexGb, Eb, Ib }, NO_PREFIX },
2642 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2643 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2644 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2645 { "%NFshrA", { VexGb, Eb, Ib }, NO_PREFIX },
2646 { "%NFshlA", { VexGb, Eb, Ib }, NO_PREFIX },
2647 { "%NFsarA", { VexGb, Eb, Ib }, NO_PREFIX },
2648 },
2649 /* REG_C1 */
2650 {
2651 { "%NFrolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2652 { "%NFrorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2653 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2654 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2655 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2656 { "%NFshrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2657 { "%NFshlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2658 { "%NFsarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2659 },
2660 /* REG_C6 */
2661 {
2662 { "movA", { Ebh3, Ib }, 0 },
2663 { Bad_Opcode },
2664 { Bad_Opcode },
2665 { Bad_Opcode },
2666 { Bad_Opcode },
2667 { Bad_Opcode },
2668 { Bad_Opcode },
2669 { RM_TABLE (RM_C6_REG_7) },
2670 },
2671 /* REG_C7 */
2672 {
2673 { "movQ", { Evh3, Iv }, 0 },
2674 { Bad_Opcode },
2675 { Bad_Opcode },
2676 { Bad_Opcode },
2677 { Bad_Opcode },
2678 { Bad_Opcode },
2679 { Bad_Opcode },
2680 { RM_TABLE (RM_C7_REG_7) },
2681 },
2682 /* REG_D0 */
2683 {
2684 { "%NFrolA", { VexGb, Eb, I1 }, NO_PREFIX },
2685 { "%NFrorA", { VexGb, Eb, I1 }, NO_PREFIX },
2686 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2687 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2688 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2689 { "%NFshrA", { VexGb, Eb, I1 }, NO_PREFIX },
2690 { "%NFshlA", { VexGb, Eb, I1 }, NO_PREFIX },
2691 { "%NFsarA", { VexGb, Eb, I1 }, NO_PREFIX },
2692 },
2693 /* REG_D1 */
2694 {
2695 { "%NFrolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2696 { "%NFrorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2697 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2698 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2699 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2700 { "%NFshrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2701 { "%NFshlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2702 { "%NFsarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2703 },
2704 /* REG_D2 */
2705 {
2706 { "%NFrolA", { VexGb, Eb, CL }, NO_PREFIX },
2707 { "%NFrorA", { VexGb, Eb, CL }, NO_PREFIX },
2708 { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2709 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2710 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2711 { "%NFshrA", { VexGb, Eb, CL }, NO_PREFIX },
2712 { "%NFshlA", { VexGb, Eb, CL }, NO_PREFIX },
2713 { "%NFsarA", { VexGb, Eb, CL }, NO_PREFIX },
2714 },
2715 /* REG_D3 */
2716 {
2717 { "%NFrolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2718 { "%NFrorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2719 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2720 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2721 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2722 { "%NFshrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2723 { "%NFshlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2724 { "%NFsarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2725 },
2726 /* REG_F6 */
2727 {
2728 { "testA", { Eb, Ib }, 0 },
2729 { "testA", { Eb, Ib }, 0 },
2730 { "notA", { Ebh1 }, 0 },
2731 { "negA", { Ebh1 }, 0 },
2732 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2733 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2734 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2735 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2736 },
2737 /* REG_F7 */
2738 {
2739 { "testQ", { Ev, Iv }, 0 },
2740 { "testQ", { Ev, Iv }, 0 },
2741 { "notQ", { Evh1 }, 0 },
2742 { "negQ", { Evh1 }, 0 },
2743 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2744 { "imulQ", { Ev }, 0 },
2745 { "divQ", { Ev }, 0 },
2746 { "idivQ", { Ev }, 0 },
2747 },
2748 /* REG_FE */
2749 {
2750 { "incA", { Ebh1 }, 0 },
2751 { "decA", { Ebh1 }, 0 },
2752 },
2753 /* REG_FF */
2754 {
2755 { "incQ", { Evh1 }, 0 },
2756 { "decQ", { Evh1 }, 0 },
2757 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2758 { "{l|}call^", { indirEp }, 0 },
2759 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2760 { "{l|}jmp^", { indirEp }, 0 },
2761 { "push{P|}", { stackEv }, 0 },
2762 { Bad_Opcode },
2763 },
2764 /* REG_0F00 */
2765 {
2766 { "sldtD", { Sv }, 0 },
2767 { "strD", { Sv }, 0 },
2768 { "lldtD", { Sv }, 0 },
2769 { "ltrD", { Sv }, 0 },
2770 { "verrD", { Sv }, 0 },
2771 { "verwD", { Sv }, 0 },
2772 { X86_64_TABLE (X86_64_0F00_REG_6) },
2773 { Bad_Opcode },
2774 },
2775 /* REG_0F01 */
2776 {
2777 { MOD_TABLE (MOD_0F01_REG_0) },
2778 { MOD_TABLE (MOD_0F01_REG_1) },
2779 { MOD_TABLE (MOD_0F01_REG_2) },
2780 { MOD_TABLE (MOD_0F01_REG_3) },
2781 { "smswD", { Sv }, 0 },
2782 { MOD_TABLE (MOD_0F01_REG_5) },
2783 { "lmsw", { Ew }, 0 },
2784 { MOD_TABLE (MOD_0F01_REG_7) },
2785 },
2786 /* REG_0F0D */
2787 {
2788 { "prefetch", { Mb }, 0 },
2789 { "prefetchw", { Mb }, 0 },
2790 { "prefetchwt1", { Mb }, 0 },
2791 { "prefetch", { Mb }, 0 },
2792 { "prefetch", { Mb }, 0 },
2793 { "prefetch", { Mb }, 0 },
2794 { "prefetch", { Mb }, 0 },
2795 { "prefetch", { Mb }, 0 },
2796 },
2797 /* REG_0F18 */
2798 {
2799 { MOD_TABLE (MOD_0F18_REG_0) },
2800 { MOD_TABLE (MOD_0F18_REG_1) },
2801 { MOD_TABLE (MOD_0F18_REG_2) },
2802 { MOD_TABLE (MOD_0F18_REG_3) },
2803 { "nopQ", { Ev }, 0 },
2804 { "nopQ", { Ev }, 0 },
2805 { MOD_TABLE (MOD_0F18_REG_6) },
2806 { MOD_TABLE (MOD_0F18_REG_7) },
2807 },
2808 /* REG_0F1C_P_0_MOD_0 */
2809 {
2810 { "cldemote", { Mb }, 0 },
2811 { "nopQ", { Ev }, 0 },
2812 { "nopQ", { Ev }, 0 },
2813 { "nopQ", { Ev }, 0 },
2814 { "nopQ", { Ev }, 0 },
2815 { "nopQ", { Ev }, 0 },
2816 { "nopQ", { Ev }, 0 },
2817 { "nopQ", { Ev }, 0 },
2818 },
2819 /* REG_0F1E_P_1_MOD_3 */
2820 {
2821 { "nopQ", { Ev }, PREFIX_IGNORED },
2822 { "rdsspK", { Edq }, 0 },
2823 { "nopQ", { Ev }, PREFIX_IGNORED },
2824 { "nopQ", { Ev }, PREFIX_IGNORED },
2825 { "nopQ", { Ev }, PREFIX_IGNORED },
2826 { "nopQ", { Ev }, PREFIX_IGNORED },
2827 { "nopQ", { Ev }, PREFIX_IGNORED },
2828 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2829 },
2830 /* REG_0F38D8_PREFIX_1 */
2831 {
2832 { "aesencwide128kl", { M }, 0 },
2833 { "aesdecwide128kl", { M }, 0 },
2834 { "aesencwide256kl", { M }, 0 },
2835 { "aesdecwide256kl", { M }, 0 },
2836 },
2837 /* REG_0F3A0F_P_1 */
2838 {
2839 { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2840 },
2841 /* REG_0F71 */
2842 {
2843 { Bad_Opcode },
2844 { Bad_Opcode },
2845 { "psrlw", { Nq, Ib }, PREFIX_OPCODE },
2846 { Bad_Opcode },
2847 { "psraw", { Nq, Ib }, PREFIX_OPCODE },
2848 { Bad_Opcode },
2849 { "psllw", { Nq, Ib }, PREFIX_OPCODE },
2850 },
2851 /* REG_0F72 */
2852 {
2853 { Bad_Opcode },
2854 { Bad_Opcode },
2855 { "psrld", { Nq, Ib }, PREFIX_OPCODE },
2856 { Bad_Opcode },
2857 { "psrad", { Nq, Ib }, PREFIX_OPCODE },
2858 { Bad_Opcode },
2859 { "pslld", { Nq, Ib }, PREFIX_OPCODE },
2860 },
2861 /* REG_0F73 */
2862 {
2863 { Bad_Opcode },
2864 { Bad_Opcode },
2865 { "psrlq", { Nq, Ib }, PREFIX_OPCODE },
2866 { "psrldq", { Ux, Ib }, PREFIX_DATA },
2867 { Bad_Opcode },
2868 { Bad_Opcode },
2869 { "psllq", { Nq, Ib }, PREFIX_OPCODE },
2870 { "pslldq", { Ux, Ib }, PREFIX_DATA },
2871 },
2872 /* REG_0FA6 */
2873 {
2874 { "montmul", { { OP_0f07, 0 } }, 0 },
2875 { "xsha1", { { OP_0f07, 0 } }, 0 },
2876 { "xsha256", { { OP_0f07, 0 } }, 0 },
2877 },
2878 /* REG_0FA7 */
2879 {
2880 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2881 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2882 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2883 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2884 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2885 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2886 },
2887 /* REG_0FAE */
2888 {
2889 { MOD_TABLE (MOD_0FAE_REG_0) },
2890 { MOD_TABLE (MOD_0FAE_REG_1) },
2891 { MOD_TABLE (MOD_0FAE_REG_2) },
2892 { MOD_TABLE (MOD_0FAE_REG_3) },
2893 { MOD_TABLE (MOD_0FAE_REG_4) },
2894 { MOD_TABLE (MOD_0FAE_REG_5) },
2895 { MOD_TABLE (MOD_0FAE_REG_6) },
2896 { MOD_TABLE (MOD_0FAE_REG_7) },
2897 },
2898 /* REG_0FBA */
2899 {
2900 { Bad_Opcode },
2901 { Bad_Opcode },
2902 { Bad_Opcode },
2903 { Bad_Opcode },
2904 { "btQ", { Ev, Ib }, 0 },
2905 { "btsQ", { Evh1, Ib }, 0 },
2906 { "btrQ", { Evh1, Ib }, 0 },
2907 { "btcQ", { Evh1, Ib }, 0 },
2908 },
2909 /* REG_0FC7 */
2910 {
2911 { Bad_Opcode },
2912 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2913 { Bad_Opcode },
2914 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2915 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2916 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2917 { MOD_TABLE (MOD_0FC7_REG_6) },
2918 { MOD_TABLE (MOD_0FC7_REG_7) },
2919 },
2920 /* REG_VEX_0F71 */
2921 {
2922 { Bad_Opcode },
2923 { Bad_Opcode },
2924 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
2925 { Bad_Opcode },
2926 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
2927 { Bad_Opcode },
2928 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
2929 },
2930 /* REG_VEX_0F72 */
2931 {
2932 { Bad_Opcode },
2933 { Bad_Opcode },
2934 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
2935 { Bad_Opcode },
2936 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
2937 { Bad_Opcode },
2938 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
2939 },
2940 /* REG_VEX_0F73 */
2941 {
2942 { Bad_Opcode },
2943 { Bad_Opcode },
2944 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
2945 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
2946 { Bad_Opcode },
2947 { Bad_Opcode },
2948 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
2949 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
2950 },
2951 /* REG_VEX_0FAE */
2952 {
2953 { Bad_Opcode },
2954 { Bad_Opcode },
2955 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2956 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2957 },
2958 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2959 {
2960 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2961 },
2962 /* REG_VEX_0F38F3_L_0_P_0 */
2963 {
2964 { Bad_Opcode },
2965 { "%NFblsrS", { VexGdq, Edq }, 0 },
2966 { "%NFblsmskS", { VexGdq, Edq }, 0 },
2967 { "%NFblsiS", { VexGdq, Edq }, 0 },
2968 },
2969 /* REG_VEX_MAP7_F8_L_0_W_0 */
2970 {
2971 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2972 },
2973 /* REG_XOP_09_01_L_0 */
2974 {
2975 { Bad_Opcode },
2976 { "blcfill", { VexGdq, Edq }, 0 },
2977 { "blsfill", { VexGdq, Edq }, 0 },
2978 { "blcs", { VexGdq, Edq }, 0 },
2979 { "tzmsk", { VexGdq, Edq }, 0 },
2980 { "blcic", { VexGdq, Edq }, 0 },
2981 { "blsic", { VexGdq, Edq }, 0 },
2982 { "t1mskc", { VexGdq, Edq }, 0 },
2983 },
2984 /* REG_XOP_09_02_L_0 */
2985 {
2986 { Bad_Opcode },
2987 { "blcmsk", { VexGdq, Edq }, 0 },
2988 { Bad_Opcode },
2989 { Bad_Opcode },
2990 { Bad_Opcode },
2991 { Bad_Opcode },
2992 { "blci", { VexGdq, Edq }, 0 },
2993 },
2994 /* REG_XOP_09_12_L_0 */
2995 {
2996 { "llwpcb", { Rdq }, 0 },
2997 { "slwpcb", { Rdq }, 0 },
2998 },
2999 /* REG_XOP_0A_12_L_0 */
3000 {
3001 { "lwpins", { VexGdq, Ed, Id }, 0 },
3002 { "lwpval", { VexGdq, Ed, Id }, 0 },
3003 },
3004
3005 #include "i386-dis-evex-reg.h"
3006 };
3007
3008 static const struct dis386 prefix_table[][4] = {
3009 /* PREFIX_90 */
3010 {
3011 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3012 { "pause", { XX }, 0 },
3013 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3014 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3015 },
3016
3017 /* PREFIX_0F00_REG_6_X86_64 */
3018 {
3019 { Bad_Opcode },
3020 { Bad_Opcode },
3021 { Bad_Opcode },
3022 { "lkgsD", { Sv }, 0 },
3023 },
3024
3025 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3026 {
3027 { "wrmsrns", { Skip_MODRM }, 0 },
3028 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3029 { Bad_Opcode },
3030 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3031 },
3032
3033 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3034 {
3035 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3036 },
3037
3038 /* PREFIX_0F01_REG_1_RM_2 */
3039 {
3040 { "clac", { Skip_MODRM }, 0 },
3041 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3042 { Bad_Opcode },
3043 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3044 },
3045
3046 /* PREFIX_0F01_REG_1_RM_4 */
3047 {
3048 { Bad_Opcode },
3049 { Bad_Opcode },
3050 { "tdcall", { Skip_MODRM }, 0 },
3051 { Bad_Opcode },
3052 },
3053
3054 /* PREFIX_0F01_REG_1_RM_5 */
3055 {
3056 { Bad_Opcode },
3057 { Bad_Opcode },
3058 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3059 { Bad_Opcode },
3060 },
3061
3062 /* PREFIX_0F01_REG_1_RM_6 */
3063 {
3064 { Bad_Opcode },
3065 { Bad_Opcode },
3066 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3067 { Bad_Opcode },
3068 },
3069
3070 /* PREFIX_0F01_REG_1_RM_7 */
3071 {
3072 { "encls", { Skip_MODRM }, 0 },
3073 { Bad_Opcode },
3074 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3075 { Bad_Opcode },
3076 },
3077
3078 /* PREFIX_0F01_REG_3_RM_1 */
3079 {
3080 { "vmmcall", { Skip_MODRM }, 0 },
3081 { "vmgexit", { Skip_MODRM }, 0 },
3082 { Bad_Opcode },
3083 { "vmgexit", { Skip_MODRM }, 0 },
3084 },
3085
3086 /* PREFIX_0F01_REG_5_MOD_0 */
3087 {
3088 { Bad_Opcode },
3089 { "rstorssp", { Mq }, PREFIX_OPCODE },
3090 },
3091
3092 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3093 {
3094 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3095 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3096 { Bad_Opcode },
3097 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3098 },
3099
3100 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3101 {
3102 { Bad_Opcode },
3103 { Bad_Opcode },
3104 { Bad_Opcode },
3105 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3106 },
3107
3108 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3109 {
3110 { Bad_Opcode },
3111 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3112 },
3113
3114 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3115 {
3116 { Bad_Opcode },
3117 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3118 },
3119
3120 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3121 {
3122 { Bad_Opcode },
3123 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3124 },
3125
3126 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3127 {
3128 { "rdpkru", { Skip_MODRM }, 0 },
3129 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3130 },
3131
3132 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3133 {
3134 { "wrpkru", { Skip_MODRM }, 0 },
3135 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3136 },
3137
3138 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3139 {
3140 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3141 { "mcommit", { Skip_MODRM }, 0 },
3142 },
3143
3144 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3145 {
3146 { "rdpru", { Skip_MODRM }, 0 },
3147 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3148 },
3149
3150 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3151 {
3152 { "invlpgb", { Skip_MODRM }, 0 },
3153 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3154 { Bad_Opcode },
3155 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3156 },
3157
3158 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3159 {
3160 { "tlbsync", { Skip_MODRM }, 0 },
3161 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3162 { Bad_Opcode },
3163 { "pvalidate", { Skip_MODRM }, 0 },
3164 },
3165
3166 /* PREFIX_0F09 */
3167 {
3168 { "wbinvd", { XX }, 0 },
3169 { "wbnoinvd", { XX }, 0 },
3170 },
3171
3172 /* PREFIX_0F10 */
3173 {
3174 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3175 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3176 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3177 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3178 },
3179
3180 /* PREFIX_0F11 */
3181 {
3182 { "%XEVmovupX", { EXxS, XM }, 0 },
3183 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3184 { "%XEVmovupX", { EXxS, XM }, 0 },
3185 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3186 },
3187
3188 /* PREFIX_0F12 */
3189 {
3190 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3191 { "movsldup", { XM, EXx }, 0 },
3192 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
3193 { "movddup", { XM, EXq }, 0 },
3194 },
3195
3196 /* PREFIX_0F16 */
3197 {
3198 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3199 { "movshdup", { XM, EXx }, 0 },
3200 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
3201 },
3202
3203 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3204 {
3205 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3206 { "nopQ", { Ev }, 0 },
3207 { "nopQ", { Ev }, 0 },
3208 { "nopQ", { Ev }, 0 },
3209 },
3210
3211 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3212 {
3213 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3214 { "nopQ", { Ev }, 0 },
3215 { "nopQ", { Ev }, 0 },
3216 { "nopQ", { Ev }, 0 },
3217 },
3218
3219 /* PREFIX_0F1A */
3220 {
3221 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3222 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3223 { "bndmov", { Gbnd, Ebnd }, 0 },
3224 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3225 },
3226
3227 /* PREFIX_0F1B */
3228 {
3229 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3230 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3231 { "bndmov", { EbndS, Gbnd }, 0 },
3232 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3233 },
3234
3235 /* PREFIX_0F1C */
3236 {
3237 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3238 { "nopQ", { Ev }, PREFIX_IGNORED },
3239 { "nopQ", { Ev }, 0 },
3240 { "nopQ", { Ev }, PREFIX_IGNORED },
3241 },
3242
3243 /* PREFIX_0F1E */
3244 {
3245 { "nopQ", { Ev }, 0 },
3246 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3247 { "nopQ", { Ev }, 0 },
3248 { NULL, { XX }, PREFIX_IGNORED },
3249 },
3250
3251 /* PREFIX_0F2A */
3252 {
3253 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3254 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3255 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3256 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3257 },
3258
3259 /* PREFIX_0F2B */
3260 {
3261 { "movntps", { Mx, XM }, 0 },
3262 { "movntss", { Md, XM }, 0 },
3263 { "movntpd", { Mx, XM }, 0 },
3264 { "movntsd", { Mq, XM }, 0 },
3265 },
3266
3267 /* PREFIX_0F2C */
3268 {
3269 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3270 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3271 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3272 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3273 },
3274
3275 /* PREFIX_0F2D */
3276 {
3277 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3278 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3279 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3280 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3281 },
3282
3283 /* PREFIX_0F2E */
3284 {
3285 { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3286 { Bad_Opcode },
3287 { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3288 },
3289
3290 /* PREFIX_0F2F */
3291 {
3292 { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3293 { Bad_Opcode },
3294 { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3295 },
3296
3297 /* PREFIX_0F51 */
3298 {
3299 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3300 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3301 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3302 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3303 },
3304
3305 /* PREFIX_0F52 */
3306 {
3307 { "Vrsqrtps", { XM, EXx }, 0 },
3308 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3309 },
3310
3311 /* PREFIX_0F53 */
3312 {
3313 { "Vrcpps", { XM, EXx }, 0 },
3314 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3315 },
3316
3317 /* PREFIX_0F58 */
3318 {
3319 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3320 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3321 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3322 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3323 },
3324
3325 /* PREFIX_0F59 */
3326 {
3327 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3328 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3329 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3330 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3331 },
3332
3333 /* PREFIX_0F5A */
3334 {
3335 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3336 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3337 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3338 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3339 },
3340
3341 /* PREFIX_0F5B */
3342 {
3343 { "Vcvtdq2ps", { XM, EXx }, 0 },
3344 { "Vcvttps2dq", { XM, EXx }, 0 },
3345 { "Vcvtps2dq", { XM, EXx }, 0 },
3346 },
3347
3348 /* PREFIX_0F5C */
3349 {
3350 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3351 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3352 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3353 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3354 },
3355
3356 /* PREFIX_0F5D */
3357 {
3358 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3359 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3360 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3361 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3362 },
3363
3364 /* PREFIX_0F5E */
3365 {
3366 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3367 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3368 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3369 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3370 },
3371
3372 /* PREFIX_0F5F */
3373 {
3374 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3375 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3376 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3377 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3378 },
3379
3380 /* PREFIX_0F60 */
3381 {
3382 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3383 { Bad_Opcode },
3384 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3385 },
3386
3387 /* PREFIX_0F61 */
3388 {
3389 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3390 { Bad_Opcode },
3391 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3392 },
3393
3394 /* PREFIX_0F62 */
3395 {
3396 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3397 { Bad_Opcode },
3398 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3399 },
3400
3401 /* PREFIX_0F6F */
3402 {
3403 { "movq", { MX, EM }, PREFIX_OPCODE },
3404 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3405 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3406 },
3407
3408 /* PREFIX_0F70 */
3409 {
3410 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3411 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3412 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3413 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3414 },
3415
3416 /* PREFIX_0F78 */
3417 {
3418 {"vmread", { Em, Gm }, 0 },
3419 { Bad_Opcode },
3420 {"extrq", { Uxmm, Ib, Ib }, 0 },
3421 {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3422 },
3423
3424 /* PREFIX_0F79 */
3425 {
3426 {"vmwrite", { Gm, Em }, 0 },
3427 { Bad_Opcode },
3428 {"extrq", { XM, Uxmm }, 0 },
3429 {"insertq", { XM, Uxmm }, 0 },
3430 },
3431
3432 /* PREFIX_0F7C */
3433 {
3434 { Bad_Opcode },
3435 { Bad_Opcode },
3436 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3437 { "Vhaddps", { XM, Vex, EXx }, 0 },
3438 },
3439
3440 /* PREFIX_0F7D */
3441 {
3442 { Bad_Opcode },
3443 { Bad_Opcode },
3444 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3445 { "Vhsubps", { XM, Vex, EXx }, 0 },
3446 },
3447
3448 /* PREFIX_0F7E */
3449 {
3450 { "movK", { Edq, MX }, PREFIX_OPCODE },
3451 { "movq", { XM, EXq }, PREFIX_OPCODE },
3452 { "movK", { Edq, XM }, PREFIX_OPCODE },
3453 },
3454
3455 /* PREFIX_0F7F */
3456 {
3457 { "movq", { EMS, MX }, PREFIX_OPCODE },
3458 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3459 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3460 },
3461
3462 /* PREFIX_0FAE_REG_0_MOD_3 */
3463 {
3464 { Bad_Opcode },
3465 { "rdfsbase", { Ev }, 0 },
3466 },
3467
3468 /* PREFIX_0FAE_REG_1_MOD_3 */
3469 {
3470 { Bad_Opcode },
3471 { "rdgsbase", { Ev }, 0 },
3472 },
3473
3474 /* PREFIX_0FAE_REG_2_MOD_3 */
3475 {
3476 { Bad_Opcode },
3477 { "wrfsbase", { Ev }, 0 },
3478 },
3479
3480 /* PREFIX_0FAE_REG_3_MOD_3 */
3481 {
3482 { Bad_Opcode },
3483 { "wrgsbase", { Ev }, 0 },
3484 },
3485
3486 /* PREFIX_0FAE_REG_4_MOD_0 */
3487 {
3488 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3489 { "ptwrite{%LQ|}", { Edq }, 0 },
3490 },
3491
3492 /* PREFIX_0FAE_REG_4_MOD_3 */
3493 {
3494 { Bad_Opcode },
3495 { "ptwrite{%LQ|}", { Edq }, 0 },
3496 },
3497
3498 /* PREFIX_0FAE_REG_5_MOD_3 */
3499 {
3500 { "lfence", { Skip_MODRM }, 0 },
3501 { "incsspK", { Edq }, PREFIX_OPCODE },
3502 },
3503
3504 /* PREFIX_0FAE_REG_6_MOD_0 */
3505 {
3506 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3507 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3508 { "clwb", { Mb }, PREFIX_OPCODE },
3509 },
3510
3511 /* PREFIX_0FAE_REG_6_MOD_3 */
3512 {
3513 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3514 { "umonitor", { Eva }, PREFIX_OPCODE },
3515 { "tpause", { Edq }, PREFIX_OPCODE },
3516 { "umwait", { Edq }, PREFIX_OPCODE },
3517 },
3518
3519 /* PREFIX_0FAE_REG_7_MOD_0 */
3520 {
3521 { "clflush", { Mb }, 0 },
3522 { Bad_Opcode },
3523 { "clflushopt", { Mb }, 0 },
3524 },
3525
3526 /* PREFIX_0FB8 */
3527 {
3528 { Bad_Opcode },
3529 { "popcntS", { Gv, Ev }, 0 },
3530 },
3531
3532 /* PREFIX_0FBC */
3533 {
3534 { "bsfS", { Gv, Ev }, 0 },
3535 { "tzcntS", { Gv, Ev }, 0 },
3536 { "bsfS", { Gv, Ev }, 0 },
3537 },
3538
3539 /* PREFIX_0FBD */
3540 {
3541 { "bsrS", { Gv, Ev }, 0 },
3542 { "lzcntS", { Gv, Ev }, 0 },
3543 { "bsrS", { Gv, Ev }, 0 },
3544 },
3545
3546 /* PREFIX_0FC2 */
3547 {
3548 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3549 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3550 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3551 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3552 },
3553
3554 /* PREFIX_0FC7_REG_6_MOD_0 */
3555 {
3556 { "vmptrld",{ Mq }, 0 },
3557 { "vmxon", { Mq }, 0 },
3558 { "vmclear",{ Mq }, 0 },
3559 },
3560
3561 /* PREFIX_0FC7_REG_6_MOD_3 */
3562 {
3563 { "rdrand", { Ev }, 0 },
3564 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3565 { "rdrand", { Ev }, 0 }
3566 },
3567
3568 /* PREFIX_0FC7_REG_7_MOD_3 */
3569 {
3570 { "rdseed", { Ev }, 0 },
3571 { "rdpid", { Em }, 0 },
3572 { "rdseed", { Ev }, 0 },
3573 },
3574
3575 /* PREFIX_0FD0 */
3576 {
3577 { Bad_Opcode },
3578 { Bad_Opcode },
3579 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3580 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3581 },
3582
3583 /* PREFIX_0FD6 */
3584 {
3585 { Bad_Opcode },
3586 { "movq2dq",{ XM, Nq }, 0 },
3587 { "movq", { EXqS, XM }, 0 },
3588 { "movdq2q",{ MX, Ux }, 0 },
3589 },
3590
3591 /* PREFIX_0FE6 */
3592 {
3593 { Bad_Opcode },
3594 { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
3595 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
3596 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3597 },
3598
3599 /* PREFIX_0FE7 */
3600 {
3601 { "movntq", { Mq, MX }, 0 },
3602 { Bad_Opcode },
3603 { "movntdq", { Mx, XM }, 0 },
3604 },
3605
3606 /* PREFIX_0FF0 */
3607 {
3608 { Bad_Opcode },
3609 { Bad_Opcode },
3610 { Bad_Opcode },
3611 { "Vlddqu", { XM, M }, 0 },
3612 },
3613
3614 /* PREFIX_0FF7 */
3615 {
3616 { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3617 { Bad_Opcode },
3618 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3619 },
3620
3621 /* PREFIX_0F38D8 */
3622 {
3623 { Bad_Opcode },
3624 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3625 },
3626
3627 /* PREFIX_0F38DC */
3628 {
3629 { Bad_Opcode },
3630 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3631 { "aesenc", { XM, EXx }, 0 },
3632 },
3633
3634 /* PREFIX_0F38DD */
3635 {
3636 { Bad_Opcode },
3637 { "aesdec128kl", { XM, M }, 0 },
3638 { "aesenclast", { XM, EXx }, 0 },
3639 },
3640
3641 /* PREFIX_0F38DE */
3642 {
3643 { Bad_Opcode },
3644 { "aesenc256kl", { XM, M }, 0 },
3645 { "aesdec", { XM, EXx }, 0 },
3646 },
3647
3648 /* PREFIX_0F38DF */
3649 {
3650 { Bad_Opcode },
3651 { "aesdec256kl", { XM, M }, 0 },
3652 { "aesdeclast", { XM, EXx }, 0 },
3653 },
3654
3655 /* PREFIX_0F38F0 */
3656 {
3657 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3658 { Bad_Opcode },
3659 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3660 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3661 },
3662
3663 /* PREFIX_0F38F1 */
3664 {
3665 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3666 { Bad_Opcode },
3667 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3668 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3669 },
3670
3671 /* PREFIX_0F38F6 */
3672 {
3673 { "wrssK", { M, Gdq }, 0 },
3674 { "adoxL", { VexGdq, Gdq, Edq }, 0 },
3675 { "adcxL", { VexGdq, Gdq, Edq }, 0 },
3676 { Bad_Opcode },
3677 },
3678
3679 /* PREFIX_0F38F8_M_0 */
3680 {
3681 { Bad_Opcode },
3682 { "enqcmds", { Gva, M }, 0 },
3683 { "movdir64b", { Gva, M }, 0 },
3684 { "enqcmd", { Gva, M }, 0 },
3685 },
3686
3687 /* PREFIX_0F38F8_M_1_X86_64 */
3688 {
3689 { Bad_Opcode },
3690 { "uwrmsr", { Gq, Rq }, 0 },
3691 { Bad_Opcode },
3692 { "urdmsr", { Rq, Gq }, 0 },
3693 },
3694
3695 /* PREFIX_0F38FA */
3696 {
3697 { Bad_Opcode },
3698 { "encodekey128", { Gd, Rd }, 0 },
3699 },
3700
3701 /* PREFIX_0F38FB */
3702 {
3703 { Bad_Opcode },
3704 { "encodekey256", { Gd, Rd }, 0 },
3705 },
3706
3707 /* PREFIX_0F38FC */
3708 {
3709 { "aadd", { Mdq, Gdq }, 0 },
3710 { "axor", { Mdq, Gdq }, 0 },
3711 { "aand", { Mdq, Gdq }, 0 },
3712 { "aor", { Mdq, Gdq }, 0 },
3713 },
3714
3715 /* PREFIX_0F3A0F */
3716 {
3717 { Bad_Opcode },
3718 { REG_TABLE (REG_0F3A0F_P_1) },
3719 },
3720
3721 /* PREFIX_VEX_0F12 */
3722 {
3723 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3724 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3725 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3726 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3727 },
3728
3729 /* PREFIX_VEX_0F16 */
3730 {
3731 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3732 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3733 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3734 },
3735
3736 /* PREFIX_VEX_0F2A */
3737 {
3738 { Bad_Opcode },
3739 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3740 { Bad_Opcode },
3741 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3742 },
3743
3744 /* PREFIX_VEX_0F2C */
3745 {
3746 { Bad_Opcode },
3747 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3748 { Bad_Opcode },
3749 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3750 },
3751
3752 /* PREFIX_VEX_0F2D */
3753 {
3754 { Bad_Opcode },
3755 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3756 { Bad_Opcode },
3757 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3758 },
3759
3760 /* PREFIX_VEX_0F41_L_1_W_0 */
3761 {
3762 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
3763 { Bad_Opcode },
3764 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
3765 },
3766
3767 /* PREFIX_VEX_0F41_L_1_W_1 */
3768 {
3769 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
3770 { Bad_Opcode },
3771 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
3772 },
3773
3774 /* PREFIX_VEX_0F42_L_1_W_0 */
3775 {
3776 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
3777 { Bad_Opcode },
3778 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
3779 },
3780
3781 /* PREFIX_VEX_0F42_L_1_W_1 */
3782 {
3783 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
3784 { Bad_Opcode },
3785 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
3786 },
3787
3788 /* PREFIX_VEX_0F44_L_0_W_0 */
3789 {
3790 { "knotw", { MaskG, MaskR }, 0 },
3791 { Bad_Opcode },
3792 { "knotb", { MaskG, MaskR }, 0 },
3793 },
3794
3795 /* PREFIX_VEX_0F44_L_0_W_1 */
3796 {
3797 { "knotq", { MaskG, MaskR }, 0 },
3798 { Bad_Opcode },
3799 { "knotd", { MaskG, MaskR }, 0 },
3800 },
3801
3802 /* PREFIX_VEX_0F45_L_1_W_0 */
3803 {
3804 { "korw", { MaskG, MaskVex, MaskR }, 0 },
3805 { Bad_Opcode },
3806 { "korb", { MaskG, MaskVex, MaskR }, 0 },
3807 },
3808
3809 /* PREFIX_VEX_0F45_L_1_W_1 */
3810 {
3811 { "korq", { MaskG, MaskVex, MaskR }, 0 },
3812 { Bad_Opcode },
3813 { "kord", { MaskG, MaskVex, MaskR }, 0 },
3814 },
3815
3816 /* PREFIX_VEX_0F46_L_1_W_0 */
3817 {
3818 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
3819 { Bad_Opcode },
3820 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
3821 },
3822
3823 /* PREFIX_VEX_0F46_L_1_W_1 */
3824 {
3825 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
3826 { Bad_Opcode },
3827 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
3828 },
3829
3830 /* PREFIX_VEX_0F47_L_1_W_0 */
3831 {
3832 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
3833 { Bad_Opcode },
3834 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
3835 },
3836
3837 /* PREFIX_VEX_0F47_L_1_W_1 */
3838 {
3839 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
3840 { Bad_Opcode },
3841 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
3842 },
3843
3844 /* PREFIX_VEX_0F4A_L_1_W_0 */
3845 {
3846 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
3847 { Bad_Opcode },
3848 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
3849 },
3850
3851 /* PREFIX_VEX_0F4A_L_1_W_1 */
3852 {
3853 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
3854 { Bad_Opcode },
3855 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
3856 },
3857
3858 /* PREFIX_VEX_0F4B_L_1_W_0 */
3859 {
3860 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
3861 { Bad_Opcode },
3862 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
3863 },
3864
3865 /* PREFIX_VEX_0F4B_L_1_W_1 */
3866 {
3867 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
3868 },
3869
3870 /* PREFIX_VEX_0F6F */
3871 {
3872 { Bad_Opcode },
3873 { "vmovdqu", { XM, EXx }, 0 },
3874 { "vmovdqa", { XM, EXx }, 0 },
3875 },
3876
3877 /* PREFIX_VEX_0F70 */
3878 {
3879 { Bad_Opcode },
3880 { "vpshufhw", { XM, EXx, Ib }, 0 },
3881 { "vpshufd", { XM, EXx, Ib }, 0 },
3882 { "vpshuflw", { XM, EXx, Ib }, 0 },
3883 },
3884
3885 /* PREFIX_VEX_0F7E */
3886 {
3887 { Bad_Opcode },
3888 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3889 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3890 },
3891
3892 /* PREFIX_VEX_0F7F */
3893 {
3894 { Bad_Opcode },
3895 { "vmovdqu", { EXxS, XM }, 0 },
3896 { "vmovdqa", { EXxS, XM }, 0 },
3897 },
3898
3899 /* PREFIX_VEX_0F90_L_0_W_0 */
3900 {
3901 { "%XEkmovw", { MaskG, MaskE }, 0 },
3902 { Bad_Opcode },
3903 { "%XEkmovb", { MaskG, MaskBDE }, 0 },
3904 },
3905
3906 /* PREFIX_VEX_0F90_L_0_W_1 */
3907 {
3908 { "%XEkmovq", { MaskG, MaskE }, 0 },
3909 { Bad_Opcode },
3910 { "%XEkmovd", { MaskG, MaskBDE }, 0 },
3911 },
3912
3913 /* PREFIX_VEX_0F91_L_0_W_0 */
3914 {
3915 { "%XEkmovw", { Mw, MaskG }, 0 },
3916 { Bad_Opcode },
3917 { "%XEkmovb", { Mb, MaskG }, 0 },
3918 },
3919
3920 /* PREFIX_VEX_0F91_L_0_W_1 */
3921 {
3922 { "%XEkmovq", { Mq, MaskG }, 0 },
3923 { Bad_Opcode },
3924 { "%XEkmovd", { Md, MaskG }, 0 },
3925 },
3926
3927 /* PREFIX_VEX_0F92_L_0_W_0 */
3928 {
3929 { "%XEkmovw", { MaskG, Rdq }, 0 },
3930 { Bad_Opcode },
3931 { "%XEkmovb", { MaskG, Rdq }, 0 },
3932 { "%XEkmovd", { MaskG, Rdq }, 0 },
3933 },
3934
3935 /* PREFIX_VEX_0F92_L_0_W_1 */
3936 {
3937 { Bad_Opcode },
3938 { Bad_Opcode },
3939 { Bad_Opcode },
3940 { "%XEkmovK", { MaskG, Rdq }, 0 },
3941 },
3942
3943 /* PREFIX_VEX_0F93_L_0_W_0 */
3944 {
3945 { "%XEkmovw", { Gdq, MaskR }, 0 },
3946 { Bad_Opcode },
3947 { "%XEkmovb", { Gdq, MaskR }, 0 },
3948 { "%XEkmovd", { Gdq, MaskR }, 0 },
3949 },
3950
3951 /* PREFIX_VEX_0F93_L_0_W_1 */
3952 {
3953 { Bad_Opcode },
3954 { Bad_Opcode },
3955 { Bad_Opcode },
3956 { "%XEkmovK", { Gdq, MaskR }, 0 },
3957 },
3958
3959 /* PREFIX_VEX_0F98_L_0_W_0 */
3960 {
3961 { "kortestw", { MaskG, MaskR }, 0 },
3962 { Bad_Opcode },
3963 { "kortestb", { MaskG, MaskR }, 0 },
3964 },
3965
3966 /* PREFIX_VEX_0F98_L_0_W_1 */
3967 {
3968 { "kortestq", { MaskG, MaskR }, 0 },
3969 { Bad_Opcode },
3970 { "kortestd", { MaskG, MaskR }, 0 },
3971 },
3972
3973 /* PREFIX_VEX_0F99_L_0_W_0 */
3974 {
3975 { "ktestw", { MaskG, MaskR }, 0 },
3976 { Bad_Opcode },
3977 { "ktestb", { MaskG, MaskR }, 0 },
3978 },
3979
3980 /* PREFIX_VEX_0F99_L_0_W_1 */
3981 {
3982 { "ktestq", { MaskG, MaskR }, 0 },
3983 { Bad_Opcode },
3984 { "ktestd", { MaskG, MaskR }, 0 },
3985 },
3986
3987 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3988 {
3989 { "ldtilecfg", { M }, 0 },
3990 { Bad_Opcode },
3991 { "sttilecfg", { M }, 0 },
3992 },
3993
3994 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3995 {
3996 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3997 { Bad_Opcode },
3998 { Bad_Opcode },
3999 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
4000 },
4001
4002 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
4003 {
4004 { Bad_Opcode },
4005 { "tilestored", { MVexSIBMEM, TMM }, 0 },
4006 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
4007 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
4008 },
4009
4010 /* PREFIX_VEX_0F3850_W_0 */
4011 {
4012 { "vpdpbuud", { XM, Vex, EXx }, 0 },
4013 { "vpdpbsud", { XM, Vex, EXx }, 0 },
4014 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4015 { "vpdpbssd", { XM, Vex, EXx }, 0 },
4016 },
4017
4018 /* PREFIX_VEX_0F3851_W_0 */
4019 {
4020 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
4021 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
4022 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4023 { "vpdpbssds", { XM, Vex, EXx }, 0 },
4024 },
4025 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4026 {
4027 { Bad_Opcode },
4028 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4029 { Bad_Opcode },
4030 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4031 },
4032
4033 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4034 {
4035 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4036 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4037 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4038 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4039 },
4040
4041 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4042 {
4043 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4044 { Bad_Opcode },
4045 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4046 },
4047
4048 /* PREFIX_VEX_0F3872 */
4049 {
4050 { Bad_Opcode },
4051 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4052 },
4053
4054 /* PREFIX_VEX_0F38B0_W_0 */
4055 {
4056 { "vcvtneoph2ps", { XM, Mx }, 0 },
4057 { "vcvtneebf162ps", { XM, Mx }, 0 },
4058 { "vcvtneeph2ps", { XM, Mx }, 0 },
4059 { "vcvtneobf162ps", { XM, Mx }, 0 },
4060 },
4061
4062 /* PREFIX_VEX_0F38B1_W_0 */
4063 {
4064 { Bad_Opcode },
4065 { "vbcstnebf162ps", { XM, Mw }, 0 },
4066 { "vbcstnesh2ps", { XM, Mw }, 0 },
4067 },
4068
4069 /* PREFIX_VEX_0F38D2_W_0 */
4070 {
4071 { "vpdpwuud", { XM, Vex, EXx }, 0 },
4072 { "vpdpwsud", { XM, Vex, EXx }, 0 },
4073 { "vpdpwusd", { XM, Vex, EXx }, 0 },
4074 },
4075
4076 /* PREFIX_VEX_0F38D3_W_0 */
4077 {
4078 { "vpdpwuuds", { XM, Vex, EXx }, 0 },
4079 { "vpdpwsuds", { XM, Vex, EXx }, 0 },
4080 { "vpdpwusds", { XM, Vex, EXx }, 0 },
4081 },
4082
4083 /* PREFIX_VEX_0F38CB */
4084 {
4085 { Bad_Opcode },
4086 { Bad_Opcode },
4087 { Bad_Opcode },
4088 { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4089 },
4090
4091 /* PREFIX_VEX_0F38CC */
4092 {
4093 { Bad_Opcode },
4094 { Bad_Opcode },
4095 { Bad_Opcode },
4096 { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4097 },
4098
4099 /* PREFIX_VEX_0F38CD */
4100 {
4101 { Bad_Opcode },
4102 { Bad_Opcode },
4103 { Bad_Opcode },
4104 { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4105 },
4106
4107 /* PREFIX_VEX_0F38DA_W_0 */
4108 {
4109 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4110 { "vsm4key4", { XM, Vex, EXx }, 0 },
4111 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4112 { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4113 },
4114
4115 /* PREFIX_VEX_0F38F2_L_0 */
4116 {
4117 { "%NFandnS", { Gdq, VexGdq, Edq }, 0 },
4118 },
4119
4120 /* PREFIX_VEX_0F38F3_L_0 */
4121 {
4122 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4123 },
4124
4125 /* PREFIX_VEX_0F38F5_L_0 */
4126 {
4127 { "%NFbzhiS", { Gdq, Edq, VexGdq }, 0 },
4128 { "%XEpextS", { Gdq, VexGdq, Edq }, 0 },
4129 { Bad_Opcode },
4130 { "%XEpdepS", { Gdq, VexGdq, Edq }, 0 },
4131 },
4132
4133 /* PREFIX_VEX_0F38F6_L_0 */
4134 {
4135 { Bad_Opcode },
4136 { Bad_Opcode },
4137 { Bad_Opcode },
4138 { "%XEmulxS", { Gdq, VexGdq, Edq }, 0 },
4139 },
4140
4141 /* PREFIX_VEX_0F38F7_L_0 */
4142 {
4143 { "%NFbextrS", { Gdq, Edq, VexGdq }, 0 },
4144 { "%XEsarxS", { Gdq, Edq, VexGdq }, 0 },
4145 { "%XEshlxS", { Gdq, Edq, VexGdq }, 0 },
4146 { "%XEshrxS", { Gdq, Edq, VexGdq }, 0 },
4147 },
4148
4149 /* PREFIX_VEX_0F3AF0_L_0 */
4150 {
4151 { Bad_Opcode },
4152 { Bad_Opcode },
4153 { Bad_Opcode },
4154 { "%XErorxS", { Gdq, Edq, Ib }, 0 },
4155 },
4156
4157 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4158 {
4159 { Bad_Opcode },
4160 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4161 { Bad_Opcode },
4162 { "urdmsr", { Rq, Id }, 0 },
4163 },
4164
4165 #include "i386-dis-evex-prefix.h"
4166 };
4167
4168 static const struct dis386 x86_64_table[][2] = {
4169 /* X86_64_06 */
4170 {
4171 { "pushP", { es }, 0 },
4172 },
4173
4174 /* X86_64_07 */
4175 {
4176 { "popP", { es }, 0 },
4177 },
4178
4179 /* X86_64_0E */
4180 {
4181 { "pushP", { cs }, 0 },
4182 },
4183
4184 /* X86_64_16 */
4185 {
4186 { "pushP", { ss }, 0 },
4187 },
4188
4189 /* X86_64_17 */
4190 {
4191 { "popP", { ss }, 0 },
4192 },
4193
4194 /* X86_64_1E */
4195 {
4196 { "pushP", { ds }, 0 },
4197 },
4198
4199 /* X86_64_1F */
4200 {
4201 { "popP", { ds }, 0 },
4202 },
4203
4204 /* X86_64_27 */
4205 {
4206 { "daa", { XX }, 0 },
4207 },
4208
4209 /* X86_64_2F */
4210 {
4211 { "das", { XX }, 0 },
4212 },
4213
4214 /* X86_64_37 */
4215 {
4216 { "aaa", { XX }, 0 },
4217 },
4218
4219 /* X86_64_3F */
4220 {
4221 { "aas", { XX }, 0 },
4222 },
4223
4224 /* X86_64_60 */
4225 {
4226 { "pushaP", { XX }, 0 },
4227 },
4228
4229 /* X86_64_61 */
4230 {
4231 { "popaP", { XX }, 0 },
4232 },
4233
4234 /* X86_64_62 */
4235 {
4236 { MOD_TABLE (MOD_62_32BIT) },
4237 { EVEX_TABLE () },
4238 },
4239
4240 /* X86_64_63 */
4241 {
4242 { "arplS", { Sv, Gv }, 0 },
4243 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4244 },
4245
4246 /* X86_64_6D */
4247 {
4248 { "ins{R|}", { Yzr, indirDX }, 0 },
4249 { "ins{G|}", { Yzr, indirDX }, 0 },
4250 },
4251
4252 /* X86_64_6F */
4253 {
4254 { "outs{R|}", { indirDXr, Xz }, 0 },
4255 { "outs{G|}", { indirDXr, Xz }, 0 },
4256 },
4257
4258 /* X86_64_82 */
4259 {
4260 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4261 { REG_TABLE (REG_80) },
4262 },
4263
4264 /* X86_64_9A */
4265 {
4266 { "{l|}call{P|}", { Ap }, 0 },
4267 },
4268
4269 /* X86_64_C2 */
4270 {
4271 { "retP", { Iw, BND }, 0 },
4272 { "ret@", { Iw, BND }, 0 },
4273 },
4274
4275 /* X86_64_C3 */
4276 {
4277 { "retP", { BND }, 0 },
4278 { "ret@", { BND }, 0 },
4279 },
4280
4281 /* X86_64_C4 */
4282 {
4283 { MOD_TABLE (MOD_C4_32BIT) },
4284 { VEX_C4_TABLE () },
4285 },
4286
4287 /* X86_64_C5 */
4288 {
4289 { MOD_TABLE (MOD_C5_32BIT) },
4290 { VEX_C5_TABLE () },
4291 },
4292
4293 /* X86_64_CE */
4294 {
4295 { "into", { XX }, 0 },
4296 },
4297
4298 /* X86_64_D4 */
4299 {
4300 { "aam", { Ib }, 0 },
4301 },
4302
4303 /* X86_64_D5 */
4304 {
4305 { "aad", { Ib }, 0 },
4306 },
4307
4308 /* X86_64_E8 */
4309 {
4310 { "callP", { Jv, BND }, 0 },
4311 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4312 },
4313
4314 /* X86_64_E9 */
4315 {
4316 { "jmpP", { Jv, BND }, 0 },
4317 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4318 },
4319
4320 /* X86_64_EA */
4321 {
4322 { "{l|}jmp{P|}", { Ap }, 0 },
4323 },
4324
4325 /* X86_64_0F00_REG_6 */
4326 {
4327 { Bad_Opcode },
4328 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4329 },
4330
4331 /* X86_64_0F01_REG_0 */
4332 {
4333 { "sgdt{Q|Q}", { M }, 0 },
4334 { "sgdt", { M }, 0 },
4335 },
4336
4337 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4338 {
4339 { Bad_Opcode },
4340 { "wrmsrlist", { Skip_MODRM }, 0 },
4341 },
4342
4343 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4344 {
4345 { Bad_Opcode },
4346 { "rdmsrlist", { Skip_MODRM }, 0 },
4347 },
4348
4349 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4350 {
4351 { Bad_Opcode },
4352 { "pbndkb", { Skip_MODRM }, 0 },
4353 },
4354
4355 /* X86_64_0F01_REG_1 */
4356 {
4357 { "sidt{Q|Q}", { M }, 0 },
4358 { "sidt", { M }, 0 },
4359 },
4360
4361 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4362 {
4363 { Bad_Opcode },
4364 { "eretu", { Skip_MODRM }, 0 },
4365 },
4366
4367 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4368 {
4369 { Bad_Opcode },
4370 { "erets", { Skip_MODRM }, 0 },
4371 },
4372
4373 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4374 {
4375 { Bad_Opcode },
4376 { "seamret", { Skip_MODRM }, 0 },
4377 },
4378
4379 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4380 {
4381 { Bad_Opcode },
4382 { "seamops", { Skip_MODRM }, 0 },
4383 },
4384
4385 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4386 {
4387 { Bad_Opcode },
4388 { "seamcall", { Skip_MODRM }, 0 },
4389 },
4390
4391 /* X86_64_0F01_REG_2 */
4392 {
4393 { "lgdt{Q|Q}", { M }, 0 },
4394 { "lgdt", { M }, 0 },
4395 },
4396
4397 /* X86_64_0F01_REG_3 */
4398 {
4399 { "lidt{Q|Q}", { M }, 0 },
4400 { "lidt", { M }, 0 },
4401 },
4402
4403 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4404 {
4405 { Bad_Opcode },
4406 { "uiret", { Skip_MODRM }, 0 },
4407 },
4408
4409 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4410 {
4411 { Bad_Opcode },
4412 { "testui", { Skip_MODRM }, 0 },
4413 },
4414
4415 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4416 {
4417 { Bad_Opcode },
4418 { "clui", { Skip_MODRM }, 0 },
4419 },
4420
4421 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4422 {
4423 { Bad_Opcode },
4424 { "stui", { Skip_MODRM }, 0 },
4425 },
4426
4427 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4428 {
4429 { Bad_Opcode },
4430 { "rmpquery", { Skip_MODRM }, 0 },
4431 },
4432
4433 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4434 {
4435 { Bad_Opcode },
4436 { "rmpadjust", { Skip_MODRM }, 0 },
4437 },
4438
4439 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4440 {
4441 { Bad_Opcode },
4442 { "rmpupdate", { Skip_MODRM }, 0 },
4443 },
4444
4445 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4446 {
4447 { Bad_Opcode },
4448 { "psmash", { Skip_MODRM }, 0 },
4449 },
4450
4451 /* X86_64_0F18_REG_6_MOD_0 */
4452 {
4453 { "nopQ", { Ev }, 0 },
4454 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4455 },
4456
4457 /* X86_64_0F18_REG_7_MOD_0 */
4458 {
4459 { "nopQ", { Ev }, 0 },
4460 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4461 },
4462
4463 {
4464 /* X86_64_0F24 */
4465 { "movZ", { Em, Td }, 0 },
4466 },
4467
4468 {
4469 /* X86_64_0F26 */
4470 { "movZ", { Td, Em }, 0 },
4471 },
4472
4473 {
4474 /* X86_64_0F38F8_M_1 */
4475 { Bad_Opcode },
4476 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4477 },
4478
4479 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4480 {
4481 { Bad_Opcode },
4482 { "senduipi", { Eq }, 0 },
4483 },
4484
4485 /* X86_64_VEX_0F3849 */
4486 {
4487 { Bad_Opcode },
4488 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4489 },
4490
4491 /* X86_64_VEX_0F384B */
4492 {
4493 { Bad_Opcode },
4494 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4495 },
4496
4497 /* X86_64_VEX_0F385C */
4498 {
4499 { Bad_Opcode },
4500 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4501 },
4502
4503 /* X86_64_VEX_0F385E */
4504 {
4505 { Bad_Opcode },
4506 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4507 },
4508
4509 /* X86_64_VEX_0F386C */
4510 {
4511 { Bad_Opcode },
4512 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4513 },
4514
4515 /* X86_64_VEX_0F38E0 */
4516 {
4517 { Bad_Opcode },
4518 { "%XEcmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4519 },
4520
4521 /* X86_64_VEX_0F38E1 */
4522 {
4523 { Bad_Opcode },
4524 { "%XEcmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4525 },
4526
4527 /* X86_64_VEX_0F38E2 */
4528 {
4529 { Bad_Opcode },
4530 { "%XEcmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4531 },
4532
4533 /* X86_64_VEX_0F38E3 */
4534 {
4535 { Bad_Opcode },
4536 { "%XEcmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4537 },
4538
4539 /* X86_64_VEX_0F38E4 */
4540 {
4541 { Bad_Opcode },
4542 { "%XEcmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4543 },
4544
4545 /* X86_64_VEX_0F38E5 */
4546 {
4547 { Bad_Opcode },
4548 { "%XEcmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4549 },
4550
4551 /* X86_64_VEX_0F38E6 */
4552 {
4553 { Bad_Opcode },
4554 { "%XEcmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4555 },
4556
4557 /* X86_64_VEX_0F38E7 */
4558 {
4559 { Bad_Opcode },
4560 { "%XEcmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4561 },
4562
4563 /* X86_64_VEX_0F38E8 */
4564 {
4565 { Bad_Opcode },
4566 { "%XEcmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4567 },
4568
4569 /* X86_64_VEX_0F38E9 */
4570 {
4571 { Bad_Opcode },
4572 { "%XEcmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4573 },
4574
4575 /* X86_64_VEX_0F38EA */
4576 {
4577 { Bad_Opcode },
4578 { "%XEcmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4579 },
4580
4581 /* X86_64_VEX_0F38EB */
4582 {
4583 { Bad_Opcode },
4584 { "%XEcmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4585 },
4586
4587 /* X86_64_VEX_0F38EC */
4588 {
4589 { Bad_Opcode },
4590 { "%XEcmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4591 },
4592
4593 /* X86_64_VEX_0F38ED */
4594 {
4595 { Bad_Opcode },
4596 { "%XEcmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4597 },
4598
4599 /* X86_64_VEX_0F38EE */
4600 {
4601 { Bad_Opcode },
4602 { "%XEcmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4603 },
4604
4605 /* X86_64_VEX_0F38EF */
4606 {
4607 { Bad_Opcode },
4608 { "%XEcmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4609 },
4610
4611 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4612 {
4613 { Bad_Opcode },
4614 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4615 },
4616 };
4617
4618 static const struct dis386 three_byte_table[][256] = {
4619
4620 /* THREE_BYTE_0F38 */
4621 {
4622 /* 00 */
4623 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4624 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4625 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4626 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4627 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4628 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4629 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4630 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4631 /* 08 */
4632 { "psignb", { MX, EM }, PREFIX_OPCODE },
4633 { "psignw", { MX, EM }, PREFIX_OPCODE },
4634 { "psignd", { MX, EM }, PREFIX_OPCODE },
4635 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 { Bad_Opcode },
4639 { Bad_Opcode },
4640 /* 10 */
4641 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4646 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4647 { Bad_Opcode },
4648 { "ptest", { XM, EXx }, PREFIX_DATA },
4649 /* 18 */
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4655 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4656 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4657 { Bad_Opcode },
4658 /* 20 */
4659 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4660 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4661 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4662 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4663 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4664 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4665 { Bad_Opcode },
4666 { Bad_Opcode },
4667 /* 28 */
4668 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4669 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4670 { "movntdqa", { XM, Mx }, PREFIX_DATA },
4671 { "packusdw", { XM, EXx }, PREFIX_DATA },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 { Bad_Opcode },
4675 { Bad_Opcode },
4676 /* 30 */
4677 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4678 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4679 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4680 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4681 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4682 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4683 { Bad_Opcode },
4684 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4685 /* 38 */
4686 { "pminsb", { XM, EXx }, PREFIX_DATA },
4687 { "pminsd", { XM, EXx }, PREFIX_DATA },
4688 { "pminuw", { XM, EXx }, PREFIX_DATA },
4689 { "pminud", { XM, EXx }, PREFIX_DATA },
4690 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4691 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4692 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4693 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4694 /* 40 */
4695 { "pmulld", { XM, EXx }, PREFIX_DATA },
4696 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 { Bad_Opcode },
4702 { Bad_Opcode },
4703 /* 48 */
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 { Bad_Opcode },
4711 { Bad_Opcode },
4712 /* 50 */
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 { Bad_Opcode },
4720 { Bad_Opcode },
4721 /* 58 */
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 { Bad_Opcode },
4729 { Bad_Opcode },
4730 /* 60 */
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 { Bad_Opcode },
4738 { Bad_Opcode },
4739 /* 68 */
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 { Bad_Opcode },
4747 { Bad_Opcode },
4748 /* 70 */
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 /* 78 */
4758 { Bad_Opcode },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 { Bad_Opcode },
4765 { Bad_Opcode },
4766 /* 80 */
4767 { "invept", { Gm, Mo }, PREFIX_DATA },
4768 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4769 { "invpcid", { Gm, M }, PREFIX_DATA },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 { Bad_Opcode },
4774 { Bad_Opcode },
4775 /* 88 */
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 /* 90 */
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 /* 98 */
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 /* a0 */
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 /* a8 */
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 /* b0 */
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 /* b8 */
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 /* c0 */
4839 { Bad_Opcode },
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 /* c8 */
4848 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4849 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4850 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4851 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4852 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4853 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4854 { Bad_Opcode },
4855 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4856 /* d0 */
4857 { Bad_Opcode },
4858 { Bad_Opcode },
4859 { Bad_Opcode },
4860 { Bad_Opcode },
4861 { Bad_Opcode },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 /* d8 */
4866 { PREFIX_TABLE (PREFIX_0F38D8) },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { "aesimc", { XM, EXx }, PREFIX_DATA },
4870 { PREFIX_TABLE (PREFIX_0F38DC) },
4871 { PREFIX_TABLE (PREFIX_0F38DD) },
4872 { PREFIX_TABLE (PREFIX_0F38DE) },
4873 { PREFIX_TABLE (PREFIX_0F38DF) },
4874 /* e0 */
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 /* e8 */
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 /* f0 */
4893 { PREFIX_TABLE (PREFIX_0F38F0) },
4894 { PREFIX_TABLE (PREFIX_0F38F1) },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { "wrussK", { M, Gdq }, PREFIX_DATA },
4899 { PREFIX_TABLE (PREFIX_0F38F6) },
4900 { Bad_Opcode },
4901 /* f8 */
4902 { MOD_TABLE (MOD_0F38F8) },
4903 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE },
4904 { PREFIX_TABLE (PREFIX_0F38FA) },
4905 { PREFIX_TABLE (PREFIX_0F38FB) },
4906 { PREFIX_TABLE (PREFIX_0F38FC) },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 },
4911 /* THREE_BYTE_0F3A */
4912 {
4913 /* 00 */
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 { Bad_Opcode },
4921 { Bad_Opcode },
4922 /* 08 */
4923 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4924 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4925 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4926 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4927 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4928 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4929 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4930 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4931 /* 10 */
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4937 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4938 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4939 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4940 /* 18 */
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 { Bad_Opcode },
4948 { Bad_Opcode },
4949 /* 20 */
4950 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4951 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4952 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 { Bad_Opcode },
4957 { Bad_Opcode },
4958 /* 28 */
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 { Bad_Opcode },
4966 { Bad_Opcode },
4967 /* 30 */
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 { Bad_Opcode },
4975 { Bad_Opcode },
4976 /* 38 */
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { Bad_Opcode },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 { Bad_Opcode },
4984 { Bad_Opcode },
4985 /* 40 */
4986 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4987 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4988 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4989 { Bad_Opcode },
4990 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4991 { Bad_Opcode },
4992 { Bad_Opcode },
4993 { Bad_Opcode },
4994 /* 48 */
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 { Bad_Opcode },
5002 { Bad_Opcode },
5003 /* 50 */
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 { Bad_Opcode },
5011 { Bad_Opcode },
5012 /* 58 */
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 { Bad_Opcode },
5020 { Bad_Opcode },
5021 /* 60 */
5022 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5023 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5024 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5025 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 { Bad_Opcode },
5029 { Bad_Opcode },
5030 /* 68 */
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 { Bad_Opcode },
5038 { Bad_Opcode },
5039 /* 70 */
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 /* 78 */
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 /* 80 */
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 /* 88 */
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 /* 90 */
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 /* 98 */
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 /* a0 */
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 /* a8 */
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 /* b0 */
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 /* b8 */
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 /* c0 */
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 { Bad_Opcode },
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 /* c8 */
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5144 { Bad_Opcode },
5145 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5146 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5147 /* d0 */
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 /* d8 */
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5165 /* e0 */
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 /* e8 */
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 /* f0 */
5184 { PREFIX_TABLE (PREFIX_0F3A0F) },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 /* f8 */
5193 { Bad_Opcode },
5194 { Bad_Opcode },
5195 { Bad_Opcode },
5196 { Bad_Opcode },
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 },
5202 };
5203
5204 static const struct dis386 xop_table[][256] = {
5205 /* XOP_08 */
5206 {
5207 /* 00 */
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 { Bad_Opcode },
5215 { Bad_Opcode },
5216 /* 08 */
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 { Bad_Opcode },
5224 { Bad_Opcode },
5225 /* 10 */
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 { Bad_Opcode },
5233 { Bad_Opcode },
5234 /* 18 */
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 { Bad_Opcode },
5242 { Bad_Opcode },
5243 /* 20 */
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 { Bad_Opcode },
5251 { Bad_Opcode },
5252 /* 28 */
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 { Bad_Opcode },
5260 { Bad_Opcode },
5261 /* 30 */
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 { Bad_Opcode },
5269 { Bad_Opcode },
5270 /* 38 */
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 { Bad_Opcode },
5278 { Bad_Opcode },
5279 /* 40 */
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 { Bad_Opcode },
5287 { Bad_Opcode },
5288 /* 48 */
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 { Bad_Opcode },
5296 { Bad_Opcode },
5297 /* 50 */
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 { Bad_Opcode },
5305 { Bad_Opcode },
5306 /* 58 */
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 { Bad_Opcode },
5314 { Bad_Opcode },
5315 /* 60 */
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 { Bad_Opcode },
5323 { Bad_Opcode },
5324 /* 68 */
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 { Bad_Opcode },
5332 { Bad_Opcode },
5333 /* 70 */
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 /* 78 */
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 /* 80 */
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { Bad_Opcode },
5357 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5358 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5359 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5360 /* 88 */
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5368 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5369 /* 90 */
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5376 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5377 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5378 /* 98 */
5379 { Bad_Opcode },
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5386 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5387 /* a0 */
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5391 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5395 { Bad_Opcode },
5396 /* a8 */
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 /* b0 */
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5413 { Bad_Opcode },
5414 /* b8 */
5415 { Bad_Opcode },
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 /* c0 */
5424 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5425 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5426 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5427 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 /* c8 */
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5438 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5439 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5440 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5441 /* d0 */
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 /* d8 */
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 /* e0 */
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 /* e8 */
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5474 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5475 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5476 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5477 /* f0 */
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 /* f8 */
5487 { Bad_Opcode },
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 },
5496 /* XOP_09 */
5497 {
5498 /* 00 */
5499 { Bad_Opcode },
5500 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5501 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 { Bad_Opcode },
5506 { Bad_Opcode },
5507 /* 08 */
5508 { Bad_Opcode },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 { Bad_Opcode },
5515 { Bad_Opcode },
5516 /* 10 */
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 { Bad_Opcode },
5524 { Bad_Opcode },
5525 /* 18 */
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 { Bad_Opcode },
5533 { Bad_Opcode },
5534 /* 20 */
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 { Bad_Opcode },
5542 { Bad_Opcode },
5543 /* 28 */
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 { Bad_Opcode },
5551 { Bad_Opcode },
5552 /* 30 */
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 { Bad_Opcode },
5560 { Bad_Opcode },
5561 /* 38 */
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 { Bad_Opcode },
5569 { Bad_Opcode },
5570 /* 40 */
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 { Bad_Opcode },
5578 { Bad_Opcode },
5579 /* 48 */
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 { Bad_Opcode },
5587 { Bad_Opcode },
5588 /* 50 */
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 { Bad_Opcode },
5596 { Bad_Opcode },
5597 /* 58 */
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 { Bad_Opcode },
5605 { Bad_Opcode },
5606 /* 60 */
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 { Bad_Opcode },
5614 { Bad_Opcode },
5615 /* 68 */
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 { Bad_Opcode },
5623 { Bad_Opcode },
5624 /* 70 */
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 /* 78 */
5634 { Bad_Opcode },
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 /* 80 */
5643 { VEX_W_TABLE (VEX_W_XOP_09_80) },
5644 { VEX_W_TABLE (VEX_W_XOP_09_81) },
5645 { VEX_W_TABLE (VEX_W_XOP_09_82) },
5646 { VEX_W_TABLE (VEX_W_XOP_09_83) },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 /* 88 */
5652 { Bad_Opcode },
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 /* 90 */
5661 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5662 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5663 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5664 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5665 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5666 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5667 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5668 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5669 /* 98 */
5670 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5671 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5672 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5673 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 /* a0 */
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 /* a8 */
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 /* b0 */
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 /* b8 */
5706 { Bad_Opcode },
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 /* c0 */
5715 { Bad_Opcode },
5716 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5717 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5718 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5722 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5723 /* c8 */
5724 { Bad_Opcode },
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 /* d0 */
5733 { Bad_Opcode },
5734 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5735 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5736 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5740 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5741 /* d8 */
5742 { Bad_Opcode },
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 /* e0 */
5751 { Bad_Opcode },
5752 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5753 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5754 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 /* e8 */
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 /* f0 */
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 /* f8 */
5778 { Bad_Opcode },
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 },
5787 /* XOP_0A */
5788 {
5789 /* 00 */
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 { Bad_Opcode },
5797 { Bad_Opcode },
5798 /* 08 */
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 { Bad_Opcode },
5806 { Bad_Opcode },
5807 /* 10 */
5808 { "bextrS", { Gdq, Edq, Id }, 0 },
5809 { Bad_Opcode },
5810 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 { Bad_Opcode },
5815 { Bad_Opcode },
5816 /* 18 */
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 { Bad_Opcode },
5824 { Bad_Opcode },
5825 /* 20 */
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 { Bad_Opcode },
5833 { Bad_Opcode },
5834 /* 28 */
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 { Bad_Opcode },
5842 { Bad_Opcode },
5843 /* 30 */
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 { Bad_Opcode },
5851 { Bad_Opcode },
5852 /* 38 */
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 { Bad_Opcode },
5860 { Bad_Opcode },
5861 /* 40 */
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 { Bad_Opcode },
5869 { Bad_Opcode },
5870 /* 48 */
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 { Bad_Opcode },
5878 { Bad_Opcode },
5879 /* 50 */
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 { Bad_Opcode },
5887 { Bad_Opcode },
5888 /* 58 */
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 { Bad_Opcode },
5896 { Bad_Opcode },
5897 /* 60 */
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 { Bad_Opcode },
5905 { Bad_Opcode },
5906 /* 68 */
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 { Bad_Opcode },
5914 { Bad_Opcode },
5915 /* 70 */
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 /* 78 */
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 /* 80 */
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 { Bad_Opcode },
5941 { Bad_Opcode },
5942 /* 88 */
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 /* 90 */
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 /* 98 */
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 { Bad_Opcode },
5968 { Bad_Opcode },
5969 /* a0 */
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 /* a8 */
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 /* b0 */
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 { Bad_Opcode },
5995 { Bad_Opcode },
5996 /* b8 */
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { Bad_Opcode },
6004 { Bad_Opcode },
6005 /* c0 */
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 { Bad_Opcode },
6013 { Bad_Opcode },
6014 /* c8 */
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 { Bad_Opcode },
6022 { Bad_Opcode },
6023 /* d0 */
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 { Bad_Opcode },
6031 { Bad_Opcode },
6032 /* d8 */
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 { Bad_Opcode },
6040 { Bad_Opcode },
6041 /* e0 */
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 { Bad_Opcode },
6049 { Bad_Opcode },
6050 /* e8 */
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 /* f0 */
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 /* f8 */
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 { Bad_Opcode },
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 },
6078 };
6079
6080 static const struct dis386 vex_table[][256] = {
6081 /* VEX_0F */
6082 {
6083 /* 00 */
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 { Bad_Opcode },
6091 { Bad_Opcode },
6092 /* 08 */
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 { Bad_Opcode },
6100 { Bad_Opcode },
6101 /* 10 */
6102 { PREFIX_TABLE (PREFIX_0F10) },
6103 { PREFIX_TABLE (PREFIX_0F11) },
6104 { PREFIX_TABLE (PREFIX_VEX_0F12) },
6105 { VEX_LEN_TABLE (VEX_LEN_0F13) },
6106 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6107 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6108 { PREFIX_TABLE (PREFIX_VEX_0F16) },
6109 { VEX_LEN_TABLE (VEX_LEN_0F17) },
6110 /* 18 */
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 { Bad_Opcode },
6118 { Bad_Opcode },
6119 /* 20 */
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 { Bad_Opcode },
6127 { Bad_Opcode },
6128 /* 28 */
6129 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6130 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6131 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6132 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6133 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6134 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6135 { PREFIX_TABLE (PREFIX_0F2E) },
6136 { PREFIX_TABLE (PREFIX_0F2F) },
6137 /* 30 */
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 { Bad_Opcode },
6145 { Bad_Opcode },
6146 /* 38 */
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 { Bad_Opcode },
6154 { Bad_Opcode },
6155 /* 40 */
6156 { Bad_Opcode },
6157 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6158 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6159 { Bad_Opcode },
6160 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6161 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6162 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6163 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6164 /* 48 */
6165 { Bad_Opcode },
6166 { Bad_Opcode },
6167 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6168 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6169 { Bad_Opcode },
6170 { Bad_Opcode },
6171 { Bad_Opcode },
6172 { Bad_Opcode },
6173 /* 50 */
6174 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE },
6175 { PREFIX_TABLE (PREFIX_0F51) },
6176 { PREFIX_TABLE (PREFIX_0F52) },
6177 { PREFIX_TABLE (PREFIX_0F53) },
6178 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6179 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6180 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6181 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6182 /* 58 */
6183 { PREFIX_TABLE (PREFIX_0F58) },
6184 { PREFIX_TABLE (PREFIX_0F59) },
6185 { PREFIX_TABLE (PREFIX_0F5A) },
6186 { PREFIX_TABLE (PREFIX_0F5B) },
6187 { PREFIX_TABLE (PREFIX_0F5C) },
6188 { PREFIX_TABLE (PREFIX_0F5D) },
6189 { PREFIX_TABLE (PREFIX_0F5E) },
6190 { PREFIX_TABLE (PREFIX_0F5F) },
6191 /* 60 */
6192 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6193 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6194 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6197 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6198 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6199 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6200 /* 68 */
6201 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6202 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6203 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6204 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6205 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6206 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6207 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6208 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6209 /* 70 */
6210 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6211 { REG_TABLE (REG_VEX_0F71) },
6212 { REG_TABLE (REG_VEX_0F72) },
6213 { REG_TABLE (REG_VEX_0F73) },
6214 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6215 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6216 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6217 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6218 /* 78 */
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { PREFIX_TABLE (PREFIX_0F7C) },
6224 { PREFIX_TABLE (PREFIX_0F7D) },
6225 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6226 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6227 /* 80 */
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 { Bad_Opcode },
6236 /* 88 */
6237 { Bad_Opcode },
6238 { Bad_Opcode },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 { Bad_Opcode },
6244 { Bad_Opcode },
6245 /* 90 */
6246 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6247 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6248 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6249 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6250 { Bad_Opcode },
6251 { Bad_Opcode },
6252 { Bad_Opcode },
6253 { Bad_Opcode },
6254 /* 98 */
6255 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6256 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 { Bad_Opcode },
6262 { Bad_Opcode },
6263 /* a0 */
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { Bad_Opcode },
6269 { Bad_Opcode },
6270 { Bad_Opcode },
6271 { Bad_Opcode },
6272 /* a8 */
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 { REG_TABLE (REG_VEX_0FAE) },
6280 { Bad_Opcode },
6281 /* b0 */
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { Bad_Opcode },
6289 { Bad_Opcode },
6290 /* b8 */
6291 { Bad_Opcode },
6292 { Bad_Opcode },
6293 { Bad_Opcode },
6294 { Bad_Opcode },
6295 { Bad_Opcode },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 /* c0 */
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { PREFIX_TABLE (PREFIX_0FC2) },
6303 { Bad_Opcode },
6304 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6305 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
6306 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6307 { Bad_Opcode },
6308 /* c8 */
6309 { Bad_Opcode },
6310 { Bad_Opcode },
6311 { Bad_Opcode },
6312 { Bad_Opcode },
6313 { Bad_Opcode },
6314 { Bad_Opcode },
6315 { Bad_Opcode },
6316 { Bad_Opcode },
6317 /* d0 */
6318 { PREFIX_TABLE (PREFIX_0FD0) },
6319 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6320 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6321 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6322 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6323 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6324 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6325 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA },
6326 /* d8 */
6327 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6328 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6329 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6330 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6331 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6332 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6333 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6334 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6335 /* e0 */
6336 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6337 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6338 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6339 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6340 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6341 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6342 { PREFIX_TABLE (PREFIX_0FE6) },
6343 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6344 /* e8 */
6345 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6346 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6347 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6348 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6349 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6350 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6351 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6352 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6353 /* f0 */
6354 { PREFIX_TABLE (PREFIX_0FF0) },
6355 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6356 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6357 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6358 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6359 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6360 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6361 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA },
6362 /* f8 */
6363 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6364 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6365 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6367 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6368 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6369 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6370 { Bad_Opcode },
6371 },
6372 /* VEX_0F38 */
6373 {
6374 /* 00 */
6375 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6376 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6377 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6378 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6379 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6380 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6381 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6382 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6383 /* 08 */
6384 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6385 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6386 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6387 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6388 { VEX_W_TABLE (VEX_W_0F380C) },
6389 { VEX_W_TABLE (VEX_W_0F380D) },
6390 { VEX_W_TABLE (VEX_W_0F380E) },
6391 { VEX_W_TABLE (VEX_W_0F380F) },
6392 /* 10 */
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { VEX_W_TABLE (VEX_W_0F3813) },
6397 { Bad_Opcode },
6398 { Bad_Opcode },
6399 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6400 { "vptest", { XM, EXx }, PREFIX_DATA },
6401 /* 18 */
6402 { VEX_W_TABLE (VEX_W_0F3818) },
6403 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6404 { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6405 { Bad_Opcode },
6406 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6407 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6408 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6409 { Bad_Opcode },
6410 /* 20 */
6411 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6412 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6413 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6414 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6415 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6416 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6417 { Bad_Opcode },
6418 { Bad_Opcode },
6419 /* 28 */
6420 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6421 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6422 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
6423 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6424 { VEX_W_TABLE (VEX_W_0F382C) },
6425 { VEX_W_TABLE (VEX_W_0F382D) },
6426 { VEX_W_TABLE (VEX_W_0F382E) },
6427 { VEX_W_TABLE (VEX_W_0F382F) },
6428 /* 30 */
6429 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6430 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6431 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6432 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6433 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6434 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6435 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6436 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6437 /* 38 */
6438 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6439 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6440 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6441 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6442 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6443 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6444 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6445 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6446 /* 40 */
6447 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6448 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6453 { VEX_W_TABLE (VEX_W_0F3846) },
6454 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6455 /* 48 */
6456 { Bad_Opcode },
6457 { X86_64_TABLE (X86_64_VEX_0F3849) },
6458 { Bad_Opcode },
6459 { X86_64_TABLE (X86_64_VEX_0F384B) },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 { Bad_Opcode },
6463 { Bad_Opcode },
6464 /* 50 */
6465 { VEX_W_TABLE (VEX_W_0F3850) },
6466 { VEX_W_TABLE (VEX_W_0F3851) },
6467 { VEX_W_TABLE (VEX_W_0F3852) },
6468 { VEX_W_TABLE (VEX_W_0F3853) },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 { Bad_Opcode },
6472 { Bad_Opcode },
6473 /* 58 */
6474 { VEX_W_TABLE (VEX_W_0F3858) },
6475 { VEX_W_TABLE (VEX_W_0F3859) },
6476 { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6477 { Bad_Opcode },
6478 { X86_64_TABLE (X86_64_VEX_0F385C) },
6479 { Bad_Opcode },
6480 { X86_64_TABLE (X86_64_VEX_0F385E) },
6481 { Bad_Opcode },
6482 /* 60 */
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { Bad_Opcode },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 { Bad_Opcode },
6490 { Bad_Opcode },
6491 /* 68 */
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { X86_64_TABLE (X86_64_VEX_0F386C) },
6497 { Bad_Opcode },
6498 { Bad_Opcode },
6499 { Bad_Opcode },
6500 /* 70 */
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 { Bad_Opcode },
6508 { Bad_Opcode },
6509 /* 78 */
6510 { VEX_W_TABLE (VEX_W_0F3878) },
6511 { VEX_W_TABLE (VEX_W_0F3879) },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 { Bad_Opcode },
6517 { Bad_Opcode },
6518 /* 80 */
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { Bad_Opcode },
6525 { Bad_Opcode },
6526 { Bad_Opcode },
6527 /* 88 */
6528 { Bad_Opcode },
6529 { Bad_Opcode },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6533 { Bad_Opcode },
6534 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6535 { Bad_Opcode },
6536 /* 90 */
6537 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6538 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6539 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6540 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6544 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6545 /* 98 */
6546 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6547 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6548 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6549 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6550 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6551 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6552 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6553 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6554 /* a0 */
6555 { Bad_Opcode },
6556 { Bad_Opcode },
6557 { Bad_Opcode },
6558 { Bad_Opcode },
6559 { Bad_Opcode },
6560 { Bad_Opcode },
6561 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6562 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6563 /* a8 */
6564 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6565 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6566 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6567 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6568 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6569 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6570 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6571 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6572 /* b0 */
6573 { VEX_W_TABLE (VEX_W_0F38B0) },
6574 { VEX_W_TABLE (VEX_W_0F38B1) },
6575 { Bad_Opcode },
6576 { Bad_Opcode },
6577 { VEX_W_TABLE (VEX_W_0F38B4) },
6578 { VEX_W_TABLE (VEX_W_0F38B5) },
6579 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6580 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6581 /* b8 */
6582 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6583 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6584 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6585 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6586 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6587 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6588 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6589 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6590 /* c0 */
6591 { Bad_Opcode },
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 /* c8 */
6600 { Bad_Opcode },
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6604 { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6605 { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6606 { Bad_Opcode },
6607 { VEX_W_TABLE (VEX_W_0F38CF) },
6608 /* d0 */
6609 { Bad_Opcode },
6610 { Bad_Opcode },
6611 { VEX_W_TABLE (VEX_W_0F38D2) },
6612 { VEX_W_TABLE (VEX_W_0F38D3) },
6613 { Bad_Opcode },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 /* d8 */
6618 { Bad_Opcode },
6619 { Bad_Opcode },
6620 { VEX_W_TABLE (VEX_W_0F38DA) },
6621 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6622 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6623 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6624 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6625 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6626 /* e0 */
6627 { X86_64_TABLE (X86_64_VEX_0F38E0) },
6628 { X86_64_TABLE (X86_64_VEX_0F38E1) },
6629 { X86_64_TABLE (X86_64_VEX_0F38E2) },
6630 { X86_64_TABLE (X86_64_VEX_0F38E3) },
6631 { X86_64_TABLE (X86_64_VEX_0F38E4) },
6632 { X86_64_TABLE (X86_64_VEX_0F38E5) },
6633 { X86_64_TABLE (X86_64_VEX_0F38E6) },
6634 { X86_64_TABLE (X86_64_VEX_0F38E7) },
6635 /* e8 */
6636 { X86_64_TABLE (X86_64_VEX_0F38E8) },
6637 { X86_64_TABLE (X86_64_VEX_0F38E9) },
6638 { X86_64_TABLE (X86_64_VEX_0F38EA) },
6639 { X86_64_TABLE (X86_64_VEX_0F38EB) },
6640 { X86_64_TABLE (X86_64_VEX_0F38EC) },
6641 { X86_64_TABLE (X86_64_VEX_0F38ED) },
6642 { X86_64_TABLE (X86_64_VEX_0F38EE) },
6643 { X86_64_TABLE (X86_64_VEX_0F38EF) },
6644 /* f0 */
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6648 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6649 { Bad_Opcode },
6650 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6651 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6652 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6653 /* f8 */
6654 { Bad_Opcode },
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 },
6663 /* VEX_0F3A */
6664 {
6665 /* 00 */
6666 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6668 { VEX_W_TABLE (VEX_W_0F3A02) },
6669 { Bad_Opcode },
6670 { VEX_W_TABLE (VEX_W_0F3A04) },
6671 { VEX_W_TABLE (VEX_W_0F3A05) },
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6673 { Bad_Opcode },
6674 /* 08 */
6675 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6676 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6677 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6678 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6679 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6680 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6681 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6682 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6683 /* 10 */
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6689 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6692 /* 18 */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6694 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { VEX_W_TABLE (VEX_W_0F3A1D) },
6699 { Bad_Opcode },
6700 { Bad_Opcode },
6701 /* 20 */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6703 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 { Bad_Opcode },
6709 { Bad_Opcode },
6710 /* 28 */
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 { Bad_Opcode },
6718 { Bad_Opcode },
6719 /* 30 */
6720 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6722 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6723 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 { Bad_Opcode },
6727 { Bad_Opcode },
6728 /* 38 */
6729 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6730 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { Bad_Opcode },
6734 { Bad_Opcode },
6735 { Bad_Opcode },
6736 { Bad_Opcode },
6737 /* 40 */
6738 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6740 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6741 { Bad_Opcode },
6742 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6743 { Bad_Opcode },
6744 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6745 { Bad_Opcode },
6746 /* 48 */
6747 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6748 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6749 { VEX_W_TABLE (VEX_W_0F3A4A) },
6750 { VEX_W_TABLE (VEX_W_0F3A4B) },
6751 { VEX_W_TABLE (VEX_W_0F3A4C) },
6752 { Bad_Opcode },
6753 { Bad_Opcode },
6754 { Bad_Opcode },
6755 /* 50 */
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 { Bad_Opcode },
6763 { Bad_Opcode },
6764 /* 58 */
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6770 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6771 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6772 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6773 /* 60 */
6774 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6775 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6776 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6777 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 { Bad_Opcode },
6781 { Bad_Opcode },
6782 /* 68 */
6783 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6784 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6785 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6786 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6787 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6788 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6789 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6790 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6791 /* 70 */
6792 { Bad_Opcode },
6793 { Bad_Opcode },
6794 { Bad_Opcode },
6795 { Bad_Opcode },
6796 { Bad_Opcode },
6797 { Bad_Opcode },
6798 { Bad_Opcode },
6799 { Bad_Opcode },
6800 /* 78 */
6801 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6802 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6803 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6804 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6805 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6806 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6807 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6808 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6809 /* 80 */
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 { Bad_Opcode },
6816 { Bad_Opcode },
6817 { Bad_Opcode },
6818 /* 88 */
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 { Bad_Opcode },
6826 { Bad_Opcode },
6827 /* 90 */
6828 { Bad_Opcode },
6829 { Bad_Opcode },
6830 { Bad_Opcode },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 { Bad_Opcode },
6835 { Bad_Opcode },
6836 /* 98 */
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 { Bad_Opcode },
6844 { Bad_Opcode },
6845 /* a0 */
6846 { Bad_Opcode },
6847 { Bad_Opcode },
6848 { Bad_Opcode },
6849 { Bad_Opcode },
6850 { Bad_Opcode },
6851 { Bad_Opcode },
6852 { Bad_Opcode },
6853 { Bad_Opcode },
6854 /* a8 */
6855 { Bad_Opcode },
6856 { Bad_Opcode },
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { Bad_Opcode },
6861 { Bad_Opcode },
6862 { Bad_Opcode },
6863 /* b0 */
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 { Bad_Opcode },
6871 { Bad_Opcode },
6872 /* b8 */
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 { Bad_Opcode },
6880 { Bad_Opcode },
6881 /* c0 */
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { Bad_Opcode },
6887 { Bad_Opcode },
6888 { Bad_Opcode },
6889 { Bad_Opcode },
6890 /* c8 */
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 { VEX_W_TABLE (VEX_W_0F3ACE) },
6898 { VEX_W_TABLE (VEX_W_0F3ACF) },
6899 /* d0 */
6900 { Bad_Opcode },
6901 { Bad_Opcode },
6902 { Bad_Opcode },
6903 { Bad_Opcode },
6904 { Bad_Opcode },
6905 { Bad_Opcode },
6906 { Bad_Opcode },
6907 { Bad_Opcode },
6908 /* d8 */
6909 { Bad_Opcode },
6910 { Bad_Opcode },
6911 { Bad_Opcode },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 { VEX_W_TABLE (VEX_W_0F3ADE) },
6916 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6917 /* e0 */
6918 { Bad_Opcode },
6919 { Bad_Opcode },
6920 { Bad_Opcode },
6921 { Bad_Opcode },
6922 { Bad_Opcode },
6923 { Bad_Opcode },
6924 { Bad_Opcode },
6925 { Bad_Opcode },
6926 /* e8 */
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { Bad_Opcode },
6930 { Bad_Opcode },
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 { Bad_Opcode },
6934 { Bad_Opcode },
6935 /* f0 */
6936 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6937 { Bad_Opcode },
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 { Bad_Opcode },
6941 { Bad_Opcode },
6942 { Bad_Opcode },
6943 { Bad_Opcode },
6944 /* f8 */
6945 { Bad_Opcode },
6946 { Bad_Opcode },
6947 { Bad_Opcode },
6948 { Bad_Opcode },
6949 { Bad_Opcode },
6950 { Bad_Opcode },
6951 { Bad_Opcode },
6952 { Bad_Opcode },
6953 },
6954 };
6955
6956 #include "i386-dis-evex.h"
6957
6958 static const struct dis386 vex_len_table[][2] = {
6959 /* VEX_LEN_0F12_P_0 */
6960 {
6961 { MOD_TABLE (MOD_0F12_PREFIX_0) },
6962 },
6963
6964 /* VEX_LEN_0F12_P_2 */
6965 {
6966 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
6967 },
6968
6969 /* VEX_LEN_0F13 */
6970 {
6971 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE },
6972 },
6973
6974 /* VEX_LEN_0F16_P_0 */
6975 {
6976 { MOD_TABLE (MOD_0F16_PREFIX_0) },
6977 },
6978
6979 /* VEX_LEN_0F16_P_2 */
6980 {
6981 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
6982 },
6983
6984 /* VEX_LEN_0F17 */
6985 {
6986 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE },
6987 },
6988
6989 /* VEX_LEN_0F41 */
6990 {
6991 { Bad_Opcode },
6992 { VEX_W_TABLE (VEX_W_0F41_L_1) },
6993 },
6994
6995 /* VEX_LEN_0F42 */
6996 {
6997 { Bad_Opcode },
6998 { VEX_W_TABLE (VEX_W_0F42_L_1) },
6999 },
7000
7001 /* VEX_LEN_0F44 */
7002 {
7003 { VEX_W_TABLE (VEX_W_0F44_L_0) },
7004 },
7005
7006 /* VEX_LEN_0F45 */
7007 {
7008 { Bad_Opcode },
7009 { VEX_W_TABLE (VEX_W_0F45_L_1) },
7010 },
7011
7012 /* VEX_LEN_0F46 */
7013 {
7014 { Bad_Opcode },
7015 { VEX_W_TABLE (VEX_W_0F46_L_1) },
7016 },
7017
7018 /* VEX_LEN_0F47 */
7019 {
7020 { Bad_Opcode },
7021 { VEX_W_TABLE (VEX_W_0F47_L_1) },
7022 },
7023
7024 /* VEX_LEN_0F4A */
7025 {
7026 { Bad_Opcode },
7027 { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7028 },
7029
7030 /* VEX_LEN_0F4B */
7031 {
7032 { Bad_Opcode },
7033 { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7034 },
7035
7036 /* VEX_LEN_0F6E */
7037 {
7038 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
7039 },
7040
7041 /* VEX_LEN_0F77 */
7042 {
7043 { "vzeroupper", { XX }, 0 },
7044 { "vzeroall", { XX }, 0 },
7045 },
7046
7047 /* VEX_LEN_0F7E_P_1 */
7048 {
7049 { "%XEvmovqY", { XMScalar, EXq }, 0 },
7050 },
7051
7052 /* VEX_LEN_0F7E_P_2 */
7053 {
7054 { "%XEvmovK", { Edq, XMScalar }, 0 },
7055 },
7056
7057 /* VEX_LEN_0F90 */
7058 {
7059 { VEX_W_TABLE (VEX_W_0F90_L_0) },
7060 },
7061
7062 /* VEX_LEN_0F91 */
7063 {
7064 { VEX_W_TABLE (VEX_W_0F91_L_0) },
7065 },
7066
7067 /* VEX_LEN_0F92 */
7068 {
7069 { VEX_W_TABLE (VEX_W_0F92_L_0) },
7070 },
7071
7072 /* VEX_LEN_0F93 */
7073 {
7074 { VEX_W_TABLE (VEX_W_0F93_L_0) },
7075 },
7076
7077 /* VEX_LEN_0F98 */
7078 {
7079 { VEX_W_TABLE (VEX_W_0F98_L_0) },
7080 },
7081
7082 /* VEX_LEN_0F99 */
7083 {
7084 { VEX_W_TABLE (VEX_W_0F99_L_0) },
7085 },
7086
7087 /* VEX_LEN_0FAE_R_2 */
7088 {
7089 { "vldmxcsr", { Md }, 0 },
7090 },
7091
7092 /* VEX_LEN_0FAE_R_3 */
7093 {
7094 { "vstmxcsr", { Md }, 0 },
7095 },
7096
7097 /* VEX_LEN_0FC4 */
7098 {
7099 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7100 },
7101
7102 /* VEX_LEN_0FD6 */
7103 {
7104 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
7105 },
7106
7107 /* VEX_LEN_0F3816 */
7108 {
7109 { Bad_Opcode },
7110 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7111 },
7112
7113 /* VEX_LEN_0F3819 */
7114 {
7115 { Bad_Opcode },
7116 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7117 },
7118
7119 /* VEX_LEN_0F381A */
7120 {
7121 { Bad_Opcode },
7122 { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7123 },
7124
7125 /* VEX_LEN_0F3836 */
7126 {
7127 { Bad_Opcode },
7128 { VEX_W_TABLE (VEX_W_0F3836) },
7129 },
7130
7131 /* VEX_LEN_0F3841 */
7132 {
7133 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7134 },
7135
7136 /* VEX_LEN_0F3849_X86_64 */
7137 {
7138 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7139 },
7140
7141 /* VEX_LEN_0F384B_X86_64 */
7142 {
7143 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7144 },
7145
7146 /* VEX_LEN_0F385A */
7147 {
7148 { Bad_Opcode },
7149 { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7150 },
7151
7152 /* VEX_LEN_0F385C_X86_64 */
7153 {
7154 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7155 },
7156
7157 /* VEX_LEN_0F385E_X86_64 */
7158 {
7159 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7160 },
7161
7162 /* VEX_LEN_0F386C_X86_64 */
7163 {
7164 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7165 },
7166
7167 /* VEX_LEN_0F38CB_P_3_W_0 */
7168 {
7169 { Bad_Opcode },
7170 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7171 },
7172
7173 /* VEX_LEN_0F38CC_P_3_W_0 */
7174 {
7175 { Bad_Opcode },
7176 { "vsha512msg1", { XM, Rxmmq }, 0 },
7177 },
7178
7179 /* VEX_LEN_0F38CD_P_3_W_0 */
7180 {
7181 { Bad_Opcode },
7182 { "vsha512msg2", { XM, Rymm }, 0 },
7183 },
7184
7185 /* VEX_LEN_0F38DA_W_0_P_0 */
7186 {
7187 { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7188 },
7189
7190 /* VEX_LEN_0F38DA_W_0_P_2 */
7191 {
7192 { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7193 },
7194
7195 /* VEX_LEN_0F38DB */
7196 {
7197 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7198 },
7199
7200 /* VEX_LEN_0F38F2 */
7201 {
7202 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7203 },
7204
7205 /* VEX_LEN_0F38F3 */
7206 {
7207 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7208 },
7209
7210 /* VEX_LEN_0F38F5 */
7211 {
7212 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7213 },
7214
7215 /* VEX_LEN_0F38F6 */
7216 {
7217 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7218 },
7219
7220 /* VEX_LEN_0F38F7 */
7221 {
7222 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7223 },
7224
7225 /* VEX_LEN_0F3A00 */
7226 {
7227 { Bad_Opcode },
7228 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7229 },
7230
7231 /* VEX_LEN_0F3A01 */
7232 {
7233 { Bad_Opcode },
7234 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7235 },
7236
7237 /* VEX_LEN_0F3A06 */
7238 {
7239 { Bad_Opcode },
7240 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7241 },
7242
7243 /* VEX_LEN_0F3A14 */
7244 {
7245 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7246 },
7247
7248 /* VEX_LEN_0F3A15 */
7249 {
7250 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7251 },
7252
7253 /* VEX_LEN_0F3A16 */
7254 {
7255 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7256 },
7257
7258 /* VEX_LEN_0F3A17 */
7259 {
7260 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7261 },
7262
7263 /* VEX_LEN_0F3A18 */
7264 {
7265 { Bad_Opcode },
7266 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7267 },
7268
7269 /* VEX_LEN_0F3A19 */
7270 {
7271 { Bad_Opcode },
7272 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7273 },
7274
7275 /* VEX_LEN_0F3A20 */
7276 {
7277 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7278 },
7279
7280 /* VEX_LEN_0F3A21 */
7281 {
7282 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7283 },
7284
7285 /* VEX_LEN_0F3A22 */
7286 {
7287 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7288 },
7289
7290 /* VEX_LEN_0F3A30 */
7291 {
7292 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7293 },
7294
7295 /* VEX_LEN_0F3A31 */
7296 {
7297 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7298 },
7299
7300 /* VEX_LEN_0F3A32 */
7301 {
7302 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7303 },
7304
7305 /* VEX_LEN_0F3A33 */
7306 {
7307 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7308 },
7309
7310 /* VEX_LEN_0F3A38 */
7311 {
7312 { Bad_Opcode },
7313 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7314 },
7315
7316 /* VEX_LEN_0F3A39 */
7317 {
7318 { Bad_Opcode },
7319 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7320 },
7321
7322 /* VEX_LEN_0F3A41 */
7323 {
7324 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7325 },
7326
7327 /* VEX_LEN_0F3A46 */
7328 {
7329 { Bad_Opcode },
7330 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7331 },
7332
7333 /* VEX_LEN_0F3A60 */
7334 {
7335 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7336 },
7337
7338 /* VEX_LEN_0F3A61 */
7339 {
7340 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7341 },
7342
7343 /* VEX_LEN_0F3A62 */
7344 {
7345 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7346 },
7347
7348 /* VEX_LEN_0F3A63 */
7349 {
7350 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7351 },
7352
7353 /* VEX_LEN_0F3ADE_W_0 */
7354 {
7355 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7356 },
7357
7358 /* VEX_LEN_0F3ADF */
7359 {
7360 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7361 },
7362
7363 /* VEX_LEN_0F3AF0 */
7364 {
7365 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7366 },
7367
7368 /* VEX_LEN_MAP7_F8 */
7369 {
7370 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7371 },
7372
7373 /* VEX_LEN_XOP_08_85 */
7374 {
7375 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7376 },
7377
7378 /* VEX_LEN_XOP_08_86 */
7379 {
7380 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7381 },
7382
7383 /* VEX_LEN_XOP_08_87 */
7384 {
7385 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7386 },
7387
7388 /* VEX_LEN_XOP_08_8E */
7389 {
7390 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7391 },
7392
7393 /* VEX_LEN_XOP_08_8F */
7394 {
7395 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7396 },
7397
7398 /* VEX_LEN_XOP_08_95 */
7399 {
7400 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7401 },
7402
7403 /* VEX_LEN_XOP_08_96 */
7404 {
7405 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7406 },
7407
7408 /* VEX_LEN_XOP_08_97 */
7409 {
7410 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7411 },
7412
7413 /* VEX_LEN_XOP_08_9E */
7414 {
7415 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7416 },
7417
7418 /* VEX_LEN_XOP_08_9F */
7419 {
7420 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7421 },
7422
7423 /* VEX_LEN_XOP_08_A3 */
7424 {
7425 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7426 },
7427
7428 /* VEX_LEN_XOP_08_A6 */
7429 {
7430 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7431 },
7432
7433 /* VEX_LEN_XOP_08_B6 */
7434 {
7435 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7436 },
7437
7438 /* VEX_LEN_XOP_08_C0 */
7439 {
7440 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7441 },
7442
7443 /* VEX_LEN_XOP_08_C1 */
7444 {
7445 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7446 },
7447
7448 /* VEX_LEN_XOP_08_C2 */
7449 {
7450 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7451 },
7452
7453 /* VEX_LEN_XOP_08_C3 */
7454 {
7455 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7456 },
7457
7458 /* VEX_LEN_XOP_08_CC */
7459 {
7460 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7461 },
7462
7463 /* VEX_LEN_XOP_08_CD */
7464 {
7465 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7466 },
7467
7468 /* VEX_LEN_XOP_08_CE */
7469 {
7470 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7471 },
7472
7473 /* VEX_LEN_XOP_08_CF */
7474 {
7475 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7476 },
7477
7478 /* VEX_LEN_XOP_08_EC */
7479 {
7480 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7481 },
7482
7483 /* VEX_LEN_XOP_08_ED */
7484 {
7485 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7486 },
7487
7488 /* VEX_LEN_XOP_08_EE */
7489 {
7490 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7491 },
7492
7493 /* VEX_LEN_XOP_08_EF */
7494 {
7495 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7496 },
7497
7498 /* VEX_LEN_XOP_09_01 */
7499 {
7500 { REG_TABLE (REG_XOP_09_01_L_0) },
7501 },
7502
7503 /* VEX_LEN_XOP_09_02 */
7504 {
7505 { REG_TABLE (REG_XOP_09_02_L_0) },
7506 },
7507
7508 /* VEX_LEN_XOP_09_12 */
7509 {
7510 { REG_TABLE (REG_XOP_09_12_L_0) },
7511 },
7512
7513 /* VEX_LEN_XOP_09_82_W_0 */
7514 {
7515 { "vfrczss", { XM, EXd }, 0 },
7516 },
7517
7518 /* VEX_LEN_XOP_09_83_W_0 */
7519 {
7520 { "vfrczsd", { XM, EXq }, 0 },
7521 },
7522
7523 /* VEX_LEN_XOP_09_90 */
7524 {
7525 { "vprotb", { XM, EXx, VexW }, 0 },
7526 },
7527
7528 /* VEX_LEN_XOP_09_91 */
7529 {
7530 { "vprotw", { XM, EXx, VexW }, 0 },
7531 },
7532
7533 /* VEX_LEN_XOP_09_92 */
7534 {
7535 { "vprotd", { XM, EXx, VexW }, 0 },
7536 },
7537
7538 /* VEX_LEN_XOP_09_93 */
7539 {
7540 { "vprotq", { XM, EXx, VexW }, 0 },
7541 },
7542
7543 /* VEX_LEN_XOP_09_94 */
7544 {
7545 { "vpshlb", { XM, EXx, VexW }, 0 },
7546 },
7547
7548 /* VEX_LEN_XOP_09_95 */
7549 {
7550 { "vpshlw", { XM, EXx, VexW }, 0 },
7551 },
7552
7553 /* VEX_LEN_XOP_09_96 */
7554 {
7555 { "vpshld", { XM, EXx, VexW }, 0 },
7556 },
7557
7558 /* VEX_LEN_XOP_09_97 */
7559 {
7560 { "vpshlq", { XM, EXx, VexW }, 0 },
7561 },
7562
7563 /* VEX_LEN_XOP_09_98 */
7564 {
7565 { "vpshab", { XM, EXx, VexW }, 0 },
7566 },
7567
7568 /* VEX_LEN_XOP_09_99 */
7569 {
7570 { "vpshaw", { XM, EXx, VexW }, 0 },
7571 },
7572
7573 /* VEX_LEN_XOP_09_9A */
7574 {
7575 { "vpshad", { XM, EXx, VexW }, 0 },
7576 },
7577
7578 /* VEX_LEN_XOP_09_9B */
7579 {
7580 { "vpshaq", { XM, EXx, VexW }, 0 },
7581 },
7582
7583 /* VEX_LEN_XOP_09_C1 */
7584 {
7585 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7586 },
7587
7588 /* VEX_LEN_XOP_09_C2 */
7589 {
7590 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7591 },
7592
7593 /* VEX_LEN_XOP_09_C3 */
7594 {
7595 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7596 },
7597
7598 /* VEX_LEN_XOP_09_C6 */
7599 {
7600 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7601 },
7602
7603 /* VEX_LEN_XOP_09_C7 */
7604 {
7605 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7606 },
7607
7608 /* VEX_LEN_XOP_09_CB */
7609 {
7610 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7611 },
7612
7613 /* VEX_LEN_XOP_09_D1 */
7614 {
7615 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7616 },
7617
7618 /* VEX_LEN_XOP_09_D2 */
7619 {
7620 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7621 },
7622
7623 /* VEX_LEN_XOP_09_D3 */
7624 {
7625 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7626 },
7627
7628 /* VEX_LEN_XOP_09_D6 */
7629 {
7630 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7631 },
7632
7633 /* VEX_LEN_XOP_09_D7 */
7634 {
7635 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7636 },
7637
7638 /* VEX_LEN_XOP_09_DB */
7639 {
7640 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7641 },
7642
7643 /* VEX_LEN_XOP_09_E1 */
7644 {
7645 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7646 },
7647
7648 /* VEX_LEN_XOP_09_E2 */
7649 {
7650 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7651 },
7652
7653 /* VEX_LEN_XOP_09_E3 */
7654 {
7655 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7656 },
7657
7658 /* VEX_LEN_XOP_0A_12 */
7659 {
7660 { REG_TABLE (REG_XOP_0A_12_L_0) },
7661 },
7662 };
7663
7664 #include "i386-dis-evex-len.h"
7665
7666 static const struct dis386 vex_w_table[][2] = {
7667 {
7668 /* VEX_W_0F41_L_1_M_1 */
7669 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7671 },
7672 {
7673 /* VEX_W_0F42_L_1_M_1 */
7674 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7676 },
7677 {
7678 /* VEX_W_0F44_L_0_M_1 */
7679 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7680 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7681 },
7682 {
7683 /* VEX_W_0F45_L_1_M_1 */
7684 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7686 },
7687 {
7688 /* VEX_W_0F46_L_1_M_1 */
7689 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7690 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7691 },
7692 {
7693 /* VEX_W_0F47_L_1_M_1 */
7694 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7695 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7696 },
7697 {
7698 /* VEX_W_0F4A_L_1_M_1 */
7699 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7700 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7701 },
7702 {
7703 /* VEX_W_0F4B_L_1_M_1 */
7704 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7705 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7706 },
7707 {
7708 /* VEX_W_0F90_L_0 */
7709 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7710 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7711 },
7712 {
7713 /* VEX_W_0F91_L_0_M_0 */
7714 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7715 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7716 },
7717 {
7718 /* VEX_W_0F92_L_0_M_1 */
7719 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7720 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7721 },
7722 {
7723 /* VEX_W_0F93_L_0_M_1 */
7724 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7725 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7726 },
7727 {
7728 /* VEX_W_0F98_L_0_M_1 */
7729 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7730 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7731 },
7732 {
7733 /* VEX_W_0F99_L_0_M_1 */
7734 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7735 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7736 },
7737 {
7738 /* VEX_W_0F380C */
7739 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7740 },
7741 {
7742 /* VEX_W_0F380D */
7743 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7744 },
7745 {
7746 /* VEX_W_0F380E */
7747 { "vtestps", { XM, EXx }, PREFIX_DATA },
7748 },
7749 {
7750 /* VEX_W_0F380F */
7751 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7752 },
7753 {
7754 /* VEX_W_0F3813 */
7755 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7756 },
7757 {
7758 /* VEX_W_0F3816_L_1 */
7759 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7760 },
7761 {
7762 /* VEX_W_0F3818 */
7763 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7764 },
7765 {
7766 /* VEX_W_0F3819_L_1 */
7767 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7768 },
7769 {
7770 /* VEX_W_0F381A_L_1 */
7771 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7772 },
7773 {
7774 /* VEX_W_0F382C */
7775 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7776 },
7777 {
7778 /* VEX_W_0F382D */
7779 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7780 },
7781 {
7782 /* VEX_W_0F382E */
7783 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7784 },
7785 {
7786 /* VEX_W_0F382F */
7787 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7788 },
7789 {
7790 /* VEX_W_0F3836 */
7791 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7792 },
7793 {
7794 /* VEX_W_0F3846 */
7795 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7796 },
7797 {
7798 /* VEX_W_0F3849_X86_64_L_0 */
7799 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7800 },
7801 {
7802 /* VEX_W_0F384B_X86_64_L_0 */
7803 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7804 },
7805 {
7806 /* VEX_W_0F3850 */
7807 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7808 },
7809 {
7810 /* VEX_W_0F3851 */
7811 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7812 },
7813 {
7814 /* VEX_W_0F3852 */
7815 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7816 },
7817 {
7818 /* VEX_W_0F3853 */
7819 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7820 },
7821 {
7822 /* VEX_W_0F3858 */
7823 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7824 },
7825 {
7826 /* VEX_W_0F3859 */
7827 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7828 },
7829 {
7830 /* VEX_W_0F385A_L_0 */
7831 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7832 },
7833 {
7834 /* VEX_W_0F385C_X86_64_L_0 */
7835 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7836 },
7837 {
7838 /* VEX_W_0F385E_X86_64_L_0 */
7839 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7840 },
7841 {
7842 /* VEX_W_0F386C_X86_64_L_0 */
7843 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7844 },
7845 {
7846 /* VEX_W_0F3872_P_1 */
7847 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7848 },
7849 {
7850 /* VEX_W_0F3878 */
7851 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7852 },
7853 {
7854 /* VEX_W_0F3879 */
7855 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7856 },
7857 {
7858 /* VEX_W_0F38B0 */
7859 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7860 },
7861 {
7862 /* VEX_W_0F38B1 */
7863 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7864 },
7865 {
7866 /* VEX_W_0F38B4 */
7867 { Bad_Opcode },
7868 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7869 },
7870 {
7871 /* VEX_W_0F38B5 */
7872 { Bad_Opcode },
7873 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7874 },
7875 {
7876 /* VEX_W_0F38CB_P_3 */
7877 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7878 },
7879 {
7880 /* VEX_W_0F38CC_P_3 */
7881 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7882 },
7883 {
7884 /* VEX_W_0F38CD_P_3 */
7885 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7886 },
7887 {
7888 /* VEX_W_0F38CF */
7889 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7890 },
7891 {
7892 /* VEX_W_0F38D2 */
7893 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7894 },
7895 {
7896 /* VEX_W_0F38D3 */
7897 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7898 },
7899 {
7900 /* VEX_W_0F38DA */
7901 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7902 },
7903 {
7904 /* VEX_W_0F3A00_L_1 */
7905 { Bad_Opcode },
7906 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7907 },
7908 {
7909 /* VEX_W_0F3A01_L_1 */
7910 { Bad_Opcode },
7911 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7912 },
7913 {
7914 /* VEX_W_0F3A02 */
7915 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7916 },
7917 {
7918 /* VEX_W_0F3A04 */
7919 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7920 },
7921 {
7922 /* VEX_W_0F3A05 */
7923 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7924 },
7925 {
7926 /* VEX_W_0F3A06_L_1 */
7927 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7928 },
7929 {
7930 /* VEX_W_0F3A18_L_1 */
7931 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7932 },
7933 {
7934 /* VEX_W_0F3A19_L_1 */
7935 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7936 },
7937 {
7938 /* VEX_W_0F3A1D */
7939 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7940 },
7941 {
7942 /* VEX_W_0F3A38_L_1 */
7943 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7944 },
7945 {
7946 /* VEX_W_0F3A39_L_1 */
7947 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7948 },
7949 {
7950 /* VEX_W_0F3A46_L_1 */
7951 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7952 },
7953 {
7954 /* VEX_W_0F3A4A */
7955 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7956 },
7957 {
7958 /* VEX_W_0F3A4B */
7959 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7960 },
7961 {
7962 /* VEX_W_0F3A4C */
7963 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7964 },
7965 {
7966 /* VEX_W_0F3ACE */
7967 { Bad_Opcode },
7968 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7969 },
7970 {
7971 /* VEX_W_0F3ACF */
7972 { Bad_Opcode },
7973 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7974 },
7975 {
7976 /* VEX_W_0F3ADE */
7977 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7978 },
7979 {
7980 /* VEX_W_MAP7_F8_L_0 */
7981 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7982 },
7983 /* VEX_W_XOP_08_85_L_0 */
7984 {
7985 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7986 },
7987 /* VEX_W_XOP_08_86_L_0 */
7988 {
7989 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7990 },
7991 /* VEX_W_XOP_08_87_L_0 */
7992 {
7993 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7994 },
7995 /* VEX_W_XOP_08_8E_L_0 */
7996 {
7997 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7998 },
7999 /* VEX_W_XOP_08_8F_L_0 */
8000 {
8001 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8002 },
8003 /* VEX_W_XOP_08_95_L_0 */
8004 {
8005 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
8006 },
8007 /* VEX_W_XOP_08_96_L_0 */
8008 {
8009 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8010 },
8011 /* VEX_W_XOP_08_97_L_0 */
8012 {
8013 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8014 },
8015 /* VEX_W_XOP_08_9E_L_0 */
8016 {
8017 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8018 },
8019 /* VEX_W_XOP_08_9F_L_0 */
8020 {
8021 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8022 },
8023 /* VEX_W_XOP_08_A6_L_0 */
8024 {
8025 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8026 },
8027 /* VEX_W_XOP_08_B6_L_0 */
8028 {
8029 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8030 },
8031 /* VEX_W_XOP_08_C0_L_0 */
8032 {
8033 { "vprotb", { XM, EXx, Ib }, 0 },
8034 },
8035 /* VEX_W_XOP_08_C1_L_0 */
8036 {
8037 { "vprotw", { XM, EXx, Ib }, 0 },
8038 },
8039 /* VEX_W_XOP_08_C2_L_0 */
8040 {
8041 { "vprotd", { XM, EXx, Ib }, 0 },
8042 },
8043 /* VEX_W_XOP_08_C3_L_0 */
8044 {
8045 { "vprotq", { XM, EXx, Ib }, 0 },
8046 },
8047 /* VEX_W_XOP_08_CC_L_0 */
8048 {
8049 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8050 },
8051 /* VEX_W_XOP_08_CD_L_0 */
8052 {
8053 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8054 },
8055 /* VEX_W_XOP_08_CE_L_0 */
8056 {
8057 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8058 },
8059 /* VEX_W_XOP_08_CF_L_0 */
8060 {
8061 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8062 },
8063 /* VEX_W_XOP_08_EC_L_0 */
8064 {
8065 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8066 },
8067 /* VEX_W_XOP_08_ED_L_0 */
8068 {
8069 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8070 },
8071 /* VEX_W_XOP_08_EE_L_0 */
8072 {
8073 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8074 },
8075 /* VEX_W_XOP_08_EF_L_0 */
8076 {
8077 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8078 },
8079 /* VEX_W_XOP_09_80 */
8080 {
8081 { "vfrczps", { XM, EXx }, 0 },
8082 },
8083 /* VEX_W_XOP_09_81 */
8084 {
8085 { "vfrczpd", { XM, EXx }, 0 },
8086 },
8087 /* VEX_W_XOP_09_82 */
8088 {
8089 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8090 },
8091 /* VEX_W_XOP_09_83 */
8092 {
8093 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8094 },
8095 /* VEX_W_XOP_09_C1_L_0 */
8096 {
8097 { "vphaddbw", { XM, EXxmm }, 0 },
8098 },
8099 /* VEX_W_XOP_09_C2_L_0 */
8100 {
8101 { "vphaddbd", { XM, EXxmm }, 0 },
8102 },
8103 /* VEX_W_XOP_09_C3_L_0 */
8104 {
8105 { "vphaddbq", { XM, EXxmm }, 0 },
8106 },
8107 /* VEX_W_XOP_09_C6_L_0 */
8108 {
8109 { "vphaddwd", { XM, EXxmm }, 0 },
8110 },
8111 /* VEX_W_XOP_09_C7_L_0 */
8112 {
8113 { "vphaddwq", { XM, EXxmm }, 0 },
8114 },
8115 /* VEX_W_XOP_09_CB_L_0 */
8116 {
8117 { "vphadddq", { XM, EXxmm }, 0 },
8118 },
8119 /* VEX_W_XOP_09_D1_L_0 */
8120 {
8121 { "vphaddubw", { XM, EXxmm }, 0 },
8122 },
8123 /* VEX_W_XOP_09_D2_L_0 */
8124 {
8125 { "vphaddubd", { XM, EXxmm }, 0 },
8126 },
8127 /* VEX_W_XOP_09_D3_L_0 */
8128 {
8129 { "vphaddubq", { XM, EXxmm }, 0 },
8130 },
8131 /* VEX_W_XOP_09_D6_L_0 */
8132 {
8133 { "vphadduwd", { XM, EXxmm }, 0 },
8134 },
8135 /* VEX_W_XOP_09_D7_L_0 */
8136 {
8137 { "vphadduwq", { XM, EXxmm }, 0 },
8138 },
8139 /* VEX_W_XOP_09_DB_L_0 */
8140 {
8141 { "vphaddudq", { XM, EXxmm }, 0 },
8142 },
8143 /* VEX_W_XOP_09_E1_L_0 */
8144 {
8145 { "vphsubbw", { XM, EXxmm }, 0 },
8146 },
8147 /* VEX_W_XOP_09_E2_L_0 */
8148 {
8149 { "vphsubwd", { XM, EXxmm }, 0 },
8150 },
8151 /* VEX_W_XOP_09_E3_L_0 */
8152 {
8153 { "vphsubdq", { XM, EXxmm }, 0 },
8154 },
8155
8156 #include "i386-dis-evex-w.h"
8157 };
8158
8159 static const struct dis386 mod_table[][2] = {
8160 {
8161 /* MOD_62_32BIT */
8162 { "bound{S|}", { Gv, Ma }, 0 },
8163 { EVEX_TABLE () },
8164 },
8165 {
8166 /* MOD_C4_32BIT */
8167 { "lesS", { Gv, Mp }, 0 },
8168 { VEX_C4_TABLE () },
8169 },
8170 {
8171 /* MOD_C5_32BIT */
8172 { "ldsS", { Gv, Mp }, 0 },
8173 { VEX_C5_TABLE () },
8174 },
8175 {
8176 /* MOD_0F01_REG_0 */
8177 { X86_64_TABLE (X86_64_0F01_REG_0) },
8178 { RM_TABLE (RM_0F01_REG_0) },
8179 },
8180 {
8181 /* MOD_0F01_REG_1 */
8182 { X86_64_TABLE (X86_64_0F01_REG_1) },
8183 { RM_TABLE (RM_0F01_REG_1) },
8184 },
8185 {
8186 /* MOD_0F01_REG_2 */
8187 { X86_64_TABLE (X86_64_0F01_REG_2) },
8188 { RM_TABLE (RM_0F01_REG_2) },
8189 },
8190 {
8191 /* MOD_0F01_REG_3 */
8192 { X86_64_TABLE (X86_64_0F01_REG_3) },
8193 { RM_TABLE (RM_0F01_REG_3) },
8194 },
8195 {
8196 /* MOD_0F01_REG_5 */
8197 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8198 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8199 },
8200 {
8201 /* MOD_0F01_REG_7 */
8202 { "invlpg", { Mb }, 0 },
8203 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8204 },
8205 {
8206 /* MOD_0F12_PREFIX_0 */
8207 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8208 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8209 },
8210 {
8211 /* MOD_0F16_PREFIX_0 */
8212 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8213 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8214 },
8215 {
8216 /* MOD_0F18_REG_0 */
8217 { "prefetchnta", { Mb }, 0 },
8218 { "nopQ", { Ev }, 0 },
8219 },
8220 {
8221 /* MOD_0F18_REG_1 */
8222 { "prefetcht0", { Mb }, 0 },
8223 { "nopQ", { Ev }, 0 },
8224 },
8225 {
8226 /* MOD_0F18_REG_2 */
8227 { "prefetcht1", { Mb }, 0 },
8228 { "nopQ", { Ev }, 0 },
8229 },
8230 {
8231 /* MOD_0F18_REG_3 */
8232 { "prefetcht2", { Mb }, 0 },
8233 { "nopQ", { Ev }, 0 },
8234 },
8235 {
8236 /* MOD_0F18_REG_6 */
8237 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8238 { "nopQ", { Ev }, 0 },
8239 },
8240 {
8241 /* MOD_0F18_REG_7 */
8242 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8243 { "nopQ", { Ev }, 0 },
8244 },
8245 {
8246 /* MOD_0F1A_PREFIX_0 */
8247 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8248 { "nopQ", { Ev }, 0 },
8249 },
8250 {
8251 /* MOD_0F1B_PREFIX_0 */
8252 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8253 { "nopQ", { Ev }, 0 },
8254 },
8255 {
8256 /* MOD_0F1B_PREFIX_1 */
8257 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8258 { "nopQ", { Ev }, PREFIX_IGNORED },
8259 },
8260 {
8261 /* MOD_0F1C_PREFIX_0 */
8262 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8263 { "nopQ", { Ev }, 0 },
8264 },
8265 {
8266 /* MOD_0F1E_PREFIX_1 */
8267 { "nopQ", { Ev }, PREFIX_IGNORED },
8268 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8269 },
8270 {
8271 /* MOD_0FAE_REG_0 */
8272 { "fxsave", { FXSAVE }, 0 },
8273 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8274 },
8275 {
8276 /* MOD_0FAE_REG_1 */
8277 { "fxrstor", { FXSAVE }, 0 },
8278 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8279 },
8280 {
8281 /* MOD_0FAE_REG_2 */
8282 { "ldmxcsr", { Md }, 0 },
8283 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8284 },
8285 {
8286 /* MOD_0FAE_REG_3 */
8287 { "stmxcsr", { Md }, 0 },
8288 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8289 },
8290 {
8291 /* MOD_0FAE_REG_4 */
8292 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8293 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8294 },
8295 {
8296 /* MOD_0FAE_REG_5 */
8297 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8298 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8299 },
8300 {
8301 /* MOD_0FAE_REG_6 */
8302 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8303 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8304 },
8305 {
8306 /* MOD_0FAE_REG_7 */
8307 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8308 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8309 },
8310 {
8311 /* MOD_0FC7_REG_6 */
8312 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8313 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8314 },
8315 {
8316 /* MOD_0FC7_REG_7 */
8317 { "vmptrst", { Mq }, 0 },
8318 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8319 },
8320 {
8321 /* MOD_0F38DC_PREFIX_1 */
8322 { "aesenc128kl", { XM, M }, 0 },
8323 { "loadiwkey", { XM, EXx }, 0 },
8324 },
8325 /* MOD_0F38F8 */
8326 {
8327 { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8328 { X86_64_TABLE (X86_64_0F38F8_M_1) },
8329 },
8330 {
8331 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8332 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8333 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8334 },
8335
8336 #include "i386-dis-evex-mod.h"
8337 };
8338
8339 static const struct dis386 rm_table[][8] = {
8340 {
8341 /* RM_C6_REG_7 */
8342 { "xabort", { Skip_MODRM, Ib }, 0 },
8343 },
8344 {
8345 /* RM_C7_REG_7 */
8346 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8347 },
8348 {
8349 /* RM_0F01_REG_0 */
8350 { "enclv", { Skip_MODRM }, 0 },
8351 { "vmcall", { Skip_MODRM }, 0 },
8352 { "vmlaunch", { Skip_MODRM }, 0 },
8353 { "vmresume", { Skip_MODRM }, 0 },
8354 { "vmxoff", { Skip_MODRM }, 0 },
8355 { "pconfig", { Skip_MODRM }, 0 },
8356 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8357 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8358 },
8359 {
8360 /* RM_0F01_REG_1 */
8361 { "monitor", { { OP_Monitor, 0 } }, 0 },
8362 { "mwait", { { OP_Mwait, 0 } }, 0 },
8363 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8364 { "stac", { Skip_MODRM }, 0 },
8365 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8366 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8367 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8368 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8369 },
8370 {
8371 /* RM_0F01_REG_2 */
8372 { "xgetbv", { Skip_MODRM }, 0 },
8373 { "xsetbv", { Skip_MODRM }, 0 },
8374 { Bad_Opcode },
8375 { Bad_Opcode },
8376 { "vmfunc", { Skip_MODRM }, 0 },
8377 { "xend", { Skip_MODRM }, 0 },
8378 { "xtest", { Skip_MODRM }, 0 },
8379 { "enclu", { Skip_MODRM }, 0 },
8380 },
8381 {
8382 /* RM_0F01_REG_3 */
8383 { "vmrun", { Skip_MODRM }, 0 },
8384 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8385 { "vmload", { Skip_MODRM }, 0 },
8386 { "vmsave", { Skip_MODRM }, 0 },
8387 { "stgi", { Skip_MODRM }, 0 },
8388 { "clgi", { Skip_MODRM }, 0 },
8389 { "skinit", { Skip_MODRM }, 0 },
8390 { "invlpga", { Skip_MODRM }, 0 },
8391 },
8392 {
8393 /* RM_0F01_REG_5_MOD_3 */
8394 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8395 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8396 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8397 { Bad_Opcode },
8398 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8399 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8400 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8401 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8402 },
8403 {
8404 /* RM_0F01_REG_7_MOD_3 */
8405 { "swapgs", { Skip_MODRM }, 0 },
8406 { "rdtscp", { Skip_MODRM }, 0 },
8407 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8408 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8409 { "clzero", { Skip_MODRM }, 0 },
8410 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8411 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8412 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8413 },
8414 {
8415 /* RM_0F1E_P_1_MOD_3_REG_7 */
8416 { "nopQ", { Ev }, PREFIX_IGNORED },
8417 { "nopQ", { Ev }, PREFIX_IGNORED },
8418 { "endbr64", { Skip_MODRM }, 0 },
8419 { "endbr32", { Skip_MODRM }, 0 },
8420 { "nopQ", { Ev }, PREFIX_IGNORED },
8421 { "nopQ", { Ev }, PREFIX_IGNORED },
8422 { "nopQ", { Ev }, PREFIX_IGNORED },
8423 { "nopQ", { Ev }, PREFIX_IGNORED },
8424 },
8425 {
8426 /* RM_0FAE_REG_6_MOD_3 */
8427 { "mfence", { Skip_MODRM }, 0 },
8428 },
8429 {
8430 /* RM_0FAE_REG_7_MOD_3 */
8431 { "sfence", { Skip_MODRM }, 0 },
8432 },
8433 {
8434 /* RM_0F3A0F_P_1_R_0 */
8435 { "hreset", { Skip_MODRM, Ib }, 0 },
8436 },
8437 {
8438 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8439 { "tilerelease", { Skip_MODRM }, 0 },
8440 },
8441 {
8442 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8443 { "tilezero", { TMM, Skip_MODRM }, 0 },
8444 },
8445 };
8446
8447 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8448
8449 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8450 in conflict with actual prefix opcodes. */
8451 #define REP_PREFIX 0x01
8452 #define XACQUIRE_PREFIX 0x02
8453 #define XRELEASE_PREFIX 0x03
8454 #define BND_PREFIX 0x04
8455 #define NOTRACK_PREFIX 0x05
8456
8457 static enum {
8458 ckp_okay,
8459 ckp_bogus,
8460 ckp_fetch_error,
8461 }
ckprefix(instr_info * ins)8462 ckprefix (instr_info *ins)
8463 {
8464 int i, length;
8465 uint8_t newrex;
8466
8467 i = 0;
8468 length = 0;
8469 /* The maximum instruction length is 15bytes. */
8470 while (length < MAX_CODE_LENGTH - 1)
8471 {
8472 if (!fetch_code (ins->info, ins->codep + 1))
8473 return ckp_fetch_error;
8474 newrex = 0;
8475 switch (*ins->codep)
8476 {
8477 /* REX prefixes family. */
8478 case 0x40:
8479 case 0x41:
8480 case 0x42:
8481 case 0x43:
8482 case 0x44:
8483 case 0x45:
8484 case 0x46:
8485 case 0x47:
8486 case 0x48:
8487 case 0x49:
8488 case 0x4a:
8489 case 0x4b:
8490 case 0x4c:
8491 case 0x4d:
8492 case 0x4e:
8493 case 0x4f:
8494 if (ins->address_mode == mode_64bit)
8495 newrex = *ins->codep;
8496 else
8497 return ckp_okay;
8498 ins->last_rex_prefix = i;
8499 break;
8500 /* REX2 must be the last prefix. */
8501 case REX2_OPCODE:
8502 if (ins->address_mode == mode_64bit)
8503 {
8504 if (ins->last_rex_prefix >= 0)
8505 return ckp_bogus;
8506
8507 ins->codep++;
8508 if (!fetch_code (ins->info, ins->codep + 1))
8509 return ckp_fetch_error;
8510 ins->rex2_payload = *ins->codep;
8511 ins->rex2 = ins->rex2_payload >> 4;
8512 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8513 ins->codep++;
8514 ins->last_rex2_prefix = i;
8515 ins->all_prefixes[i] = REX2_OPCODE;
8516 }
8517 return ckp_okay;
8518 case 0xf3:
8519 ins->prefixes |= PREFIX_REPZ;
8520 ins->last_repz_prefix = i;
8521 break;
8522 case 0xf2:
8523 ins->prefixes |= PREFIX_REPNZ;
8524 ins->last_repnz_prefix = i;
8525 break;
8526 case 0xf0:
8527 ins->prefixes |= PREFIX_LOCK;
8528 ins->last_lock_prefix = i;
8529 break;
8530 case 0x2e:
8531 ins->prefixes |= PREFIX_CS;
8532 ins->last_seg_prefix = i;
8533 if (ins->address_mode != mode_64bit)
8534 ins->active_seg_prefix = PREFIX_CS;
8535 break;
8536 case 0x36:
8537 ins->prefixes |= PREFIX_SS;
8538 ins->last_seg_prefix = i;
8539 if (ins->address_mode != mode_64bit)
8540 ins->active_seg_prefix = PREFIX_SS;
8541 break;
8542 case 0x3e:
8543 ins->prefixes |= PREFIX_DS;
8544 ins->last_seg_prefix = i;
8545 if (ins->address_mode != mode_64bit)
8546 ins->active_seg_prefix = PREFIX_DS;
8547 break;
8548 case 0x26:
8549 ins->prefixes |= PREFIX_ES;
8550 ins->last_seg_prefix = i;
8551 if (ins->address_mode != mode_64bit)
8552 ins->active_seg_prefix = PREFIX_ES;
8553 break;
8554 case 0x64:
8555 ins->prefixes |= PREFIX_FS;
8556 ins->last_seg_prefix = i;
8557 ins->active_seg_prefix = PREFIX_FS;
8558 break;
8559 case 0x65:
8560 ins->prefixes |= PREFIX_GS;
8561 ins->last_seg_prefix = i;
8562 ins->active_seg_prefix = PREFIX_GS;
8563 break;
8564 case 0x66:
8565 ins->prefixes |= PREFIX_DATA;
8566 ins->last_data_prefix = i;
8567 break;
8568 case 0x67:
8569 ins->prefixes |= PREFIX_ADDR;
8570 ins->last_addr_prefix = i;
8571 break;
8572 case FWAIT_OPCODE:
8573 /* fwait is really an instruction. If there are prefixes
8574 before the fwait, they belong to the fwait, *not* to the
8575 following instruction. */
8576 ins->fwait_prefix = i;
8577 if (ins->prefixes || ins->rex)
8578 {
8579 ins->prefixes |= PREFIX_FWAIT;
8580 ins->codep++;
8581 /* This ensures that the previous REX prefixes are noticed
8582 as unused prefixes, as in the return case below. */
8583 return ins->rex ? ckp_bogus : ckp_okay;
8584 }
8585 ins->prefixes = PREFIX_FWAIT;
8586 break;
8587 default:
8588 return ckp_okay;
8589 }
8590 /* Rex is ignored when followed by another prefix. */
8591 if (ins->rex)
8592 return ckp_bogus;
8593 if (*ins->codep != FWAIT_OPCODE)
8594 ins->all_prefixes[i++] = *ins->codep;
8595 ins->rex = newrex;
8596 ins->codep++;
8597 length++;
8598 }
8599 return ckp_bogus;
8600 }
8601
8602 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8603 prefix byte. */
8604
8605 static const char *
prefix_name(enum address_mode mode,uint8_t pref,int sizeflag)8606 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8607 {
8608 static const char *rexes [16] =
8609 {
8610 "rex", /* 0x40 */
8611 "rex.B", /* 0x41 */
8612 "rex.X", /* 0x42 */
8613 "rex.XB", /* 0x43 */
8614 "rex.R", /* 0x44 */
8615 "rex.RB", /* 0x45 */
8616 "rex.RX", /* 0x46 */
8617 "rex.RXB", /* 0x47 */
8618 "rex.W", /* 0x48 */
8619 "rex.WB", /* 0x49 */
8620 "rex.WX", /* 0x4a */
8621 "rex.WXB", /* 0x4b */
8622 "rex.WR", /* 0x4c */
8623 "rex.WRB", /* 0x4d */
8624 "rex.WRX", /* 0x4e */
8625 "rex.WRXB", /* 0x4f */
8626 };
8627
8628 switch (pref)
8629 {
8630 /* REX prefixes family. */
8631 case 0x40:
8632 case 0x41:
8633 case 0x42:
8634 case 0x43:
8635 case 0x44:
8636 case 0x45:
8637 case 0x46:
8638 case 0x47:
8639 case 0x48:
8640 case 0x49:
8641 case 0x4a:
8642 case 0x4b:
8643 case 0x4c:
8644 case 0x4d:
8645 case 0x4e:
8646 case 0x4f:
8647 return rexes [pref - 0x40];
8648 case 0xf3:
8649 return "repz";
8650 case 0xf2:
8651 return "repnz";
8652 case 0xf0:
8653 return "lock";
8654 case 0x2e:
8655 return "cs";
8656 case 0x36:
8657 return "ss";
8658 case 0x3e:
8659 return "ds";
8660 case 0x26:
8661 return "es";
8662 case 0x64:
8663 return "fs";
8664 case 0x65:
8665 return "gs";
8666 case 0x66:
8667 return (sizeflag & DFLAG) ? "data16" : "data32";
8668 case 0x67:
8669 if (mode == mode_64bit)
8670 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8671 else
8672 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8673 case FWAIT_OPCODE:
8674 return "fwait";
8675 case REP_PREFIX:
8676 return "rep";
8677 case XACQUIRE_PREFIX:
8678 return "xacquire";
8679 case XRELEASE_PREFIX:
8680 return "xrelease";
8681 case BND_PREFIX:
8682 return "bnd";
8683 case NOTRACK_PREFIX:
8684 return "notrack";
8685 case REX2_OPCODE:
8686 return "rex2";
8687 default:
8688 return NULL;
8689 }
8690 }
8691
8692 void
print_i386_disassembler_options(FILE * stream)8693 print_i386_disassembler_options (FILE *stream)
8694 {
8695 fprintf (stream, _("\n\
8696 The following i386/x86-64 specific disassembler options are supported for use\n\
8697 with the -M switch (multiple options should be separated by commas):\n"));
8698
8699 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8700 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8701 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8702 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8703 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8704 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n"
8705 " Display instruction with AT&T mnemonic\n"));
8706 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n"
8707 " Display instruction with Intel mnemonic\n"));
8708 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8709 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8710 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8711 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8712 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8713 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8714 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8715 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8716 }
8717
8718 /* Bad opcode. */
8719 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8720
8721 /* Fetch error indicator. */
8722 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8723
8724 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8725
8726 /* Get a pointer to struct dis386 with a valid name. */
8727
8728 static const struct dis386 *
get_valid_dis386(const struct dis386 * dp,instr_info * ins)8729 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8730 {
8731 int vindex, vex_table_index;
8732
8733 if (dp->name != NULL)
8734 return dp;
8735
8736 switch (dp->op[0].bytemode)
8737 {
8738 case USE_REG_TABLE:
8739 dp = ®_table[dp->op[1].bytemode][ins->modrm.reg];
8740 break;
8741
8742 case USE_MOD_TABLE:
8743 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8744 dp = &mod_table[dp->op[1].bytemode][vindex];
8745 break;
8746
8747 case USE_RM_TABLE:
8748 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8749 break;
8750
8751 case USE_PREFIX_TABLE:
8752 use_prefix_table:
8753 if (ins->need_vex)
8754 {
8755 /* The prefix in VEX is implicit. */
8756 switch (ins->vex.prefix)
8757 {
8758 case 0:
8759 vindex = 0;
8760 break;
8761 case REPE_PREFIX_OPCODE:
8762 vindex = 1;
8763 break;
8764 case DATA_PREFIX_OPCODE:
8765 vindex = 2;
8766 break;
8767 case REPNE_PREFIX_OPCODE:
8768 vindex = 3;
8769 break;
8770 default:
8771 abort ();
8772 break;
8773 }
8774 }
8775 else
8776 {
8777 int last_prefix = -1;
8778 int prefix = 0;
8779 vindex = 0;
8780 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8781 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8782 last one wins. */
8783 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8784 {
8785 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8786 {
8787 vindex = 1;
8788 prefix = PREFIX_REPZ;
8789 last_prefix = ins->last_repz_prefix;
8790 }
8791 else
8792 {
8793 vindex = 3;
8794 prefix = PREFIX_REPNZ;
8795 last_prefix = ins->last_repnz_prefix;
8796 }
8797
8798 /* Check if prefix should be ignored. */
8799 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8800 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8801 & prefix) != 0
8802 && !prefix_table[dp->op[1].bytemode][vindex].name)
8803 vindex = 0;
8804 }
8805
8806 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8807 {
8808 vindex = 2;
8809 prefix = PREFIX_DATA;
8810 last_prefix = ins->last_data_prefix;
8811 }
8812
8813 if (vindex != 0)
8814 {
8815 ins->used_prefixes |= prefix;
8816 ins->all_prefixes[last_prefix] = 0;
8817 }
8818 }
8819 dp = &prefix_table[dp->op[1].bytemode][vindex];
8820 break;
8821
8822 case USE_X86_64_EVEX_FROM_VEX_TABLE:
8823 case USE_X86_64_EVEX_PFX_TABLE:
8824 case USE_X86_64_EVEX_W_TABLE:
8825 case USE_X86_64_EVEX_MEM_W_TABLE:
8826 ins->evex_type = evex_from_vex;
8827 /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8828 EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0. */
8829 if (ins->address_mode != mode_64bit
8830 || (ins->vex.mask_register_specifier & 0x3) != 0
8831 || ins->vex.ll != 0
8832 || ins->vex.zeroing != 0
8833 || ins->vex.b)
8834 return &bad_opcode;
8835
8836 if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8837 goto use_prefix_table;
8838 if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8839 goto use_vex_w_table;
8840 if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8841 {
8842 if (ins->modrm.mod == 3)
8843 return &bad_opcode;
8844 goto use_vex_w_table;
8845 }
8846
8847 /* Fall through. */
8848 case USE_X86_64_TABLE:
8849 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8850 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8851 break;
8852
8853 case USE_3BYTE_TABLE:
8854 if (ins->last_rex2_prefix >= 0)
8855 return &err_opcode;
8856 if (!fetch_code (ins->info, ins->codep + 2))
8857 return &err_opcode;
8858 vindex = *ins->codep++;
8859 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8860 ins->end_codep = ins->codep;
8861 if (!fetch_modrm (ins))
8862 return &err_opcode;
8863 break;
8864
8865 case USE_VEX_LEN_TABLE:
8866 if (!ins->need_vex)
8867 abort ();
8868
8869 switch (ins->vex.length)
8870 {
8871 case 128:
8872 vindex = 0;
8873 break;
8874 case 512:
8875 /* This allows re-using in particular table entries where only
8876 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8877 if (ins->vex.evex)
8878 {
8879 case 256:
8880 vindex = 1;
8881 break;
8882 }
8883 /* Fall through. */
8884 default:
8885 abort ();
8886 break;
8887 }
8888
8889 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8890 break;
8891
8892 case USE_EVEX_LEN_TABLE:
8893 if (!ins->vex.evex)
8894 abort ();
8895
8896 switch (ins->vex.length)
8897 {
8898 case 128:
8899 vindex = 0;
8900 break;
8901 case 256:
8902 vindex = 1;
8903 break;
8904 case 512:
8905 vindex = 2;
8906 break;
8907 default:
8908 abort ();
8909 break;
8910 }
8911
8912 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8913 break;
8914
8915 case USE_XOP_8F_TABLE:
8916 if (!fetch_code (ins->info, ins->codep + 3))
8917 return &err_opcode;
8918 ins->rex = ~(*ins->codep >> 5) & 0x7;
8919
8920 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8921 switch ((*ins->codep & 0x1f))
8922 {
8923 default:
8924 dp = &bad_opcode;
8925 return dp;
8926 case 0x8:
8927 vex_table_index = XOP_08;
8928 break;
8929 case 0x9:
8930 vex_table_index = XOP_09;
8931 break;
8932 case 0xa:
8933 vex_table_index = XOP_0A;
8934 break;
8935 }
8936 ins->codep++;
8937 ins->vex.w = *ins->codep & 0x80;
8938 if (ins->vex.w && ins->address_mode == mode_64bit)
8939 ins->rex |= REX_W;
8940
8941 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8942 if (ins->address_mode != mode_64bit)
8943 {
8944 /* In 16/32-bit mode REX_B is silently ignored. */
8945 ins->rex &= ~REX_B;
8946 }
8947
8948 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8949 switch ((*ins->codep & 0x3))
8950 {
8951 case 0:
8952 break;
8953 case 1:
8954 ins->vex.prefix = DATA_PREFIX_OPCODE;
8955 break;
8956 case 2:
8957 ins->vex.prefix = REPE_PREFIX_OPCODE;
8958 break;
8959 case 3:
8960 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8961 break;
8962 }
8963 ins->need_vex = 3;
8964 ins->codep++;
8965 vindex = *ins->codep++;
8966 dp = &xop_table[vex_table_index][vindex];
8967
8968 ins->end_codep = ins->codep;
8969 if (!fetch_modrm (ins))
8970 return &err_opcode;
8971
8972 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8973 having to decode the bits for every otherwise valid encoding. */
8974 if (ins->vex.prefix)
8975 return &bad_opcode;
8976 break;
8977
8978 case USE_VEX_C4_TABLE:
8979 /* VEX prefix. */
8980 if (!fetch_code (ins->info, ins->codep + 3))
8981 return &err_opcode;
8982 ins->rex = ~(*ins->codep >> 5) & 0x7;
8983 switch ((*ins->codep & 0x1f))
8984 {
8985 default:
8986 dp = &bad_opcode;
8987 return dp;
8988 case 0x1:
8989 vex_table_index = VEX_0F;
8990 break;
8991 case 0x2:
8992 vex_table_index = VEX_0F38;
8993 break;
8994 case 0x3:
8995 vex_table_index = VEX_0F3A;
8996 break;
8997 case 0x7:
8998 vex_table_index = VEX_MAP7;
8999 break;
9000 }
9001 ins->codep++;
9002 ins->vex.w = *ins->codep & 0x80;
9003 if (ins->address_mode == mode_64bit)
9004 {
9005 if (ins->vex.w)
9006 ins->rex |= REX_W;
9007 }
9008 else
9009 {
9010 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9011 is ignored, other REX bits are 0 and the highest bit in
9012 VEX.vvvv is also ignored (but we mustn't clear it here). */
9013 ins->rex = 0;
9014 }
9015 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9016 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9017 switch ((*ins->codep & 0x3))
9018 {
9019 case 0:
9020 break;
9021 case 1:
9022 ins->vex.prefix = DATA_PREFIX_OPCODE;
9023 break;
9024 case 2:
9025 ins->vex.prefix = REPE_PREFIX_OPCODE;
9026 break;
9027 case 3:
9028 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9029 break;
9030 }
9031 ins->need_vex = 3;
9032 ins->codep++;
9033 vindex = *ins->codep++;
9034 if (vex_table_index != VEX_MAP7)
9035 dp = &vex_table[vex_table_index][vindex];
9036 else if (vindex == 0xf8)
9037 dp = &map7_f8_opcode;
9038 else
9039 dp = &bad_opcode;
9040 ins->end_codep = ins->codep;
9041 /* There is no MODRM byte for VEX0F 77. */
9042 if ((vex_table_index != VEX_0F || vindex != 0x77)
9043 && !fetch_modrm (ins))
9044 return &err_opcode;
9045 break;
9046
9047 case USE_VEX_C5_TABLE:
9048 /* VEX prefix. */
9049 if (!fetch_code (ins->info, ins->codep + 2))
9050 return &err_opcode;
9051 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9052
9053 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9054 VEX.vvvv is 1. */
9055 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9056 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9057 switch ((*ins->codep & 0x3))
9058 {
9059 case 0:
9060 break;
9061 case 1:
9062 ins->vex.prefix = DATA_PREFIX_OPCODE;
9063 break;
9064 case 2:
9065 ins->vex.prefix = REPE_PREFIX_OPCODE;
9066 break;
9067 case 3:
9068 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9069 break;
9070 }
9071 ins->need_vex = 2;
9072 ins->codep++;
9073 vindex = *ins->codep++;
9074 dp = &vex_table[VEX_0F][vindex];
9075 ins->end_codep = ins->codep;
9076 /* There is no MODRM byte for VEX 77. */
9077 if (vindex != 0x77 && !fetch_modrm (ins))
9078 return &err_opcode;
9079 break;
9080
9081 case USE_VEX_W_TABLE:
9082 use_vex_w_table:
9083 if (!ins->need_vex)
9084 abort ();
9085
9086 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9087 break;
9088
9089 case USE_EVEX_TABLE:
9090 ins->two_source_ops = false;
9091 /* EVEX prefix. */
9092 ins->vex.evex = true;
9093 if (!fetch_code (ins->info, ins->codep + 4))
9094 return &err_opcode;
9095 /* The first byte after 0x62. */
9096 if (*ins->codep & 0x8)
9097 ins->rex2 |= REX_B;
9098 if (!(*ins->codep & 0x10))
9099 ins->rex2 |= REX_R;
9100
9101 ins->rex = ~(*ins->codep >> 5) & 0x7;
9102 switch (*ins->codep & 0x7)
9103 {
9104 default:
9105 return &bad_opcode;
9106 case 0x1:
9107 vex_table_index = EVEX_0F;
9108 break;
9109 case 0x2:
9110 vex_table_index = EVEX_0F38;
9111 break;
9112 case 0x3:
9113 vex_table_index = EVEX_0F3A;
9114 break;
9115 case 0x4:
9116 vex_table_index = EVEX_MAP4;
9117 ins->evex_type = evex_from_legacy;
9118 if (ins->address_mode != mode_64bit)
9119 return &bad_opcode;
9120 break;
9121 case 0x5:
9122 vex_table_index = EVEX_MAP5;
9123 break;
9124 case 0x6:
9125 vex_table_index = EVEX_MAP6;
9126 break;
9127 case 0x7:
9128 vex_table_index = EVEX_MAP7;
9129 break;
9130 }
9131
9132 /* The second byte after 0x62. */
9133 ins->codep++;
9134 ins->vex.w = *ins->codep & 0x80;
9135 if (ins->vex.w && ins->address_mode == mode_64bit)
9136 ins->rex |= REX_W;
9137
9138 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9139
9140 if (!(*ins->codep & 0x4))
9141 ins->rex2 |= REX_X;
9142
9143 switch ((*ins->codep & 0x3))
9144 {
9145 case 0:
9146 break;
9147 case 1:
9148 ins->vex.prefix = DATA_PREFIX_OPCODE;
9149 break;
9150 case 2:
9151 ins->vex.prefix = REPE_PREFIX_OPCODE;
9152 break;
9153 case 3:
9154 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9155 break;
9156 }
9157
9158 /* The third byte after 0x62. */
9159 ins->codep++;
9160
9161 /* Remember the static rounding bits. */
9162 ins->vex.ll = (*ins->codep >> 5) & 3;
9163 ins->vex.b = *ins->codep & 0x10;
9164
9165 ins->vex.v = *ins->codep & 0x8;
9166 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9167 ins->vex.zeroing = *ins->codep & 0x80;
9168 /* Set the NF bit for EVEX-Promoted instructions, this bit will be cleared
9169 when it's an evex_default one. */
9170 ins->vex.nf = *ins->codep & 0x4;
9171
9172 if (ins->address_mode != mode_64bit)
9173 {
9174 /* Report bad for !evex_default and when two fixed values of evex
9175 change.. */
9176 if (ins->evex_type != evex_default
9177 || (ins->rex2 & (REX_B | REX_X)))
9178 return &bad_opcode;
9179 /* In 16/32-bit mode silently ignore following bits. */
9180 ins->rex &= ~REX_B;
9181 ins->rex2 &= ~REX_R;
9182 }
9183
9184 /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9185 all bits of EVEX.vvvv and EVEX.V' must be 1. */
9186 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
9187 && (ins->vex.register_specifier || !ins->vex.v))
9188 return &bad_opcode;
9189
9190 ins->need_vex = 4;
9191
9192 /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9193 lower 2 bits of EVEX.aaa must be 0. */
9194 if (ins->evex_type == evex_from_legacy
9195 && ((ins->vex.mask_register_specifier & 0x3) != 0
9196 || ins->vex.ll != 0
9197 || ins->vex.zeroing != 0))
9198 return &bad_opcode;
9199
9200 ins->codep++;
9201 vindex = *ins->codep++;
9202 if (vex_table_index != EVEX_MAP7)
9203 dp = &evex_table[vex_table_index][vindex];
9204 else if (vindex == 0xf8)
9205 dp = &map7_f8_opcode;
9206 else
9207 dp = &bad_opcode;
9208 ins->end_codep = ins->codep;
9209 if (!fetch_modrm (ins))
9210 return &err_opcode;
9211
9212 if (ins->modrm.mod == 3 && (ins->rex2 & REX_X))
9213 return &bad_opcode;
9214
9215 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9216 which has the same encoding as vex.length == 128 and they can share
9217 the same processing with vex.length in OP_VEX. */
9218 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9219 ins->vex.length = 512;
9220 else
9221 {
9222 switch (ins->vex.ll)
9223 {
9224 case 0x0:
9225 ins->vex.length = 128;
9226 break;
9227 case 0x1:
9228 ins->vex.length = 256;
9229 break;
9230 case 0x2:
9231 ins->vex.length = 512;
9232 break;
9233 default:
9234 return &bad_opcode;
9235 }
9236 }
9237 break;
9238
9239 case 0:
9240 dp = &bad_opcode;
9241 break;
9242
9243 default:
9244 abort ();
9245 }
9246
9247 if (dp->name != NULL)
9248 return dp;
9249 else
9250 return get_valid_dis386 (dp, ins);
9251 }
9252
9253 static bool
get_sib(instr_info * ins,int sizeflag)9254 get_sib (instr_info *ins, int sizeflag)
9255 {
9256 /* If modrm.mod == 3, operand must be register. */
9257 if (ins->need_modrm
9258 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9259 && ins->modrm.mod != 3
9260 && ins->modrm.rm == 4)
9261 {
9262 if (!fetch_code (ins->info, ins->codep + 2))
9263 return false;
9264 ins->sib.index = (ins->codep[1] >> 3) & 7;
9265 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9266 ins->sib.base = ins->codep[1] & 7;
9267 ins->has_sib = true;
9268 }
9269 else
9270 ins->has_sib = false;
9271
9272 return true;
9273 }
9274
9275 /* Like oappend_with_style (below) but always with text style. */
9276
9277 static void
oappend(instr_info * ins,const char * s)9278 oappend (instr_info *ins, const char *s)
9279 {
9280 oappend_with_style (ins, s, dis_style_text);
9281 }
9282
9283 /* Like oappend (above), but S is a string starting with '%'. In
9284 Intel syntax, the '%' is elided. */
9285
9286 static void
oappend_register(instr_info * ins,const char * s)9287 oappend_register (instr_info *ins, const char *s)
9288 {
9289 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9290 }
9291
9292 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9293 STYLE is the default style to use in the fprintf_styled_func calls,
9294 however, FMT might include embedded style markers (see oappend_style),
9295 these embedded markers are not printed, but instead change the style
9296 used in the next fprintf_styled_func call. */
9297
9298 static void ATTRIBUTE_PRINTF_3
i386_dis_printf(const disassemble_info * info,enum disassembler_style style,const char * fmt,...)9299 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9300 const char *fmt, ...)
9301 {
9302 va_list ap;
9303 enum disassembler_style curr_style = style;
9304 const char *start, *curr;
9305 char staging_area[40];
9306
9307 va_start (ap, fmt);
9308 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9309 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9310 with the staging area. */
9311 if (strcmp (fmt, "%s"))
9312 {
9313 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9314
9315 va_end (ap);
9316
9317 if (res < 0)
9318 return;
9319
9320 if ((size_t) res >= sizeof (staging_area))
9321 abort ();
9322
9323 start = curr = staging_area;
9324 }
9325 else
9326 {
9327 start = curr = va_arg (ap, const char *);
9328 va_end (ap);
9329 }
9330
9331 do
9332 {
9333 if (*curr == '\0'
9334 || (*curr == STYLE_MARKER_CHAR
9335 && ISXDIGIT (*(curr + 1))
9336 && *(curr + 2) == STYLE_MARKER_CHAR))
9337 {
9338 /* Output content between our START position and CURR. */
9339 int len = curr - start;
9340 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9341 "%.*s", len, start);
9342 if (n < 0)
9343 break;
9344
9345 if (*curr == '\0')
9346 break;
9347
9348 /* Skip over the initial STYLE_MARKER_CHAR. */
9349 ++curr;
9350
9351 /* Update the CURR_STYLE. As there are less than 16 styles, it
9352 is possible, that if the input is corrupted in some way, that
9353 we might set CURR_STYLE to an invalid value. Don't worry
9354 though, we check for this situation. */
9355 if (*curr >= '0' && *curr <= '9')
9356 curr_style = (enum disassembler_style) (*curr - '0');
9357 else if (*curr >= 'a' && *curr <= 'f')
9358 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9359 else
9360 curr_style = dis_style_text;
9361
9362 /* Check for an invalid style having been selected. This should
9363 never happen, but it doesn't hurt to be a little paranoid. */
9364 if (curr_style > dis_style_comment_start)
9365 curr_style = dis_style_text;
9366
9367 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9368 curr += 2;
9369
9370 /* Reset the START to after the style marker. */
9371 start = curr;
9372 }
9373 else
9374 ++curr;
9375 }
9376 while (true);
9377 }
9378
9379 static int
print_insn(bfd_vma pc,disassemble_info * info,int intel_syntax)9380 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9381 {
9382 const struct dis386 *dp;
9383 int i;
9384 int ret;
9385 char *op_txt[MAX_OPERANDS];
9386 int needcomma;
9387 bool intel_swap_2_3;
9388 int sizeflag, orig_sizeflag;
9389 const char *p;
9390 struct dis_private priv;
9391 int prefix_length;
9392 int op_count;
9393 instr_info ins = {
9394 .info = info,
9395 .intel_syntax = intel_syntax >= 0
9396 ? intel_syntax
9397 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9398 .intel_mnemonic = !SYSV386_COMPAT,
9399 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9400 .start_pc = pc,
9401 .start_codep = priv.the_buffer,
9402 .codep = priv.the_buffer,
9403 .obufp = ins.obuf,
9404 .last_lock_prefix = -1,
9405 .last_repz_prefix = -1,
9406 .last_repnz_prefix = -1,
9407 .last_data_prefix = -1,
9408 .last_addr_prefix = -1,
9409 .last_rex_prefix = -1,
9410 .last_rex2_prefix = -1,
9411 .last_seg_prefix = -1,
9412 .fwait_prefix = -1,
9413 };
9414 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9415
9416 priv.orig_sizeflag = AFLAG | DFLAG;
9417 if ((info->mach & bfd_mach_i386_i386) != 0)
9418 ins.address_mode = mode_32bit;
9419 else if (info->mach == bfd_mach_i386_i8086)
9420 {
9421 ins.address_mode = mode_16bit;
9422 priv.orig_sizeflag = 0;
9423 }
9424 else
9425 ins.address_mode = mode_64bit;
9426
9427 for (p = info->disassembler_options; p != NULL;)
9428 {
9429 if (startswith (p, "amd64"))
9430 ins.isa64 = amd64;
9431 else if (startswith (p, "intel64"))
9432 ins.isa64 = intel64;
9433 else if (startswith (p, "x86-64"))
9434 {
9435 ins.address_mode = mode_64bit;
9436 priv.orig_sizeflag |= AFLAG | DFLAG;
9437 }
9438 else if (startswith (p, "i386"))
9439 {
9440 ins.address_mode = mode_32bit;
9441 priv.orig_sizeflag |= AFLAG | DFLAG;
9442 }
9443 else if (startswith (p, "i8086"))
9444 {
9445 ins.address_mode = mode_16bit;
9446 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9447 }
9448 else if (startswith (p, "intel"))
9449 {
9450 if (startswith (p + 5, "-mnemonic"))
9451 ins.intel_mnemonic = true;
9452 else
9453 ins.intel_syntax = 1;
9454 }
9455 else if (startswith (p, "att"))
9456 {
9457 ins.intel_syntax = 0;
9458 if (startswith (p + 3, "-mnemonic"))
9459 ins.intel_mnemonic = false;
9460 }
9461 else if (startswith (p, "addr"))
9462 {
9463 if (ins.address_mode == mode_64bit)
9464 {
9465 if (p[4] == '3' && p[5] == '2')
9466 priv.orig_sizeflag &= ~AFLAG;
9467 else if (p[4] == '6' && p[5] == '4')
9468 priv.orig_sizeflag |= AFLAG;
9469 }
9470 else
9471 {
9472 if (p[4] == '1' && p[5] == '6')
9473 priv.orig_sizeflag &= ~AFLAG;
9474 else if (p[4] == '3' && p[5] == '2')
9475 priv.orig_sizeflag |= AFLAG;
9476 }
9477 }
9478 else if (startswith (p, "data"))
9479 {
9480 if (p[4] == '1' && p[5] == '6')
9481 priv.orig_sizeflag &= ~DFLAG;
9482 else if (p[4] == '3' && p[5] == '2')
9483 priv.orig_sizeflag |= DFLAG;
9484 }
9485 else if (startswith (p, "suffix"))
9486 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9487
9488 p = strchr (p, ',');
9489 if (p != NULL)
9490 p++;
9491 }
9492
9493 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9494 {
9495 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9496 return -1;
9497 }
9498
9499 if (ins.intel_syntax)
9500 {
9501 ins.open_char = '[';
9502 ins.close_char = ']';
9503 ins.separator_char = '+';
9504 ins.scale_char = '*';
9505 }
9506 else
9507 {
9508 ins.open_char = '(';
9509 ins.close_char = ')';
9510 ins.separator_char = ',';
9511 ins.scale_char = ',';
9512 }
9513
9514 /* The output looks better if we put 7 bytes on a line, since that
9515 puts most long word instructions on a single line. */
9516 info->bytes_per_line = 7;
9517
9518 info->private_data = &priv;
9519 priv.fetched = 0;
9520 priv.insn_start = pc;
9521
9522 for (i = 0; i < MAX_OPERANDS; ++i)
9523 {
9524 op_out[i][0] = 0;
9525 ins.op_out[i] = op_out[i];
9526 }
9527
9528 sizeflag = priv.orig_sizeflag;
9529
9530 switch (ckprefix (&ins))
9531 {
9532 case ckp_okay:
9533 break;
9534
9535 case ckp_bogus:
9536 /* Too many prefixes or unused REX prefixes. */
9537 for (i = 0;
9538 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9539 i++)
9540 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9541 (i == 0 ? "" : " "),
9542 prefix_name (ins.address_mode, ins.all_prefixes[i],
9543 sizeflag));
9544 ret = i;
9545 goto out;
9546
9547 case ckp_fetch_error:
9548 goto fetch_error_out;
9549 }
9550
9551 ins.nr_prefixes = ins.codep - ins.start_codep;
9552
9553 if (!fetch_code (info, ins.codep + 1))
9554 {
9555 fetch_error_out:
9556 ret = fetch_error (&ins);
9557 goto out;
9558 }
9559
9560 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9561
9562 if ((ins.prefixes & PREFIX_FWAIT)
9563 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9564 {
9565 /* Handle ins.prefixes before fwait. */
9566 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9567 i++)
9568 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9569 prefix_name (ins.address_mode, ins.all_prefixes[i],
9570 sizeflag));
9571 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9572 ret = i + 1;
9573 goto out;
9574 }
9575
9576 /* REX2.M in rex2 prefix represents map0 or map1. */
9577 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9578 {
9579 if (!ins.rex2)
9580 {
9581 ins.codep++;
9582 if (!fetch_code (info, ins.codep + 1))
9583 goto fetch_error_out;
9584 }
9585
9586 dp = &dis386_twobyte[*ins.codep];
9587 ins.need_modrm = twobyte_has_modrm[*ins.codep];
9588 }
9589 else
9590 {
9591 dp = &dis386[*ins.codep];
9592 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9593 }
9594 ins.codep++;
9595
9596 /* Save sizeflag for printing the extra ins.prefixes later before updating
9597 it for mnemonic and operand processing. The prefix names depend
9598 only on the address mode. */
9599 orig_sizeflag = sizeflag;
9600 if (ins.prefixes & PREFIX_ADDR)
9601 sizeflag ^= AFLAG;
9602 if ((ins.prefixes & PREFIX_DATA))
9603 sizeflag ^= DFLAG;
9604
9605 ins.end_codep = ins.codep;
9606 if (ins.need_modrm && !fetch_modrm (&ins))
9607 goto fetch_error_out;
9608
9609 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9610 {
9611 if (!get_sib (&ins, sizeflag)
9612 || !dofloat (&ins, sizeflag))
9613 goto fetch_error_out;
9614 }
9615 else
9616 {
9617 dp = get_valid_dis386 (dp, &ins);
9618 if (dp == &err_opcode)
9619 goto fetch_error_out;
9620
9621 /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9622 is interpreted as the operand size override. */
9623 if (ins.evex_type == evex_from_legacy
9624 && ins.vex.prefix == DATA_PREFIX_OPCODE)
9625 sizeflag ^= DFLAG;
9626
9627 if(ins.evex_type == evex_default)
9628 ins.vex.nf = false;
9629 else
9630 /* For EVEX-promoted formats, we need to clear EVEX.NF (ccmp and ctest
9631 are cleared separately.) in mask_register_specifier and keep the low
9632 2 bits of mask_register_specifier to report errors for invalid cases
9633 . */
9634 ins.vex.mask_register_specifier &= 0x3;
9635
9636 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9637 {
9638 if (!get_sib (&ins, sizeflag))
9639 goto fetch_error_out;
9640 for (i = 0; i < MAX_OPERANDS; ++i)
9641 {
9642 ins.obufp = ins.op_out[i];
9643 ins.op_ad = MAX_OPERANDS - 1 - i;
9644 if (dp->op[i].rtn
9645 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9646 goto fetch_error_out;
9647 /* For EVEX instruction after the last operand masking
9648 should be printed. */
9649 if (i == 0 && ins.vex.evex)
9650 {
9651 /* Don't print {%k0}. */
9652 if (ins.vex.mask_register_specifier)
9653 {
9654 const char *reg_name
9655 = att_names_mask[ins.vex.mask_register_specifier];
9656
9657 oappend (&ins, "{");
9658 oappend_register (&ins, reg_name);
9659 oappend (&ins, "}");
9660
9661 if (ins.vex.zeroing)
9662 oappend (&ins, "{z}");
9663 }
9664 else if (ins.vex.zeroing)
9665 {
9666 oappend (&ins, "{bad}");
9667 continue;
9668 }
9669
9670 /* Instructions with a mask register destination allow for
9671 zeroing-masking only (if any masking at all), which is
9672 _not_ expressed by EVEX.z. */
9673 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9674 ins.illegal_masking = true;
9675
9676 /* S/G insns require a mask and don't allow
9677 zeroing-masking. */
9678 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9679 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9680 && (ins.vex.mask_register_specifier == 0
9681 || ins.vex.zeroing))
9682 ins.illegal_masking = true;
9683
9684 if (ins.illegal_masking)
9685 oappend (&ins, "/(bad)");
9686 }
9687 }
9688 /* vex.nf is cleared after being consumed. */
9689 if (ins.vex.nf)
9690 oappend (&ins, "{bad-nf}");
9691
9692 /* Check whether rounding control was enabled for an insn not
9693 supporting it, when evex.b is not treated as evex.nd. */
9694 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9695 && !(ins.evex_used & EVEX_b_used))
9696 {
9697 for (i = 0; i < MAX_OPERANDS; ++i)
9698 {
9699 ins.obufp = ins.op_out[i];
9700 if (*ins.obufp)
9701 continue;
9702 oappend (&ins, names_rounding[ins.vex.ll]);
9703 oappend (&ins, "bad}");
9704 break;
9705 }
9706 }
9707 }
9708 }
9709
9710 /* Clear instruction information. */
9711 info->insn_info_valid = 0;
9712 info->branch_delay_insns = 0;
9713 info->data_size = 0;
9714 info->insn_type = dis_noninsn;
9715 info->target = 0;
9716 info->target2 = 0;
9717
9718 /* Reset jump operation indicator. */
9719 ins.op_is_jump = false;
9720 {
9721 int jump_detection = 0;
9722
9723 /* Extract flags. */
9724 for (i = 0; i < MAX_OPERANDS; ++i)
9725 {
9726 if ((dp->op[i].rtn == OP_J)
9727 || (dp->op[i].rtn == OP_indirE))
9728 jump_detection |= 1;
9729 else if ((dp->op[i].rtn == BND_Fixup)
9730 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9731 jump_detection |= 2;
9732 else if ((dp->op[i].bytemode == cond_jump_mode)
9733 || (dp->op[i].bytemode == loop_jcxz_mode))
9734 jump_detection |= 4;
9735 }
9736
9737 /* Determine if this is a jump or branch. */
9738 if ((jump_detection & 0x3) == 0x3)
9739 {
9740 ins.op_is_jump = true;
9741 if (jump_detection & 0x4)
9742 info->insn_type = dis_condbranch;
9743 else
9744 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9745 ? dis_jsr : dis_branch;
9746 }
9747 }
9748
9749 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9750 are all 0s in inverted form. */
9751 if (ins.need_vex && ins.vex.register_specifier != 0)
9752 {
9753 i386_dis_printf (info, dis_style_text, "(bad)");
9754 ret = ins.end_codep - priv.the_buffer;
9755 goto out;
9756 }
9757
9758 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9759 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9760 {
9761 i386_dis_printf (info, dis_style_text, "(bad)");
9762 ret = ins.end_codep - priv.the_buffer;
9763 goto out;
9764 }
9765
9766 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9767 {
9768 case PREFIX_DATA:
9769 /* If only the data prefix is marked as mandatory, its absence renders
9770 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9771 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9772 {
9773 i386_dis_printf (info, dis_style_text, "(bad)");
9774 ret = ins.end_codep - priv.the_buffer;
9775 goto out;
9776 }
9777 ins.used_prefixes |= PREFIX_DATA;
9778 /* Fall through. */
9779 case PREFIX_OPCODE:
9780 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9781 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9782 used by putop and MMX/SSE operand and may be overridden by the
9783 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9784 separately. */
9785 if (((ins.need_vex
9786 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9787 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9788 : (ins.prefixes
9789 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9790 && (ins.used_prefixes
9791 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9792 || (((ins.need_vex
9793 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9794 : ((ins.prefixes
9795 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9796 == PREFIX_DATA))
9797 && (ins.used_prefixes & PREFIX_DATA) == 0))
9798 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9799 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9800 {
9801 i386_dis_printf (info, dis_style_text, "(bad)");
9802 ret = ins.end_codep - priv.the_buffer;
9803 goto out;
9804 }
9805 break;
9806
9807 case PREFIX_IGNORED:
9808 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9809 origins in all_prefixes. */
9810 ins.used_prefixes &= ~PREFIX_OPCODE;
9811 if (ins.last_data_prefix >= 0)
9812 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9813 if (ins.last_repz_prefix >= 0)
9814 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9815 if (ins.last_repnz_prefix >= 0)
9816 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9817 break;
9818
9819 case PREFIX_NP_OR_DATA:
9820 if (ins.vex.prefix == REPE_PREFIX_OPCODE
9821 || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9822 {
9823 i386_dis_printf (info, dis_style_text, "(bad)");
9824 ret = ins.end_codep - priv.the_buffer;
9825 goto out;
9826 }
9827 break;
9828
9829 case NO_PREFIX:
9830 if (ins.vex.prefix)
9831 {
9832 i386_dis_printf (info, dis_style_text, "(bad)");
9833 ret = ins.end_codep - priv.the_buffer;
9834 goto out;
9835 }
9836 break;
9837 }
9838
9839 /* Check if the REX prefix is used. */
9840 if ((ins.rex ^ ins.rex_used) == 0
9841 && !ins.need_vex && ins.last_rex_prefix >= 0)
9842 ins.all_prefixes[ins.last_rex_prefix] = 0;
9843
9844 /* Check if the REX2 prefix is used. */
9845 if (ins.last_rex2_prefix >= 0
9846 && ((ins.rex2 & REX2_SPECIAL)
9847 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9848 && (ins.rex ^ ins.rex_used) == 0
9849 && (ins.rex2 & 7))))
9850 ins.all_prefixes[ins.last_rex2_prefix] = 0;
9851
9852 /* Check if the SEG prefix is used. */
9853 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9854 | PREFIX_FS | PREFIX_GS)) != 0
9855 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9856 ins.all_prefixes[ins.last_seg_prefix] = 0;
9857
9858 /* Check if the ADDR prefix is used. */
9859 if ((ins.prefixes & PREFIX_ADDR) != 0
9860 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9861 ins.all_prefixes[ins.last_addr_prefix] = 0;
9862
9863 /* Check if the DATA prefix is used. */
9864 if ((ins.prefixes & PREFIX_DATA) != 0
9865 && (ins.used_prefixes & PREFIX_DATA) != 0
9866 && !ins.need_vex)
9867 ins.all_prefixes[ins.last_data_prefix] = 0;
9868
9869 /* Print the extra ins.prefixes. */
9870 prefix_length = 0;
9871 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9872 if (ins.all_prefixes[i])
9873 {
9874 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9875 orig_sizeflag);
9876
9877 if (name == NULL)
9878 abort ();
9879 prefix_length += strlen (name) + 1;
9880 if (ins.all_prefixes[i] == REX2_OPCODE)
9881 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9882 (unsigned int) ins.rex2_payload);
9883 else
9884 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9885 }
9886
9887 /* Check maximum code length. */
9888 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9889 {
9890 i386_dis_printf (info, dis_style_text, "(bad)");
9891 ret = MAX_CODE_LENGTH;
9892 goto out;
9893 }
9894
9895 /* Calculate the number of operands this instruction has. */
9896 op_count = 0;
9897 for (i = 0; i < MAX_OPERANDS; ++i)
9898 if (*ins.op_out[i] != '\0')
9899 ++op_count;
9900
9901 /* Calculate the number of spaces to print after the mnemonic. */
9902 ins.obufp = ins.mnemonicendp;
9903 if (op_count > 0)
9904 {
9905 i = strlen (ins.obuf) + prefix_length;
9906 if (i < 7)
9907 i = 7 - i;
9908 else
9909 i = 1;
9910 }
9911 else
9912 i = 0;
9913
9914 /* Print the instruction mnemonic along with any trailing whitespace. */
9915 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9916
9917 /* The enter and bound instructions are printed with operands in the same
9918 order as the intel book; everything else is printed in reverse order. */
9919 intel_swap_2_3 = false;
9920 if (ins.intel_syntax || ins.two_source_ops)
9921 {
9922 for (i = 0; i < MAX_OPERANDS; ++i)
9923 op_txt[i] = ins.op_out[i];
9924
9925 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9926 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9927 {
9928 op_txt[2] = ins.op_out[3];
9929 op_txt[3] = ins.op_out[2];
9930 intel_swap_2_3 = true;
9931 }
9932
9933 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9934 {
9935 bool riprel;
9936
9937 ins.op_ad = ins.op_index[i];
9938 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9939 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9940 riprel = ins.op_riprel[i];
9941 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9942 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9943 }
9944 }
9945 else
9946 {
9947 for (i = 0; i < MAX_OPERANDS; ++i)
9948 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9949 }
9950
9951 needcomma = 0;
9952 for (i = 0; i < MAX_OPERANDS; ++i)
9953 if (*op_txt[i])
9954 {
9955 /* In Intel syntax embedded rounding / SAE are not separate operands.
9956 Instead they're attached to the prior register operand. Simply
9957 suppress emission of the comma to achieve that effect. */
9958 switch (i & -(ins.intel_syntax && dp))
9959 {
9960 case 2:
9961 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9962 needcomma = 0;
9963 break;
9964 case 3:
9965 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9966 needcomma = 0;
9967 break;
9968 }
9969 if (needcomma)
9970 i386_dis_printf (info, dis_style_text, ",");
9971 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9972 {
9973 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9974
9975 if (ins.op_is_jump)
9976 {
9977 info->insn_info_valid = 1;
9978 info->branch_delay_insns = 0;
9979 info->data_size = 0;
9980 info->target = target;
9981 info->target2 = 0;
9982 }
9983 (*info->print_address_func) (target, info);
9984 }
9985 else
9986 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9987 needcomma = 1;
9988 }
9989
9990 for (i = 0; i < MAX_OPERANDS; i++)
9991 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9992 {
9993 i386_dis_printf (info, dis_style_comment_start, " # ");
9994 (*info->print_address_func)
9995 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9996 + ins.op_address[ins.op_index[i]]),
9997 info);
9998 break;
9999 }
10000 ret = ins.codep - priv.the_buffer;
10001 out:
10002 info->private_data = NULL;
10003 return ret;
10004 }
10005
10006 /* Here for backwards compatibility. When gdb stops using
10007 print_insn_i386_att and print_insn_i386_intel these functions can
10008 disappear, and print_insn_i386 be merged into print_insn. */
10009 int
print_insn_i386_att(bfd_vma pc,disassemble_info * info)10010 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10011 {
10012 return print_insn (pc, info, 0);
10013 }
10014
10015 int
print_insn_i386_intel(bfd_vma pc,disassemble_info * info)10016 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10017 {
10018 return print_insn (pc, info, 1);
10019 }
10020
10021 int
print_insn_i386(bfd_vma pc,disassemble_info * info)10022 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10023 {
10024 return print_insn (pc, info, -1);
10025 }
10026
10027 static const char *float_mem[] = {
10028 /* d8 */
10029 "fadd{s|}",
10030 "fmul{s|}",
10031 "fcom{s|}",
10032 "fcomp{s|}",
10033 "fsub{s|}",
10034 "fsubr{s|}",
10035 "fdiv{s|}",
10036 "fdivr{s|}",
10037 /* d9 */
10038 "fld{s|}",
10039 "(bad)",
10040 "fst{s|}",
10041 "fstp{s|}",
10042 "fldenv{C|C}",
10043 "fldcw",
10044 "fNstenv{C|C}",
10045 "fNstcw",
10046 /* da */
10047 "fiadd{l|}",
10048 "fimul{l|}",
10049 "ficom{l|}",
10050 "ficomp{l|}",
10051 "fisub{l|}",
10052 "fisubr{l|}",
10053 "fidiv{l|}",
10054 "fidivr{l|}",
10055 /* db */
10056 "fild{l|}",
10057 "fisttp{l|}",
10058 "fist{l|}",
10059 "fistp{l|}",
10060 "(bad)",
10061 "fld{t|}",
10062 "(bad)",
10063 "fstp{t|}",
10064 /* dc */
10065 "fadd{l|}",
10066 "fmul{l|}",
10067 "fcom{l|}",
10068 "fcomp{l|}",
10069 "fsub{l|}",
10070 "fsubr{l|}",
10071 "fdiv{l|}",
10072 "fdivr{l|}",
10073 /* dd */
10074 "fld{l|}",
10075 "fisttp{ll|}",
10076 "fst{l||}",
10077 "fstp{l|}",
10078 "frstor{C|C}",
10079 "(bad)",
10080 "fNsave{C|C}",
10081 "fNstsw",
10082 /* de */
10083 "fiadd{s|}",
10084 "fimul{s|}",
10085 "ficom{s|}",
10086 "ficomp{s|}",
10087 "fisub{s|}",
10088 "fisubr{s|}",
10089 "fidiv{s|}",
10090 "fidivr{s|}",
10091 /* df */
10092 "fild{s|}",
10093 "fisttp{s|}",
10094 "fist{s|}",
10095 "fistp{s|}",
10096 "fbld",
10097 "fild{ll|}",
10098 "fbstp",
10099 "fistp{ll|}",
10100 };
10101
10102 static const unsigned char float_mem_mode[] = {
10103 /* d8 */
10104 d_mode,
10105 d_mode,
10106 d_mode,
10107 d_mode,
10108 d_mode,
10109 d_mode,
10110 d_mode,
10111 d_mode,
10112 /* d9 */
10113 d_mode,
10114 0,
10115 d_mode,
10116 d_mode,
10117 0,
10118 w_mode,
10119 0,
10120 w_mode,
10121 /* da */
10122 d_mode,
10123 d_mode,
10124 d_mode,
10125 d_mode,
10126 d_mode,
10127 d_mode,
10128 d_mode,
10129 d_mode,
10130 /* db */
10131 d_mode,
10132 d_mode,
10133 d_mode,
10134 d_mode,
10135 0,
10136 t_mode,
10137 0,
10138 t_mode,
10139 /* dc */
10140 q_mode,
10141 q_mode,
10142 q_mode,
10143 q_mode,
10144 q_mode,
10145 q_mode,
10146 q_mode,
10147 q_mode,
10148 /* dd */
10149 q_mode,
10150 q_mode,
10151 q_mode,
10152 q_mode,
10153 0,
10154 0,
10155 0,
10156 w_mode,
10157 /* de */
10158 w_mode,
10159 w_mode,
10160 w_mode,
10161 w_mode,
10162 w_mode,
10163 w_mode,
10164 w_mode,
10165 w_mode,
10166 /* df */
10167 w_mode,
10168 w_mode,
10169 w_mode,
10170 w_mode,
10171 t_mode,
10172 q_mode,
10173 t_mode,
10174 q_mode
10175 };
10176
10177 #define ST { OP_ST, 0 }
10178 #define STi { OP_STi, 0 }
10179
10180 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10181 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10182 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10183 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10184 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10185 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10186 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10187 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10188 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10189
10190 static const struct dis386 float_reg[][8] = {
10191 /* d8 */
10192 {
10193 { "fadd", { ST, STi }, 0 },
10194 { "fmul", { ST, STi }, 0 },
10195 { "fcom", { STi }, 0 },
10196 { "fcomp", { STi }, 0 },
10197 { "fsub", { ST, STi }, 0 },
10198 { "fsubr", { ST, STi }, 0 },
10199 { "fdiv", { ST, STi }, 0 },
10200 { "fdivr", { ST, STi }, 0 },
10201 },
10202 /* d9 */
10203 {
10204 { "fld", { STi }, 0 },
10205 { "fxch", { STi }, 0 },
10206 { FGRPd9_2 },
10207 { Bad_Opcode },
10208 { FGRPd9_4 },
10209 { FGRPd9_5 },
10210 { FGRPd9_6 },
10211 { FGRPd9_7 },
10212 },
10213 /* da */
10214 {
10215 { "fcmovb", { ST, STi }, 0 },
10216 { "fcmove", { ST, STi }, 0 },
10217 { "fcmovbe",{ ST, STi }, 0 },
10218 { "fcmovu", { ST, STi }, 0 },
10219 { Bad_Opcode },
10220 { FGRPda_5 },
10221 { Bad_Opcode },
10222 { Bad_Opcode },
10223 },
10224 /* db */
10225 {
10226 { "fcmovnb",{ ST, STi }, 0 },
10227 { "fcmovne",{ ST, STi }, 0 },
10228 { "fcmovnbe",{ ST, STi }, 0 },
10229 { "fcmovnu",{ ST, STi }, 0 },
10230 { FGRPdb_4 },
10231 { "fucomi", { ST, STi }, 0 },
10232 { "fcomi", { ST, STi }, 0 },
10233 { Bad_Opcode },
10234 },
10235 /* dc */
10236 {
10237 { "fadd", { STi, ST }, 0 },
10238 { "fmul", { STi, ST }, 0 },
10239 { Bad_Opcode },
10240 { Bad_Opcode },
10241 { "fsub{!M|r}", { STi, ST }, 0 },
10242 { "fsub{M|}", { STi, ST }, 0 },
10243 { "fdiv{!M|r}", { STi, ST }, 0 },
10244 { "fdiv{M|}", { STi, ST }, 0 },
10245 },
10246 /* dd */
10247 {
10248 { "ffree", { STi }, 0 },
10249 { Bad_Opcode },
10250 { "fst", { STi }, 0 },
10251 { "fstp", { STi }, 0 },
10252 { "fucom", { STi }, 0 },
10253 { "fucomp", { STi }, 0 },
10254 { Bad_Opcode },
10255 { Bad_Opcode },
10256 },
10257 /* de */
10258 {
10259 { "faddp", { STi, ST }, 0 },
10260 { "fmulp", { STi, ST }, 0 },
10261 { Bad_Opcode },
10262 { FGRPde_3 },
10263 { "fsub{!M|r}p", { STi, ST }, 0 },
10264 { "fsub{M|}p", { STi, ST }, 0 },
10265 { "fdiv{!M|r}p", { STi, ST }, 0 },
10266 { "fdiv{M|}p", { STi, ST }, 0 },
10267 },
10268 /* df */
10269 {
10270 { "ffreep", { STi }, 0 },
10271 { Bad_Opcode },
10272 { Bad_Opcode },
10273 { Bad_Opcode },
10274 { FGRPdf_4 },
10275 { "fucomip", { ST, STi }, 0 },
10276 { "fcomip", { ST, STi }, 0 },
10277 { Bad_Opcode },
10278 },
10279 };
10280
10281 static const char *const fgrps[][8] = {
10282 /* Bad opcode 0 */
10283 {
10284 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10285 },
10286
10287 /* d9_2 1 */
10288 {
10289 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10290 },
10291
10292 /* d9_4 2 */
10293 {
10294 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10295 },
10296
10297 /* d9_5 3 */
10298 {
10299 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10300 },
10301
10302 /* d9_6 4 */
10303 {
10304 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10305 },
10306
10307 /* d9_7 5 */
10308 {
10309 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10310 },
10311
10312 /* da_5 6 */
10313 {
10314 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10315 },
10316
10317 /* db_4 7 */
10318 {
10319 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10320 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10321 },
10322
10323 /* de_3 8 */
10324 {
10325 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10326 },
10327
10328 /* df_4 9 */
10329 {
10330 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10331 },
10332 };
10333
10334 static void
swap_operand(instr_info * ins)10335 swap_operand (instr_info *ins)
10336 {
10337 ins->mnemonicendp[0] = '.';
10338 ins->mnemonicendp[1] = 's';
10339 ins->mnemonicendp[2] = '\0';
10340 ins->mnemonicendp += 2;
10341 }
10342
10343 static bool
dofloat(instr_info * ins,int sizeflag)10344 dofloat (instr_info *ins, int sizeflag)
10345 {
10346 const struct dis386 *dp;
10347 unsigned char floatop = ins->codep[-1];
10348
10349 if (ins->modrm.mod != 3)
10350 {
10351 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10352
10353 putop (ins, float_mem[fp_indx], sizeflag);
10354 ins->obufp = ins->op_out[0];
10355 ins->op_ad = 2;
10356 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10357 }
10358 /* Skip mod/rm byte. */
10359 MODRM_CHECK;
10360 ins->codep++;
10361
10362 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10363 if (dp->name == NULL)
10364 {
10365 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10366
10367 /* Instruction fnstsw is only one with strange arg. */
10368 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10369 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10370 }
10371 else
10372 {
10373 putop (ins, dp->name, sizeflag);
10374
10375 ins->obufp = ins->op_out[0];
10376 ins->op_ad = 2;
10377 if (dp->op[0].rtn
10378 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10379 return false;
10380
10381 ins->obufp = ins->op_out[1];
10382 ins->op_ad = 1;
10383 if (dp->op[1].rtn
10384 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10385 return false;
10386 }
10387 return true;
10388 }
10389
10390 static bool
OP_ST(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10391 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10392 int sizeflag ATTRIBUTE_UNUSED)
10393 {
10394 oappend_register (ins, "%st");
10395 return true;
10396 }
10397
10398 static bool
OP_STi(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10399 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10400 int sizeflag ATTRIBUTE_UNUSED)
10401 {
10402 char scratch[8];
10403 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10404
10405 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10406 abort ();
10407 oappend_register (ins, scratch);
10408 return true;
10409 }
10410
10411 /* Capital letters in template are macros. */
10412 static int
putop(instr_info * ins,const char * in_template,int sizeflag)10413 putop (instr_info *ins, const char *in_template, int sizeflag)
10414 {
10415 const char *p;
10416 int alt = 0;
10417 int cond = 1;
10418 unsigned int l = 0, len = 0;
10419 char last[4];
10420 bool evex_printed = false;
10421
10422 /* We don't want to add any prefix or suffix to (bad), so return early. */
10423 if (!strncmp (in_template, "(bad)", 5))
10424 {
10425 oappend (ins, "(bad)");
10426 *ins->obufp = 0;
10427 ins->mnemonicendp = ins->obufp;
10428 return 0;
10429 }
10430
10431 for (p = in_template; *p; p++)
10432 {
10433 if (len > l)
10434 {
10435 if (l >= sizeof (last) || !ISUPPER (*p))
10436 abort ();
10437 last[l++] = *p;
10438 continue;
10439 }
10440 switch (*p)
10441 {
10442 default:
10443 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
10444 && !(ins->rex2 & 7) && !evex_printed)
10445 {
10446 oappend (ins, "{evex} ");
10447 evex_printed = true;
10448 }
10449 *ins->obufp++ = *p;
10450 break;
10451 case '%':
10452 len++;
10453 break;
10454 case '!':
10455 cond = 0;
10456 break;
10457 case '{':
10458 if (ins->intel_syntax)
10459 {
10460 while (*++p != '|')
10461 if (*p == '}' || *p == '\0')
10462 abort ();
10463 alt = 1;
10464 }
10465 break;
10466 case '|':
10467 while (*++p != '}')
10468 {
10469 if (*p == '\0')
10470 abort ();
10471 }
10472 break;
10473 case '}':
10474 alt = 0;
10475 break;
10476 case 'A':
10477 if (ins->intel_syntax)
10478 break;
10479 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10480 || (sizeflag & SUFFIX_ALWAYS))
10481 *ins->obufp++ = 'b';
10482 break;
10483 case 'B':
10484 if (l == 0)
10485 {
10486 case_B:
10487 if (ins->intel_syntax)
10488 break;
10489 if (sizeflag & SUFFIX_ALWAYS)
10490 *ins->obufp++ = 'b';
10491 }
10492 else if (l == 1 && last[0] == 'L')
10493 {
10494 if (ins->address_mode == mode_64bit
10495 && !(ins->prefixes & PREFIX_ADDR))
10496 {
10497 *ins->obufp++ = 'a';
10498 *ins->obufp++ = 'b';
10499 *ins->obufp++ = 's';
10500 }
10501
10502 goto case_B;
10503 }
10504 else
10505 abort ();
10506 break;
10507 case 'C':
10508 if (ins->intel_syntax && !alt)
10509 break;
10510 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10511 {
10512 if (sizeflag & DFLAG)
10513 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10514 else
10515 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10516 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10517 }
10518 break;
10519 case 'D':
10520 if (l == 1)
10521 {
10522 switch (last[0])
10523 {
10524 case 'X':
10525 if (!ins->vex.evex || ins->vex.w)
10526 *ins->obufp++ = 'd';
10527 else
10528 oappend (ins, "{bad}");
10529 break;
10530 default:
10531 abort ();
10532 }
10533 break;
10534 }
10535 if (l)
10536 abort ();
10537 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10538 break;
10539 USED_REX (REX_W);
10540 if (ins->modrm.mod == 3)
10541 {
10542 if (ins->rex & REX_W)
10543 *ins->obufp++ = 'q';
10544 else
10545 {
10546 if (sizeflag & DFLAG)
10547 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10548 else
10549 *ins->obufp++ = 'w';
10550 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10551 }
10552 }
10553 else
10554 *ins->obufp++ = 'w';
10555 break;
10556 case 'E':
10557 if (l == 1)
10558 {
10559 switch (last[0])
10560 {
10561 case 'X':
10562 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10563 || (ins->rex2 & 7)
10564 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10565 || !ins->vex.v || ins->vex.mask_register_specifier)
10566 break;
10567 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10568 merely distinguished by EVEX.W. Look for a use of the
10569 respective macro. */
10570 if (ins->vex.w)
10571 {
10572 const char *pct = strchr (p + 1, '%');
10573
10574 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10575 break;
10576 }
10577 *ins->obufp++ = '{';
10578 *ins->obufp++ = 'e';
10579 *ins->obufp++ = 'v';
10580 *ins->obufp++ = 'e';
10581 *ins->obufp++ = 'x';
10582 *ins->obufp++ = '}';
10583 *ins->obufp++ = ' ';
10584 break;
10585 case 'M':
10586 if (ins->modrm.mod != 3 && !(ins->rex2 & 7))
10587 oappend (ins, "{evex} ");
10588 evex_printed = true;
10589 break;
10590 default:
10591 abort ();
10592 }
10593 break;
10594 }
10595 /* For jcxz/jecxz */
10596 if (ins->address_mode == mode_64bit)
10597 {
10598 if (sizeflag & AFLAG)
10599 *ins->obufp++ = 'r';
10600 else
10601 *ins->obufp++ = 'e';
10602 }
10603 else
10604 if (sizeflag & AFLAG)
10605 *ins->obufp++ = 'e';
10606 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10607 break;
10608 case 'F':
10609 if (l == 0)
10610 {
10611 if (ins->intel_syntax)
10612 break;
10613 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10614 {
10615 if (sizeflag & AFLAG)
10616 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10617 else
10618 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10619 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10620 }
10621 }
10622 else if (l == 1 && last[0] == 'C')
10623 break;
10624 else if (l == 1 && last[0] == 'N')
10625 {
10626 if (ins->vex.nf)
10627 {
10628 oappend (ins, "{nf} ");
10629 /* This bit needs to be cleared after it is consumed. */
10630 ins->vex.nf = false;
10631 evex_printed = true;
10632 }
10633 else if (ins->evex_type == evex_from_vex && !(ins->rex2 & 7)
10634 && ins->vex.v)
10635 {
10636 oappend (ins, "{evex} ");
10637 evex_printed = true;
10638 }
10639 }
10640 else
10641 abort ();
10642 break;
10643 case 'G':
10644 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10645 && !(sizeflag & SUFFIX_ALWAYS)))
10646 break;
10647 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10648 *ins->obufp++ = 'l';
10649 else
10650 *ins->obufp++ = 'w';
10651 if (!(ins->rex & REX_W))
10652 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10653 break;
10654 case 'H':
10655 if (l == 0)
10656 {
10657 if (ins->intel_syntax)
10658 break;
10659 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10660 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10661 {
10662 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10663 *ins->obufp++ = ',';
10664 *ins->obufp++ = 'p';
10665
10666 /* Set active_seg_prefix even if not set in 64-bit mode
10667 because here it is a valid branch hint. */
10668 if (ins->prefixes & PREFIX_DS)
10669 {
10670 ins->active_seg_prefix = PREFIX_DS;
10671 *ins->obufp++ = 't';
10672 }
10673 else
10674 {
10675 ins->active_seg_prefix = PREFIX_CS;
10676 *ins->obufp++ = 'n';
10677 }
10678 }
10679 }
10680 else if (l == 1 && last[0] == 'X')
10681 {
10682 if (!ins->vex.w)
10683 *ins->obufp++ = 'h';
10684 else
10685 oappend (ins, "{bad}");
10686 }
10687 else
10688 abort ();
10689 break;
10690 case 'K':
10691 USED_REX (REX_W);
10692 if (ins->rex & REX_W)
10693 *ins->obufp++ = 'q';
10694 else
10695 *ins->obufp++ = 'd';
10696 break;
10697 case 'L':
10698 if (ins->intel_syntax)
10699 break;
10700 if (sizeflag & SUFFIX_ALWAYS)
10701 {
10702 if (ins->rex & REX_W)
10703 *ins->obufp++ = 'q';
10704 else
10705 *ins->obufp++ = 'l';
10706 }
10707 break;
10708 case 'M':
10709 if (ins->intel_mnemonic != cond)
10710 *ins->obufp++ = 'r';
10711 break;
10712 case 'N':
10713 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10714 *ins->obufp++ = 'n';
10715 else
10716 ins->used_prefixes |= PREFIX_FWAIT;
10717 break;
10718 case 'O':
10719 USED_REX (REX_W);
10720 if (ins->rex & REX_W)
10721 *ins->obufp++ = 'o';
10722 else if (ins->intel_syntax && (sizeflag & DFLAG))
10723 *ins->obufp++ = 'q';
10724 else
10725 *ins->obufp++ = 'd';
10726 if (!(ins->rex & REX_W))
10727 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10728 break;
10729 case '@':
10730 if (ins->address_mode == mode_64bit
10731 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10732 || !(ins->prefixes & PREFIX_DATA)))
10733 {
10734 if (sizeflag & SUFFIX_ALWAYS)
10735 *ins->obufp++ = 'q';
10736 break;
10737 }
10738 /* Fall through. */
10739 case 'P':
10740 if (l == 0)
10741 {
10742 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10743 {
10744 /* For pushp and popp, p is printed and do not print {rex2}
10745 for them. */
10746 *ins->obufp++ = 'p';
10747 ins->rex2 |= REX2_SPECIAL;
10748 break;
10749 }
10750
10751 /* For "!P" print nothing else in Intel syntax. */
10752 if (!cond && ins->intel_syntax)
10753 break;
10754
10755 if ((ins->modrm.mod == 3 || !cond)
10756 && !(sizeflag & SUFFIX_ALWAYS))
10757 break;
10758 /* Fall through. */
10759 case 'T':
10760 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10761 || ((sizeflag & SUFFIX_ALWAYS)
10762 && ins->address_mode != mode_64bit))
10763 {
10764 *ins->obufp++ = (sizeflag & DFLAG)
10765 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10766 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10767 }
10768 else if (sizeflag & SUFFIX_ALWAYS)
10769 *ins->obufp++ = 'q';
10770 }
10771 else if (l == 1 && last[0] == 'L')
10772 {
10773 if ((ins->prefixes & PREFIX_DATA)
10774 || (ins->rex & REX_W)
10775 || (sizeflag & SUFFIX_ALWAYS))
10776 {
10777 USED_REX (REX_W);
10778 if (ins->rex & REX_W)
10779 *ins->obufp++ = 'q';
10780 else
10781 {
10782 if (sizeflag & DFLAG)
10783 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10784 else
10785 *ins->obufp++ = 'w';
10786 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10787 }
10788 }
10789 }
10790 else
10791 abort ();
10792 break;
10793 case 'Q':
10794 if (l == 0)
10795 {
10796 if (ins->intel_syntax && !alt)
10797 break;
10798 USED_REX (REX_W);
10799 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10800 || (sizeflag & SUFFIX_ALWAYS))
10801 {
10802 if (ins->rex & REX_W)
10803 *ins->obufp++ = 'q';
10804 else
10805 {
10806 if (sizeflag & DFLAG)
10807 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10808 else
10809 *ins->obufp++ = 'w';
10810 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10811 }
10812 }
10813 }
10814 else if (l == 1 && last[0] == 'D')
10815 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10816 else if (l == 1 && last[0] == 'L')
10817 {
10818 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10819 : ins->address_mode != mode_64bit)
10820 break;
10821 if ((ins->rex & REX_W))
10822 {
10823 USED_REX (REX_W);
10824 *ins->obufp++ = 'q';
10825 }
10826 else if ((ins->address_mode == mode_64bit && cond)
10827 || (sizeflag & SUFFIX_ALWAYS))
10828 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10829 }
10830 else
10831 abort ();
10832 break;
10833 case 'R':
10834 USED_REX (REX_W);
10835 if (ins->rex & REX_W)
10836 *ins->obufp++ = 'q';
10837 else if (sizeflag & DFLAG)
10838 {
10839 if (ins->intel_syntax)
10840 *ins->obufp++ = 'd';
10841 else
10842 *ins->obufp++ = 'l';
10843 }
10844 else
10845 *ins->obufp++ = 'w';
10846 if (ins->intel_syntax && !p[1]
10847 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10848 *ins->obufp++ = 'e';
10849 if (!(ins->rex & REX_W))
10850 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10851 break;
10852 case 'S':
10853 if (l == 0)
10854 {
10855 case_S:
10856 if (ins->intel_syntax)
10857 break;
10858 if (sizeflag & SUFFIX_ALWAYS)
10859 {
10860 if (ins->rex & REX_W)
10861 *ins->obufp++ = 'q';
10862 else
10863 {
10864 if (sizeflag & DFLAG)
10865 *ins->obufp++ = 'l';
10866 else
10867 *ins->obufp++ = 'w';
10868 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10869 }
10870 }
10871 break;
10872 }
10873 if (l != 1)
10874 abort ();
10875 switch (last[0])
10876 {
10877 case 'L':
10878 if (ins->address_mode == mode_64bit
10879 && !(ins->prefixes & PREFIX_ADDR))
10880 {
10881 *ins->obufp++ = 'a';
10882 *ins->obufp++ = 'b';
10883 *ins->obufp++ = 's';
10884 }
10885
10886 goto case_S;
10887 case 'X':
10888 if (!ins->vex.evex || !ins->vex.w)
10889 *ins->obufp++ = 's';
10890 else
10891 oappend (ins, "{bad}");
10892 break;
10893 default:
10894 abort ();
10895 }
10896 break;
10897 case 'U':
10898 if (l == 1 && (last[0] == 'Z'))
10899 {
10900 /* Although IMUL/SETcc does not support NDD, the EVEX.ND bit is
10901 used to control whether its destination register has its upper
10902 bits zeroed. */
10903 if (ins->vex.nd)
10904 oappend (ins, "zu");
10905 }
10906 else
10907 abort ();
10908 break;
10909 case 'V':
10910 if (l == 0)
10911 {
10912 if (ins->need_vex)
10913 *ins->obufp++ = 'v';
10914 }
10915 else if (l == 1)
10916 {
10917 switch (last[0])
10918 {
10919 case 'X':
10920 if (ins->vex.evex)
10921 break;
10922 *ins->obufp++ = '{';
10923 *ins->obufp++ = 'v';
10924 *ins->obufp++ = 'e';
10925 *ins->obufp++ = 'x';
10926 *ins->obufp++ = '}';
10927 *ins->obufp++ = ' ';
10928 break;
10929 case 'L':
10930 if (ins->rex & REX_W)
10931 {
10932 *ins->obufp++ = 'a';
10933 *ins->obufp++ = 'b';
10934 *ins->obufp++ = 's';
10935 }
10936 goto case_S;
10937 default:
10938 abort ();
10939 }
10940 }
10941 else
10942 abort ();
10943 break;
10944 case 'W':
10945 if (l == 0)
10946 {
10947 /* operand size flag for cwtl, cbtw */
10948 USED_REX (REX_W);
10949 if (ins->rex & REX_W)
10950 {
10951 if (ins->intel_syntax)
10952 *ins->obufp++ = 'd';
10953 else
10954 *ins->obufp++ = 'l';
10955 }
10956 else if (sizeflag & DFLAG)
10957 *ins->obufp++ = 'w';
10958 else
10959 *ins->obufp++ = 'b';
10960 if (!(ins->rex & REX_W))
10961 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10962 }
10963 else if (l == 1)
10964 {
10965 if (!ins->need_vex)
10966 abort ();
10967 if (last[0] == 'X')
10968 *ins->obufp++ = ins->vex.w ? 'd': 's';
10969 else if (last[0] == 'B')
10970 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10971 else
10972 abort ();
10973 }
10974 else
10975 abort ();
10976 break;
10977 case 'X':
10978 if (l != 0)
10979 abort ();
10980 if (ins->need_vex
10981 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10982 : ins->prefixes & PREFIX_DATA)
10983 {
10984 *ins->obufp++ = 'd';
10985 ins->used_prefixes |= PREFIX_DATA;
10986 }
10987 else
10988 *ins->obufp++ = 's';
10989 break;
10990 case 'Y':
10991 if (l == 0)
10992 {
10993 if (ins->vex.mask_register_specifier)
10994 ins->illegal_masking = true;
10995 }
10996 else if (l == 1 && last[0] == 'X')
10997 {
10998 if (!ins->need_vex)
10999 break;
11000 if (ins->intel_syntax
11001 || ((ins->modrm.mod == 3 || ins->vex.b)
11002 && !(sizeflag & SUFFIX_ALWAYS)))
11003 break;
11004 switch (ins->vex.length)
11005 {
11006 case 128:
11007 *ins->obufp++ = 'x';
11008 break;
11009 case 256:
11010 *ins->obufp++ = 'y';
11011 break;
11012 case 512:
11013 if (!ins->vex.evex)
11014 default:
11015 abort ();
11016 }
11017 }
11018 else
11019 abort ();
11020 break;
11021 case 'Z':
11022 if (l == 0)
11023 {
11024 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
11025 ins->modrm.mod = 3;
11026 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
11027 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
11028 }
11029 else if (l == 1 && last[0] == 'X')
11030 {
11031 if (!ins->vex.evex)
11032 abort ();
11033 if (ins->intel_syntax
11034 || ((ins->modrm.mod == 3 || ins->vex.b)
11035 && !(sizeflag & SUFFIX_ALWAYS)))
11036 break;
11037 switch (ins->vex.length)
11038 {
11039 case 128:
11040 *ins->obufp++ = 'x';
11041 break;
11042 case 256:
11043 *ins->obufp++ = 'y';
11044 break;
11045 case 512:
11046 *ins->obufp++ = 'z';
11047 break;
11048 default:
11049 abort ();
11050 }
11051 }
11052 else
11053 abort ();
11054 break;
11055 case '^':
11056 if (ins->intel_syntax)
11057 break;
11058 if (ins->isa64 == intel64 && (ins->rex & REX_W))
11059 {
11060 USED_REX (REX_W);
11061 *ins->obufp++ = 'q';
11062 break;
11063 }
11064 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
11065 {
11066 if (sizeflag & DFLAG)
11067 *ins->obufp++ = 'l';
11068 else
11069 *ins->obufp++ = 'w';
11070 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11071 }
11072 break;
11073 }
11074
11075 if (len == l)
11076 len = l = 0;
11077 }
11078 *ins->obufp = 0;
11079 ins->mnemonicendp = ins->obufp;
11080 return 0;
11081 }
11082
11083 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
11084 the buffer pointed to by INS->obufp has space. A style marker is made
11085 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11086 digit, followed by another STYLE_MARKER_CHAR. This function assumes
11087 that the number of styles is not greater than 16. */
11088
11089 static void
oappend_insert_style(instr_info * ins,enum disassembler_style style)11090 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11091 {
11092 unsigned num = (unsigned) style;
11093
11094 /* We currently assume that STYLE can be encoded as a single hex
11095 character. If more styles are added then this might start to fail,
11096 and we'll need to expand this code. */
11097 if (num > 0xf)
11098 abort ();
11099
11100 *ins->obufp++ = STYLE_MARKER_CHAR;
11101 *ins->obufp++ = (num < 10 ? ('0' + num)
11102 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11103 *ins->obufp++ = STYLE_MARKER_CHAR;
11104
11105 /* This final null character is not strictly necessary, after inserting a
11106 style marker we should always be inserting some additional content.
11107 However, having the buffer null terminated doesn't cost much, and make
11108 it easier to debug what's going on. Also, if we do ever forget to add
11109 any additional content after this style marker, then the buffer will
11110 still be well formed. */
11111 *ins->obufp = '\0';
11112 }
11113
11114 static void
oappend_with_style(instr_info * ins,const char * s,enum disassembler_style style)11115 oappend_with_style (instr_info *ins, const char *s,
11116 enum disassembler_style style)
11117 {
11118 oappend_insert_style (ins, style);
11119 ins->obufp = stpcpy (ins->obufp, s);
11120 }
11121
11122 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11123 the style for the character as STYLE. */
11124
11125 static void
oappend_char_with_style(instr_info * ins,const char c,enum disassembler_style style)11126 oappend_char_with_style (instr_info *ins, const char c,
11127 enum disassembler_style style)
11128 {
11129 oappend_insert_style (ins, style);
11130 *ins->obufp++ = c;
11131 *ins->obufp = '\0';
11132 }
11133
11134 /* Like oappend_char_with_style, but always uses dis_style_text. */
11135
11136 static void
oappend_char(instr_info * ins,const char c)11137 oappend_char (instr_info *ins, const char c)
11138 {
11139 oappend_char_with_style (ins, c, dis_style_text);
11140 }
11141
11142 static void
append_seg(instr_info * ins)11143 append_seg (instr_info *ins)
11144 {
11145 /* Only print the active segment register. */
11146 if (!ins->active_seg_prefix)
11147 return;
11148
11149 ins->used_prefixes |= ins->active_seg_prefix;
11150 switch (ins->active_seg_prefix)
11151 {
11152 case PREFIX_CS:
11153 oappend_register (ins, att_names_seg[1]);
11154 break;
11155 case PREFIX_DS:
11156 oappend_register (ins, att_names_seg[3]);
11157 break;
11158 case PREFIX_SS:
11159 oappend_register (ins, att_names_seg[2]);
11160 break;
11161 case PREFIX_ES:
11162 oappend_register (ins, att_names_seg[0]);
11163 break;
11164 case PREFIX_FS:
11165 oappend_register (ins, att_names_seg[4]);
11166 break;
11167 case PREFIX_GS:
11168 oappend_register (ins, att_names_seg[5]);
11169 break;
11170 default:
11171 break;
11172 }
11173 oappend_char (ins, ':');
11174 }
11175
11176 static void
print_operand_value(instr_info * ins,bfd_vma disp,enum disassembler_style style)11177 print_operand_value (instr_info *ins, bfd_vma disp,
11178 enum disassembler_style style)
11179 {
11180 char tmp[30];
11181
11182 if (ins->address_mode != mode_64bit)
11183 disp &= 0xffffffff;
11184 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11185 oappend_with_style (ins, tmp, style);
11186 }
11187
11188 /* Like oappend, but called for immediate operands. */
11189
11190 static void
oappend_immediate(instr_info * ins,bfd_vma imm)11191 oappend_immediate (instr_info *ins, bfd_vma imm)
11192 {
11193 if (!ins->intel_syntax)
11194 oappend_char_with_style (ins, '$', dis_style_immediate);
11195 print_operand_value (ins, imm, dis_style_immediate);
11196 }
11197
11198 /* Put DISP in BUF as signed hex number. */
11199
11200 static void
print_displacement(instr_info * ins,bfd_signed_vma val)11201 print_displacement (instr_info *ins, bfd_signed_vma val)
11202 {
11203 char tmp[30];
11204
11205 if (val < 0)
11206 {
11207 oappend_char_with_style (ins, '-', dis_style_address_offset);
11208 val = (bfd_vma) 0 - val;
11209
11210 /* Check for possible overflow. */
11211 if (val < 0)
11212 {
11213 switch (ins->address_mode)
11214 {
11215 case mode_64bit:
11216 oappend_with_style (ins, "0x8000000000000000",
11217 dis_style_address_offset);
11218 break;
11219 case mode_32bit:
11220 oappend_with_style (ins, "0x80000000",
11221 dis_style_address_offset);
11222 break;
11223 case mode_16bit:
11224 oappend_with_style (ins, "0x8000",
11225 dis_style_address_offset);
11226 break;
11227 }
11228 return;
11229 }
11230 }
11231
11232 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11233 oappend_with_style (ins, tmp, dis_style_address_offset);
11234 }
11235
11236 static void
intel_operand_size(instr_info * ins,int bytemode,int sizeflag)11237 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11238 {
11239 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
11240 if (ins->vex.b && ins->evex_type == evex_default)
11241 {
11242 if (!ins->vex.no_broadcast)
11243 switch (bytemode)
11244 {
11245 case x_mode:
11246 case evex_half_bcst_xmmq_mode:
11247 if (ins->vex.w)
11248 oappend (ins, "QWORD BCST ");
11249 else
11250 oappend (ins, "DWORD BCST ");
11251 break;
11252 case xh_mode:
11253 case evex_half_bcst_xmmqh_mode:
11254 case evex_half_bcst_xmmqdh_mode:
11255 oappend (ins, "WORD BCST ");
11256 break;
11257 default:
11258 ins->vex.no_broadcast = true;
11259 break;
11260 }
11261 return;
11262 }
11263 switch (bytemode)
11264 {
11265 case b_mode:
11266 case b_swap_mode:
11267 case db_mode:
11268 oappend (ins, "BYTE PTR ");
11269 break;
11270 case w_mode:
11271 case w_swap_mode:
11272 case dw_mode:
11273 oappend (ins, "WORD PTR ");
11274 break;
11275 case indir_v_mode:
11276 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11277 {
11278 oappend (ins, "QWORD PTR ");
11279 break;
11280 }
11281 /* Fall through. */
11282 case stack_v_mode:
11283 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11284 || (ins->rex & REX_W)))
11285 {
11286 oappend (ins, "QWORD PTR ");
11287 break;
11288 }
11289 /* Fall through. */
11290 case v_mode:
11291 case v_swap_mode:
11292 case dq_mode:
11293 USED_REX (REX_W);
11294 if (ins->rex & REX_W)
11295 oappend (ins, "QWORD PTR ");
11296 else if (bytemode == dq_mode)
11297 oappend (ins, "DWORD PTR ");
11298 else
11299 {
11300 if (sizeflag & DFLAG)
11301 oappend (ins, "DWORD PTR ");
11302 else
11303 oappend (ins, "WORD PTR ");
11304 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11305 }
11306 break;
11307 case z_mode:
11308 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11309 *ins->obufp++ = 'D';
11310 oappend (ins, "WORD PTR ");
11311 if (!(ins->rex & REX_W))
11312 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11313 break;
11314 case a_mode:
11315 if (sizeflag & DFLAG)
11316 oappend (ins, "QWORD PTR ");
11317 else
11318 oappend (ins, "DWORD PTR ");
11319 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11320 break;
11321 case movsxd_mode:
11322 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11323 oappend (ins, "WORD PTR ");
11324 else
11325 oappend (ins, "DWORD PTR ");
11326 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11327 break;
11328 case d_mode:
11329 case d_swap_mode:
11330 oappend (ins, "DWORD PTR ");
11331 break;
11332 case q_mode:
11333 case q_swap_mode:
11334 oappend (ins, "QWORD PTR ");
11335 break;
11336 case m_mode:
11337 if (ins->address_mode == mode_64bit)
11338 oappend (ins, "QWORD PTR ");
11339 else
11340 oappend (ins, "DWORD PTR ");
11341 break;
11342 case f_mode:
11343 if (sizeflag & DFLAG)
11344 oappend (ins, "FWORD PTR ");
11345 else
11346 oappend (ins, "DWORD PTR ");
11347 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11348 break;
11349 case t_mode:
11350 oappend (ins, "TBYTE PTR ");
11351 break;
11352 case x_mode:
11353 case xh_mode:
11354 case x_swap_mode:
11355 case evex_x_gscat_mode:
11356 case evex_x_nobcst_mode:
11357 case bw_unit_mode:
11358 if (ins->need_vex)
11359 {
11360 switch (ins->vex.length)
11361 {
11362 case 128:
11363 oappend (ins, "XMMWORD PTR ");
11364 break;
11365 case 256:
11366 oappend (ins, "YMMWORD PTR ");
11367 break;
11368 case 512:
11369 oappend (ins, "ZMMWORD PTR ");
11370 break;
11371 default:
11372 abort ();
11373 }
11374 }
11375 else
11376 oappend (ins, "XMMWORD PTR ");
11377 break;
11378 case xmm_mode:
11379 oappend (ins, "XMMWORD PTR ");
11380 break;
11381 case ymm_mode:
11382 oappend (ins, "YMMWORD PTR ");
11383 break;
11384 case xmmq_mode:
11385 case evex_half_bcst_xmmqh_mode:
11386 case evex_half_bcst_xmmq_mode:
11387 switch (ins->vex.length)
11388 {
11389 case 0:
11390 case 128:
11391 oappend (ins, "QWORD PTR ");
11392 break;
11393 case 256:
11394 oappend (ins, "XMMWORD PTR ");
11395 break;
11396 case 512:
11397 oappend (ins, "YMMWORD PTR ");
11398 break;
11399 default:
11400 abort ();
11401 }
11402 break;
11403 case xmmdw_mode:
11404 if (!ins->need_vex)
11405 abort ();
11406
11407 switch (ins->vex.length)
11408 {
11409 case 128:
11410 oappend (ins, "WORD PTR ");
11411 break;
11412 case 256:
11413 oappend (ins, "DWORD PTR ");
11414 break;
11415 case 512:
11416 oappend (ins, "QWORD PTR ");
11417 break;
11418 default:
11419 abort ();
11420 }
11421 break;
11422 case xmmqd_mode:
11423 case evex_half_bcst_xmmqdh_mode:
11424 if (!ins->need_vex)
11425 abort ();
11426
11427 switch (ins->vex.length)
11428 {
11429 case 128:
11430 oappend (ins, "DWORD PTR ");
11431 break;
11432 case 256:
11433 oappend (ins, "QWORD PTR ");
11434 break;
11435 case 512:
11436 oappend (ins, "XMMWORD PTR ");
11437 break;
11438 default:
11439 abort ();
11440 }
11441 break;
11442 case ymmq_mode:
11443 if (!ins->need_vex)
11444 abort ();
11445
11446 switch (ins->vex.length)
11447 {
11448 case 128:
11449 oappend (ins, "QWORD PTR ");
11450 break;
11451 case 256:
11452 oappend (ins, "YMMWORD PTR ");
11453 break;
11454 case 512:
11455 oappend (ins, "ZMMWORD PTR ");
11456 break;
11457 default:
11458 abort ();
11459 }
11460 break;
11461 case o_mode:
11462 oappend (ins, "OWORD PTR ");
11463 break;
11464 case vex_vsib_d_w_dq_mode:
11465 case vex_vsib_q_w_dq_mode:
11466 if (!ins->need_vex)
11467 abort ();
11468 if (ins->vex.w)
11469 oappend (ins, "QWORD PTR ");
11470 else
11471 oappend (ins, "DWORD PTR ");
11472 break;
11473 case mask_bd_mode:
11474 if (!ins->need_vex || ins->vex.length != 128)
11475 abort ();
11476 if (ins->vex.w)
11477 oappend (ins, "DWORD PTR ");
11478 else
11479 oappend (ins, "BYTE PTR ");
11480 break;
11481 case mask_mode:
11482 if (!ins->need_vex)
11483 abort ();
11484 if (ins->vex.w)
11485 oappend (ins, "QWORD PTR ");
11486 else
11487 oappend (ins, "WORD PTR ");
11488 break;
11489 case v_bnd_mode:
11490 case v_bndmk_mode:
11491 default:
11492 break;
11493 }
11494 }
11495
11496 static void
print_register(instr_info * ins,unsigned int reg,unsigned int rexmask,int bytemode,int sizeflag)11497 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11498 int bytemode, int sizeflag)
11499 {
11500 const char (*names)[8];
11501
11502 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11503 as the consumer will inspect it only for the destination operand. */
11504 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11505 ins->illegal_masking = true;
11506
11507 USED_REX (rexmask);
11508 if (ins->rex & rexmask)
11509 reg += 8;
11510 if (ins->rex2 & rexmask)
11511 reg += 16;
11512
11513 switch (bytemode)
11514 {
11515 case b_mode:
11516 case b_swap_mode:
11517 if (reg & 4)
11518 USED_REX (0);
11519 if (ins->rex || ins->rex2)
11520 names = att_names8rex;
11521 else
11522 names = att_names8;
11523 break;
11524 case w_mode:
11525 names = att_names16;
11526 break;
11527 case d_mode:
11528 case dw_mode:
11529 case db_mode:
11530 names = att_names32;
11531 break;
11532 case q_mode:
11533 names = att_names64;
11534 break;
11535 case m_mode:
11536 case v_bnd_mode:
11537 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11538 break;
11539 case bnd_mode:
11540 case bnd_swap_mode:
11541 if (reg > 0x3)
11542 {
11543 oappend (ins, "(bad)");
11544 return;
11545 }
11546 names = att_names_bnd;
11547 break;
11548 case indir_v_mode:
11549 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11550 {
11551 names = att_names64;
11552 break;
11553 }
11554 /* Fall through. */
11555 case stack_v_mode:
11556 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11557 || (ins->rex & REX_W)))
11558 {
11559 names = att_names64;
11560 break;
11561 }
11562 bytemode = v_mode;
11563 /* Fall through. */
11564 case v_mode:
11565 case v_swap_mode:
11566 case dq_mode:
11567 USED_REX (REX_W);
11568 if (ins->rex & REX_W)
11569 names = att_names64;
11570 else if (bytemode != v_mode && bytemode != v_swap_mode)
11571 names = att_names32;
11572 else
11573 {
11574 if (sizeflag & DFLAG)
11575 names = att_names32;
11576 else
11577 names = att_names16;
11578 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11579 }
11580 break;
11581 case movsxd_mode:
11582 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11583 names = att_names16;
11584 else
11585 names = att_names32;
11586 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11587 break;
11588 case va_mode:
11589 names = (ins->address_mode == mode_64bit
11590 ? att_names64 : att_names32);
11591 if (!(ins->prefixes & PREFIX_ADDR))
11592 names = (ins->address_mode == mode_16bit
11593 ? att_names16 : names);
11594 else
11595 {
11596 /* Remove "addr16/addr32". */
11597 ins->all_prefixes[ins->last_addr_prefix] = 0;
11598 names = (ins->address_mode != mode_32bit
11599 ? att_names32 : att_names16);
11600 ins->used_prefixes |= PREFIX_ADDR;
11601 }
11602 break;
11603 case mask_bd_mode:
11604 case mask_mode:
11605 if (reg > 0x7)
11606 {
11607 oappend (ins, "(bad)");
11608 return;
11609 }
11610 names = att_names_mask;
11611 break;
11612 case 0:
11613 return;
11614 default:
11615 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11616 return;
11617 }
11618 oappend_register (ins, names[reg]);
11619 }
11620
11621 static bool
get8s(instr_info * ins,bfd_vma * res)11622 get8s (instr_info *ins, bfd_vma *res)
11623 {
11624 if (!fetch_code (ins->info, ins->codep + 1))
11625 return false;
11626 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11627 return true;
11628 }
11629
11630 static bool
get16(instr_info * ins,bfd_vma * res)11631 get16 (instr_info *ins, bfd_vma *res)
11632 {
11633 if (!fetch_code (ins->info, ins->codep + 2))
11634 return false;
11635 *res = *ins->codep++;
11636 *res |= (bfd_vma) *ins->codep++ << 8;
11637 return true;
11638 }
11639
11640 static bool
get16s(instr_info * ins,bfd_vma * res)11641 get16s (instr_info *ins, bfd_vma *res)
11642 {
11643 if (!get16 (ins, res))
11644 return false;
11645 *res = (*res ^ 0x8000) - 0x8000;
11646 return true;
11647 }
11648
11649 static bool
get32(instr_info * ins,bfd_vma * res)11650 get32 (instr_info *ins, bfd_vma *res)
11651 {
11652 if (!fetch_code (ins->info, ins->codep + 4))
11653 return false;
11654 *res = *ins->codep++;
11655 *res |= (bfd_vma) *ins->codep++ << 8;
11656 *res |= (bfd_vma) *ins->codep++ << 16;
11657 *res |= (bfd_vma) *ins->codep++ << 24;
11658 return true;
11659 }
11660
11661 static bool
get32s(instr_info * ins,bfd_vma * res)11662 get32s (instr_info *ins, bfd_vma *res)
11663 {
11664 if (!get32 (ins, res))
11665 return false;
11666
11667 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11668
11669 return true;
11670 }
11671
11672 static bool
get64(instr_info * ins,uint64_t * res)11673 get64 (instr_info *ins, uint64_t *res)
11674 {
11675 unsigned int a;
11676 unsigned int b;
11677
11678 if (!fetch_code (ins->info, ins->codep + 8))
11679 return false;
11680 a = *ins->codep++;
11681 a |= (unsigned int) *ins->codep++ << 8;
11682 a |= (unsigned int) *ins->codep++ << 16;
11683 a |= (unsigned int) *ins->codep++ << 24;
11684 b = *ins->codep++;
11685 b |= (unsigned int) *ins->codep++ << 8;
11686 b |= (unsigned int) *ins->codep++ << 16;
11687 b |= (unsigned int) *ins->codep++ << 24;
11688 *res = a + ((uint64_t) b << 32);
11689 return true;
11690 }
11691
11692 static void
set_op(instr_info * ins,bfd_vma op,bool riprel)11693 set_op (instr_info *ins, bfd_vma op, bool riprel)
11694 {
11695 ins->op_index[ins->op_ad] = ins->op_ad;
11696 if (ins->address_mode == mode_64bit)
11697 ins->op_address[ins->op_ad] = op;
11698 else /* Mask to get a 32-bit address. */
11699 ins->op_address[ins->op_ad] = op & 0xffffffff;
11700 ins->op_riprel[ins->op_ad] = riprel;
11701 }
11702
11703 static bool
BadOp(instr_info * ins)11704 BadOp (instr_info *ins)
11705 {
11706 /* Throw away prefixes and 1st. opcode byte. */
11707 struct dis_private *priv = ins->info->private_data;
11708
11709 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11710 ins->obufp = stpcpy (ins->obufp, "(bad)");
11711 return true;
11712 }
11713
11714 static bool
OP_Skip_MODRM(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)11715 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11716 int sizeflag ATTRIBUTE_UNUSED)
11717 {
11718 if (ins->modrm.mod != 3)
11719 return BadOp (ins);
11720
11721 /* Skip mod/rm byte. */
11722 MODRM_CHECK;
11723 ins->codep++;
11724 ins->has_skipped_modrm = true;
11725 return true;
11726 }
11727
11728 static bool
OP_E_memory(instr_info * ins,int bytemode,int sizeflag)11729 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11730 {
11731 int add = (ins->rex & REX_B) ? 8 : 0;
11732 int riprel = 0;
11733 int shift;
11734
11735 add += (ins->rex2 & REX_B) ? 16 : 0;
11736
11737 /* Handles EVEX other than APX EVEX-promoted instructions. */
11738 if (ins->vex.evex && ins->evex_type == evex_default)
11739 {
11740
11741 /* Zeroing-masking is invalid for memory destinations. Set the flag
11742 uniformly, as the consumer will inspect it only for the destination
11743 operand. */
11744 if (ins->vex.zeroing)
11745 ins->illegal_masking = true;
11746
11747 switch (bytemode)
11748 {
11749 case dw_mode:
11750 case w_mode:
11751 case w_swap_mode:
11752 shift = 1;
11753 break;
11754 case db_mode:
11755 case b_mode:
11756 shift = 0;
11757 break;
11758 case dq_mode:
11759 if (ins->address_mode != mode_64bit)
11760 {
11761 case d_mode:
11762 case d_swap_mode:
11763 shift = 2;
11764 break;
11765 }
11766 /* fall through */
11767 case vex_vsib_d_w_dq_mode:
11768 case vex_vsib_q_w_dq_mode:
11769 case evex_x_gscat_mode:
11770 shift = ins->vex.w ? 3 : 2;
11771 break;
11772 case xh_mode:
11773 case evex_half_bcst_xmmqh_mode:
11774 case evex_half_bcst_xmmqdh_mode:
11775 if (ins->vex.b)
11776 {
11777 shift = ins->vex.w ? 2 : 1;
11778 break;
11779 }
11780 /* Fall through. */
11781 case x_mode:
11782 case evex_half_bcst_xmmq_mode:
11783 if (ins->vex.b)
11784 {
11785 shift = ins->vex.w ? 3 : 2;
11786 break;
11787 }
11788 /* Fall through. */
11789 case xmmqd_mode:
11790 case xmmdw_mode:
11791 case xmmq_mode:
11792 case ymmq_mode:
11793 case evex_x_nobcst_mode:
11794 case x_swap_mode:
11795 switch (ins->vex.length)
11796 {
11797 case 128:
11798 shift = 4;
11799 break;
11800 case 256:
11801 shift = 5;
11802 break;
11803 case 512:
11804 shift = 6;
11805 break;
11806 default:
11807 abort ();
11808 }
11809 /* Make necessary corrections to shift for modes that need it. */
11810 if (bytemode == xmmq_mode
11811 || bytemode == evex_half_bcst_xmmqh_mode
11812 || bytemode == evex_half_bcst_xmmq_mode
11813 || (bytemode == ymmq_mode && ins->vex.length == 128))
11814 shift -= 1;
11815 else if (bytemode == xmmqd_mode
11816 || bytemode == evex_half_bcst_xmmqdh_mode)
11817 shift -= 2;
11818 else if (bytemode == xmmdw_mode)
11819 shift -= 3;
11820 break;
11821 case ymm_mode:
11822 shift = 5;
11823 break;
11824 case xmm_mode:
11825 shift = 4;
11826 break;
11827 case q_mode:
11828 case q_swap_mode:
11829 shift = 3;
11830 break;
11831 case bw_unit_mode:
11832 shift = ins->vex.w ? 1 : 0;
11833 break;
11834 default:
11835 abort ();
11836 }
11837 }
11838 else
11839 shift = 0;
11840
11841 USED_REX (REX_B);
11842 if (ins->intel_syntax)
11843 intel_operand_size (ins, bytemode, sizeflag);
11844 append_seg (ins);
11845
11846 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11847 {
11848 /* 32/64 bit address mode */
11849 bfd_vma disp = 0;
11850 int havedisp;
11851 int havebase;
11852 int needindex;
11853 int needaddr32;
11854 int base, rbase;
11855 int vindex = 0;
11856 int scale = 0;
11857 int addr32flag = !((sizeflag & AFLAG)
11858 || bytemode == v_bnd_mode
11859 || bytemode == v_bndmk_mode
11860 || bytemode == bnd_mode
11861 || bytemode == bnd_swap_mode);
11862 bool check_gather = false;
11863 const char (*indexes)[8] = NULL;
11864
11865 havebase = 1;
11866 base = ins->modrm.rm;
11867
11868 if (base == 4)
11869 {
11870 vindex = ins->sib.index;
11871 USED_REX (REX_X);
11872 if (ins->rex & REX_X)
11873 vindex += 8;
11874 switch (bytemode)
11875 {
11876 case vex_vsib_d_w_dq_mode:
11877 case vex_vsib_q_w_dq_mode:
11878 if (!ins->need_vex)
11879 abort ();
11880 if (ins->vex.evex)
11881 {
11882 /* S/G EVEX insns require EVEX.X4 not to be set. */
11883 if (ins->rex2 & REX_X)
11884 {
11885 oappend (ins, "(bad)");
11886 return true;
11887 }
11888
11889 if (!ins->vex.v)
11890 vindex += 16;
11891 check_gather = ins->obufp == ins->op_out[1];
11892 }
11893
11894 switch (ins->vex.length)
11895 {
11896 case 128:
11897 indexes = att_names_xmm;
11898 break;
11899 case 256:
11900 if (!ins->vex.w
11901 || bytemode == vex_vsib_q_w_dq_mode)
11902 indexes = att_names_ymm;
11903 else
11904 indexes = att_names_xmm;
11905 break;
11906 case 512:
11907 if (!ins->vex.w
11908 || bytemode == vex_vsib_q_w_dq_mode)
11909 indexes = att_names_zmm;
11910 else
11911 indexes = att_names_ymm;
11912 break;
11913 default:
11914 abort ();
11915 }
11916 break;
11917 default:
11918 if (ins->rex2 & REX_X)
11919 vindex += 16;
11920
11921 if (vindex != 4)
11922 indexes = ins->address_mode == mode_64bit && !addr32flag
11923 ? att_names64 : att_names32;
11924 break;
11925 }
11926 scale = ins->sib.scale;
11927 base = ins->sib.base;
11928 ins->codep++;
11929 }
11930 else
11931 {
11932 /* Check for mandatory SIB. */
11933 if (bytemode == vex_vsib_d_w_dq_mode
11934 || bytemode == vex_vsib_q_w_dq_mode
11935 || bytemode == vex_sibmem_mode)
11936 {
11937 oappend (ins, "(bad)");
11938 return true;
11939 }
11940 }
11941 rbase = base + add;
11942
11943 switch (ins->modrm.mod)
11944 {
11945 case 0:
11946 if (base == 5)
11947 {
11948 havebase = 0;
11949 if (ins->address_mode == mode_64bit && !ins->has_sib)
11950 riprel = 1;
11951 if (!get32s (ins, &disp))
11952 return false;
11953 if (riprel && bytemode == v_bndmk_mode)
11954 {
11955 oappend (ins, "(bad)");
11956 return true;
11957 }
11958 }
11959 break;
11960 case 1:
11961 if (!get8s (ins, &disp))
11962 return false;
11963 if (ins->vex.evex && shift > 0)
11964 disp <<= shift;
11965 break;
11966 case 2:
11967 if (!get32s (ins, &disp))
11968 return false;
11969 break;
11970 }
11971
11972 needindex = 0;
11973 needaddr32 = 0;
11974 if (ins->has_sib
11975 && !havebase
11976 && !indexes
11977 && ins->address_mode != mode_16bit)
11978 {
11979 if (ins->address_mode == mode_64bit)
11980 {
11981 if (addr32flag)
11982 {
11983 /* Without base nor index registers, zero-extend the
11984 lower 32-bit displacement to 64 bits. */
11985 disp &= 0xffffffff;
11986 needindex = 1;
11987 }
11988 needaddr32 = 1;
11989 }
11990 else
11991 {
11992 /* In 32-bit mode, we need index register to tell [offset]
11993 from [eiz*1 + offset]. */
11994 needindex = 1;
11995 }
11996 }
11997
11998 havedisp = (havebase
11999 || needindex
12000 || (ins->has_sib && (indexes || scale != 0)));
12001
12002 if (!ins->intel_syntax)
12003 if (ins->modrm.mod != 0 || base == 5)
12004 {
12005 if (havedisp || riprel)
12006 print_displacement (ins, disp);
12007 else
12008 print_operand_value (ins, disp, dis_style_address_offset);
12009 if (riprel)
12010 {
12011 set_op (ins, disp, true);
12012 oappend_char (ins, '(');
12013 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
12014 dis_style_register);
12015 oappend_char (ins, ')');
12016 }
12017 }
12018
12019 if ((havebase || indexes || needindex || needaddr32 || riprel)
12020 && (ins->address_mode != mode_64bit
12021 || ((bytemode != v_bnd_mode)
12022 && (bytemode != v_bndmk_mode)
12023 && (bytemode != bnd_mode)
12024 && (bytemode != bnd_swap_mode))))
12025 ins->used_prefixes |= PREFIX_ADDR;
12026
12027 if (havedisp || (ins->intel_syntax && riprel))
12028 {
12029 oappend_char (ins, ins->open_char);
12030 if (ins->intel_syntax && riprel)
12031 {
12032 set_op (ins, disp, true);
12033 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
12034 dis_style_register);
12035 }
12036 if (havebase)
12037 oappend_register
12038 (ins,
12039 (ins->address_mode == mode_64bit && !addr32flag
12040 ? att_names64 : att_names32)[rbase]);
12041 if (ins->has_sib)
12042 {
12043 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
12044 print index to tell base + index from base. */
12045 if (scale != 0
12046 || needindex
12047 || indexes
12048 || (havebase && base != ESP_REG_NUM))
12049 {
12050 if (!ins->intel_syntax || havebase)
12051 oappend_char (ins, ins->separator_char);
12052 if (indexes)
12053 {
12054 if (ins->address_mode == mode_64bit || vindex < 16)
12055 oappend_register (ins, indexes[vindex]);
12056 else
12057 oappend (ins, "(bad)");
12058 }
12059 else
12060 oappend_register (ins,
12061 ins->address_mode == mode_64bit
12062 && !addr32flag
12063 ? att_index64
12064 : att_index32);
12065
12066 oappend_char (ins, ins->scale_char);
12067 oappend_char_with_style (ins, '0' + (1 << scale),
12068 dis_style_immediate);
12069 }
12070 }
12071 if (ins->intel_syntax
12072 && (disp || ins->modrm.mod != 0 || base == 5))
12073 {
12074 if (!havedisp || (bfd_signed_vma) disp >= 0)
12075 oappend_char (ins, '+');
12076 if (havedisp)
12077 print_displacement (ins, disp);
12078 else
12079 print_operand_value (ins, disp, dis_style_address_offset);
12080 }
12081
12082 oappend_char (ins, ins->close_char);
12083
12084 if (check_gather)
12085 {
12086 /* Both XMM/YMM/ZMM registers must be distinct. */
12087 int modrm_reg = ins->modrm.reg;
12088
12089 if (ins->rex & REX_R)
12090 modrm_reg += 8;
12091 if (ins->rex2 & REX_R)
12092 modrm_reg += 16;
12093 if (vindex == modrm_reg)
12094 oappend (ins, "/(bad)");
12095 }
12096 }
12097 else if (ins->intel_syntax)
12098 {
12099 if (ins->modrm.mod != 0 || base == 5)
12100 {
12101 if (!ins->active_seg_prefix)
12102 {
12103 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12104 oappend (ins, ":");
12105 }
12106 print_operand_value (ins, disp, dis_style_text);
12107 }
12108 }
12109 }
12110 else if (bytemode == v_bnd_mode
12111 || bytemode == v_bndmk_mode
12112 || bytemode == bnd_mode
12113 || bytemode == bnd_swap_mode
12114 || bytemode == vex_vsib_d_w_dq_mode
12115 || bytemode == vex_vsib_q_w_dq_mode)
12116 {
12117 oappend (ins, "(bad)");
12118 return true;
12119 }
12120 else
12121 {
12122 /* 16 bit address mode */
12123 bfd_vma disp = 0;
12124
12125 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12126 switch (ins->modrm.mod)
12127 {
12128 case 0:
12129 if (ins->modrm.rm == 6)
12130 {
12131 case 2:
12132 if (!get16s (ins, &disp))
12133 return false;
12134 }
12135 break;
12136 case 1:
12137 if (!get8s (ins, &disp))
12138 return false;
12139 if (ins->vex.evex && shift > 0)
12140 disp <<= shift;
12141 break;
12142 }
12143
12144 if (!ins->intel_syntax)
12145 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12146 print_displacement (ins, disp);
12147
12148 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12149 {
12150 oappend_char (ins, ins->open_char);
12151 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12152 : att_index16[ins->modrm.rm]);
12153 if (ins->intel_syntax
12154 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12155 {
12156 if ((bfd_signed_vma) disp >= 0)
12157 oappend_char (ins, '+');
12158 print_displacement (ins, disp);
12159 }
12160
12161 oappend_char (ins, ins->close_char);
12162 }
12163 else if (ins->intel_syntax)
12164 {
12165 if (!ins->active_seg_prefix)
12166 {
12167 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12168 oappend (ins, ":");
12169 }
12170 print_operand_value (ins, disp & 0xffff, dis_style_text);
12171 }
12172 }
12173 if (ins->vex.b && ins->evex_type == evex_default)
12174 {
12175 ins->evex_used |= EVEX_b_used;
12176
12177 /* Broadcast can only ever be valid for memory sources. */
12178 if (ins->obufp == ins->op_out[0])
12179 ins->vex.no_broadcast = true;
12180
12181 if (!ins->vex.no_broadcast
12182 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12183 {
12184 if (bytemode == xh_mode)
12185 {
12186 switch (ins->vex.length)
12187 {
12188 case 128:
12189 oappend (ins, "{1to8}");
12190 break;
12191 case 256:
12192 oappend (ins, "{1to16}");
12193 break;
12194 case 512:
12195 oappend (ins, "{1to32}");
12196 break;
12197 default:
12198 abort ();
12199 }
12200 }
12201 else if (bytemode == q_mode
12202 || bytemode == ymmq_mode)
12203 ins->vex.no_broadcast = true;
12204 else if (ins->vex.w
12205 || bytemode == evex_half_bcst_xmmqdh_mode
12206 || bytemode == evex_half_bcst_xmmq_mode)
12207 {
12208 switch (ins->vex.length)
12209 {
12210 case 128:
12211 oappend (ins, "{1to2}");
12212 break;
12213 case 256:
12214 oappend (ins, "{1to4}");
12215 break;
12216 case 512:
12217 oappend (ins, "{1to8}");
12218 break;
12219 default:
12220 abort ();
12221 }
12222 }
12223 else if (bytemode == x_mode
12224 || bytemode == evex_half_bcst_xmmqh_mode)
12225 {
12226 switch (ins->vex.length)
12227 {
12228 case 128:
12229 oappend (ins, "{1to4}");
12230 break;
12231 case 256:
12232 oappend (ins, "{1to8}");
12233 break;
12234 case 512:
12235 oappend (ins, "{1to16}");
12236 break;
12237 default:
12238 abort ();
12239 }
12240 }
12241 else
12242 ins->vex.no_broadcast = true;
12243 }
12244 if (ins->vex.no_broadcast)
12245 oappend (ins, "{bad}");
12246 }
12247
12248 return true;
12249 }
12250
12251 static bool
OP_E(instr_info * ins,int bytemode,int sizeflag)12252 OP_E (instr_info *ins, int bytemode, int sizeflag)
12253 {
12254 /* Skip mod/rm byte. */
12255 MODRM_CHECK;
12256 if (!ins->has_skipped_modrm)
12257 {
12258 ins->codep++;
12259 ins->has_skipped_modrm = true;
12260 }
12261
12262 if (ins->modrm.mod == 3)
12263 {
12264 if ((sizeflag & SUFFIX_ALWAYS)
12265 && (bytemode == b_swap_mode
12266 || bytemode == bnd_swap_mode
12267 || bytemode == v_swap_mode))
12268 swap_operand (ins);
12269
12270 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12271 return true;
12272 }
12273
12274 /* Masking is invalid for insns with GPR-like memory destination. Set the
12275 flag uniformly, as the consumer will inspect it only for the destination
12276 operand. */
12277 if (ins->vex.mask_register_specifier)
12278 ins->illegal_masking = true;
12279
12280 return OP_E_memory (ins, bytemode, sizeflag);
12281 }
12282
12283 static bool
OP_indirE(instr_info * ins,int bytemode,int sizeflag)12284 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12285 {
12286 if (ins->modrm.mod == 3 && bytemode == f_mode)
12287 /* bad lcall/ljmp */
12288 return BadOp (ins);
12289 if (!ins->intel_syntax)
12290 oappend (ins, "*");
12291 return OP_E (ins, bytemode, sizeflag);
12292 }
12293
12294 static bool
OP_G(instr_info * ins,int bytemode,int sizeflag)12295 OP_G (instr_info *ins, int bytemode, int sizeflag)
12296 {
12297 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12298 return true;
12299 }
12300
12301 static bool
OP_REG(instr_info * ins,int code,int sizeflag)12302 OP_REG (instr_info *ins, int code, int sizeflag)
12303 {
12304 const char *s;
12305 int add = 0;
12306
12307 switch (code)
12308 {
12309 case es_reg: case ss_reg: case cs_reg:
12310 case ds_reg: case fs_reg: case gs_reg:
12311 oappend_register (ins, att_names_seg[code - es_reg]);
12312 return true;
12313 }
12314
12315 USED_REX (REX_B);
12316 if (ins->rex & REX_B)
12317 add = 8;
12318 if (ins->rex2 & REX_B)
12319 add += 16;
12320
12321 switch (code)
12322 {
12323 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12324 case sp_reg: case bp_reg: case si_reg: case di_reg:
12325 s = att_names16[code - ax_reg + add];
12326 break;
12327 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12328 USED_REX (0);
12329 /* Fall through. */
12330 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12331 if (ins->rex)
12332 s = att_names8rex[code - al_reg + add];
12333 else
12334 s = att_names8[code - al_reg];
12335 break;
12336 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12337 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12338 if (ins->address_mode == mode_64bit
12339 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12340 {
12341 s = att_names64[code - rAX_reg + add];
12342 break;
12343 }
12344 code += eAX_reg - rAX_reg;
12345 /* Fall through. */
12346 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12347 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12348 USED_REX (REX_W);
12349 if (ins->rex & REX_W)
12350 s = att_names64[code - eAX_reg + add];
12351 else
12352 {
12353 if (sizeflag & DFLAG)
12354 s = att_names32[code - eAX_reg + add];
12355 else
12356 s = att_names16[code - eAX_reg + add];
12357 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12358 }
12359 break;
12360 default:
12361 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12362 return true;
12363 }
12364 oappend_register (ins, s);
12365 return true;
12366 }
12367
12368 static bool
OP_IMREG(instr_info * ins,int code,int sizeflag)12369 OP_IMREG (instr_info *ins, int code, int sizeflag)
12370 {
12371 const char *s;
12372
12373 switch (code)
12374 {
12375 case indir_dx_reg:
12376 if (!ins->intel_syntax)
12377 {
12378 oappend (ins, "(%dx)");
12379 return true;
12380 }
12381 s = att_names16[dx_reg - ax_reg];
12382 break;
12383 case al_reg: case cl_reg:
12384 s = att_names8[code - al_reg];
12385 break;
12386 case eAX_reg:
12387 USED_REX (REX_W);
12388 if (ins->rex & REX_W)
12389 {
12390 s = *att_names64;
12391 break;
12392 }
12393 /* Fall through. */
12394 case z_mode_ax_reg:
12395 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12396 s = *att_names32;
12397 else
12398 s = *att_names16;
12399 if (!(ins->rex & REX_W))
12400 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12401 break;
12402 default:
12403 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12404 return true;
12405 }
12406 oappend_register (ins, s);
12407 return true;
12408 }
12409
12410 static bool
OP_I(instr_info * ins,int bytemode,int sizeflag)12411 OP_I (instr_info *ins, int bytemode, int sizeflag)
12412 {
12413 bfd_vma op;
12414
12415 switch (bytemode)
12416 {
12417 case b_mode:
12418 if (!fetch_code (ins->info, ins->codep + 1))
12419 return false;
12420 op = *ins->codep++;
12421 break;
12422 case v_mode:
12423 USED_REX (REX_W);
12424 if (ins->rex & REX_W)
12425 {
12426 if (!get32s (ins, &op))
12427 return false;
12428 }
12429 else
12430 {
12431 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12432 if (sizeflag & DFLAG)
12433 {
12434 case d_mode:
12435 if (!get32 (ins, &op))
12436 return false;
12437 }
12438 else
12439 {
12440 /* Fall through. */
12441 case w_mode:
12442 if (!get16 (ins, &op))
12443 return false;
12444 }
12445 }
12446 break;
12447 case const_1_mode:
12448 if (ins->intel_syntax)
12449 oappend (ins, "1");
12450 else
12451 oappend (ins, "$1");
12452 return true;
12453 default:
12454 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12455 return true;
12456 }
12457
12458 oappend_immediate (ins, op);
12459 return true;
12460 }
12461
12462 static bool
OP_I64(instr_info * ins,int bytemode,int sizeflag)12463 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12464 {
12465 uint64_t op;
12466
12467 if (bytemode != v_mode || ins->address_mode != mode_64bit
12468 || !(ins->rex & REX_W))
12469 return OP_I (ins, bytemode, sizeflag);
12470
12471 USED_REX (REX_W);
12472
12473 if (!get64 (ins, &op))
12474 return false;
12475
12476 oappend_immediate (ins, op);
12477 return true;
12478 }
12479
12480 static bool
OP_sI(instr_info * ins,int bytemode,int sizeflag)12481 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12482 {
12483 bfd_vma op;
12484
12485 switch (bytemode)
12486 {
12487 case b_mode:
12488 case b_T_mode:
12489 if (!get8s (ins, &op))
12490 return false;
12491 if (bytemode == b_T_mode)
12492 {
12493 if (ins->address_mode != mode_64bit
12494 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12495 {
12496 /* The operand-size prefix is overridden by a REX prefix. */
12497 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12498 op &= 0xffffffff;
12499 else
12500 op &= 0xffff;
12501 }
12502 }
12503 else
12504 {
12505 if (!(ins->rex & REX_W))
12506 {
12507 if (sizeflag & DFLAG)
12508 op &= 0xffffffff;
12509 else
12510 op &= 0xffff;
12511 }
12512 }
12513 break;
12514 case v_mode:
12515 /* The operand-size prefix is overridden by a REX prefix. */
12516 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12517 {
12518 if (!get16 (ins, &op))
12519 return false;
12520 }
12521 else if (!get32s (ins, &op))
12522 return false;
12523 break;
12524 default:
12525 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12526 return true;
12527 }
12528
12529 oappend_immediate (ins, op);
12530 return true;
12531 }
12532
12533 static bool
OP_J(instr_info * ins,int bytemode,int sizeflag)12534 OP_J (instr_info *ins, int bytemode, int sizeflag)
12535 {
12536 bfd_vma disp;
12537 bfd_vma mask = -1;
12538 bfd_vma segment = 0;
12539
12540 switch (bytemode)
12541 {
12542 case b_mode:
12543 if (!get8s (ins, &disp))
12544 return false;
12545 break;
12546 case v_mode:
12547 case dqw_mode:
12548 if ((sizeflag & DFLAG)
12549 || (ins->address_mode == mode_64bit
12550 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12551 || (ins->rex & REX_W))))
12552 {
12553 if (!get32s (ins, &disp))
12554 return false;
12555 }
12556 else
12557 {
12558 if (!get16s (ins, &disp))
12559 return false;
12560 /* In 16bit mode, address is wrapped around at 64k within
12561 the same segment. Otherwise, a data16 prefix on a jump
12562 instruction means that the pc is masked to 16 bits after
12563 the displacement is added! */
12564 mask = 0xffff;
12565 if ((ins->prefixes & PREFIX_DATA) == 0)
12566 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12567 & ~((bfd_vma) 0xffff));
12568 }
12569 if (ins->address_mode != mode_64bit
12570 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12571 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12572 break;
12573 default:
12574 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12575 return true;
12576 }
12577 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12578 | segment;
12579 set_op (ins, disp, false);
12580 print_operand_value (ins, disp, dis_style_text);
12581 return true;
12582 }
12583
12584 static bool
OP_SEG(instr_info * ins,int bytemode,int sizeflag)12585 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12586 {
12587 if (bytemode == w_mode)
12588 {
12589 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12590 return true;
12591 }
12592 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12593 }
12594
12595 static bool
OP_DIR(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag)12596 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12597 {
12598 bfd_vma seg, offset;
12599 int res;
12600 char scratch[24];
12601
12602 if (sizeflag & DFLAG)
12603 {
12604 if (!get32 (ins, &offset))
12605 return false;;
12606 }
12607 else if (!get16 (ins, &offset))
12608 return false;
12609 if (!get16 (ins, &seg))
12610 return false;;
12611 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12612
12613 res = snprintf (scratch, ARRAY_SIZE (scratch),
12614 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12615 (unsigned) seg, (unsigned) offset);
12616 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12617 abort ();
12618 oappend (ins, scratch);
12619 return true;
12620 }
12621
12622 static bool
OP_OFF(instr_info * ins,int bytemode,int sizeflag)12623 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12624 {
12625 bfd_vma off;
12626
12627 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12628 intel_operand_size (ins, bytemode, sizeflag);
12629 append_seg (ins);
12630
12631 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12632 {
12633 if (!get32 (ins, &off))
12634 return false;
12635 }
12636 else
12637 {
12638 if (!get16 (ins, &off))
12639 return false;
12640 }
12641
12642 if (ins->intel_syntax)
12643 {
12644 if (!ins->active_seg_prefix)
12645 {
12646 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12647 oappend (ins, ":");
12648 }
12649 }
12650 print_operand_value (ins, off, dis_style_address_offset);
12651 return true;
12652 }
12653
12654 static bool
OP_OFF64(instr_info * ins,int bytemode,int sizeflag)12655 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12656 {
12657 uint64_t off;
12658
12659 if (ins->address_mode != mode_64bit
12660 || (ins->prefixes & PREFIX_ADDR))
12661 return OP_OFF (ins, bytemode, sizeflag);
12662
12663 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12664 intel_operand_size (ins, bytemode, sizeflag);
12665 append_seg (ins);
12666
12667 if (!get64 (ins, &off))
12668 return false;
12669
12670 if (ins->intel_syntax)
12671 {
12672 if (!ins->active_seg_prefix)
12673 {
12674 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12675 oappend (ins, ":");
12676 }
12677 }
12678 print_operand_value (ins, off, dis_style_address_offset);
12679 return true;
12680 }
12681
12682 static void
ptr_reg(instr_info * ins,int code,int sizeflag)12683 ptr_reg (instr_info *ins, int code, int sizeflag)
12684 {
12685 const char *s;
12686
12687 *ins->obufp++ = ins->open_char;
12688 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12689 if (ins->address_mode == mode_64bit)
12690 {
12691 if (!(sizeflag & AFLAG))
12692 s = att_names32[code - eAX_reg];
12693 else
12694 s = att_names64[code - eAX_reg];
12695 }
12696 else if (sizeflag & AFLAG)
12697 s = att_names32[code - eAX_reg];
12698 else
12699 s = att_names16[code - eAX_reg];
12700 oappend_register (ins, s);
12701 oappend_char (ins, ins->close_char);
12702 }
12703
12704 static bool
OP_ESreg(instr_info * ins,int code,int sizeflag)12705 OP_ESreg (instr_info *ins, int code, int sizeflag)
12706 {
12707 if (ins->intel_syntax)
12708 {
12709 switch (ins->codep[-1])
12710 {
12711 case 0x6d: /* insw/insl */
12712 intel_operand_size (ins, z_mode, sizeflag);
12713 break;
12714 case 0xa5: /* movsw/movsl/movsq */
12715 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12716 case 0xab: /* stosw/stosl */
12717 case 0xaf: /* scasw/scasl */
12718 intel_operand_size (ins, v_mode, sizeflag);
12719 break;
12720 default:
12721 intel_operand_size (ins, b_mode, sizeflag);
12722 }
12723 }
12724 oappend_register (ins, att_names_seg[0]);
12725 oappend_char (ins, ':');
12726 ptr_reg (ins, code, sizeflag);
12727 return true;
12728 }
12729
12730 static bool
OP_DSreg(instr_info * ins,int code,int sizeflag)12731 OP_DSreg (instr_info *ins, int code, int sizeflag)
12732 {
12733 if (ins->intel_syntax)
12734 {
12735 switch (ins->codep[-1])
12736 {
12737 case 0x6f: /* outsw/outsl */
12738 intel_operand_size (ins, z_mode, sizeflag);
12739 break;
12740 case 0xa5: /* movsw/movsl/movsq */
12741 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12742 case 0xad: /* lodsw/lodsl/lodsq */
12743 intel_operand_size (ins, v_mode, sizeflag);
12744 break;
12745 default:
12746 intel_operand_size (ins, b_mode, sizeflag);
12747 }
12748 }
12749 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12750 default segment register DS is printed. */
12751 if (!ins->active_seg_prefix)
12752 ins->active_seg_prefix = PREFIX_DS;
12753 append_seg (ins);
12754 ptr_reg (ins, code, sizeflag);
12755 return true;
12756 }
12757
12758 static bool
OP_C(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12759 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12760 int sizeflag ATTRIBUTE_UNUSED)
12761 {
12762 int add, res;
12763 char scratch[8];
12764
12765 if (ins->rex & REX_R)
12766 {
12767 USED_REX (REX_R);
12768 add = 8;
12769 }
12770 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12771 {
12772 ins->all_prefixes[ins->last_lock_prefix] = 0;
12773 ins->used_prefixes |= PREFIX_LOCK;
12774 add = 8;
12775 }
12776 else
12777 add = 0;
12778 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12779 ins->modrm.reg + add);
12780 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12781 abort ();
12782 oappend_register (ins, scratch);
12783 return true;
12784 }
12785
12786 static bool
OP_D(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12787 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12788 int sizeflag ATTRIBUTE_UNUSED)
12789 {
12790 int add, res;
12791 char scratch[8];
12792
12793 USED_REX (REX_R);
12794 if (ins->rex & REX_R)
12795 add = 8;
12796 else
12797 add = 0;
12798 res = snprintf (scratch, ARRAY_SIZE (scratch),
12799 ins->intel_syntax ? "dr%d" : "%%db%d",
12800 ins->modrm.reg + add);
12801 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12802 abort ();
12803 oappend (ins, scratch);
12804 return true;
12805 }
12806
12807 static bool
OP_T(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12808 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12809 int sizeflag ATTRIBUTE_UNUSED)
12810 {
12811 int res;
12812 char scratch[8];
12813
12814 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12815 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12816 abort ();
12817 oappend_register (ins, scratch);
12818 return true;
12819 }
12820
12821 static bool
OP_MMX(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12822 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12823 int sizeflag ATTRIBUTE_UNUSED)
12824 {
12825 int reg = ins->modrm.reg;
12826 const char (*names)[8];
12827
12828 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12829 if (ins->prefixes & PREFIX_DATA)
12830 {
12831 names = att_names_xmm;
12832 USED_REX (REX_R);
12833 if (ins->rex & REX_R)
12834 reg += 8;
12835 }
12836 else
12837 names = att_names_mm;
12838 oappend_register (ins, names[reg]);
12839 return true;
12840 }
12841
12842 static void
print_vector_reg(instr_info * ins,unsigned int reg,int bytemode)12843 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12844 {
12845 const char (*names)[8];
12846
12847 if (bytemode == xmmq_mode
12848 || bytemode == evex_half_bcst_xmmqh_mode
12849 || bytemode == evex_half_bcst_xmmq_mode)
12850 {
12851 switch (ins->vex.length)
12852 {
12853 case 0:
12854 case 128:
12855 case 256:
12856 names = att_names_xmm;
12857 break;
12858 case 512:
12859 names = att_names_ymm;
12860 ins->evex_used |= EVEX_len_used;
12861 break;
12862 default:
12863 abort ();
12864 }
12865 }
12866 else if (bytemode == ymm_mode)
12867 names = att_names_ymm;
12868 else if (bytemode == tmm_mode)
12869 {
12870 if (reg >= 8)
12871 {
12872 oappend (ins, "(bad)");
12873 return;
12874 }
12875 names = att_names_tmm;
12876 }
12877 else if (ins->need_vex
12878 && bytemode != xmm_mode
12879 && bytemode != scalar_mode
12880 && bytemode != xmmdw_mode
12881 && bytemode != xmmqd_mode
12882 && bytemode != evex_half_bcst_xmmqdh_mode
12883 && bytemode != w_swap_mode
12884 && bytemode != b_mode
12885 && bytemode != w_mode
12886 && bytemode != d_mode
12887 && bytemode != q_mode)
12888 {
12889 ins->evex_used |= EVEX_len_used;
12890 switch (ins->vex.length)
12891 {
12892 case 128:
12893 names = att_names_xmm;
12894 break;
12895 case 256:
12896 if (ins->vex.w
12897 || bytemode != vex_vsib_q_w_dq_mode)
12898 names = att_names_ymm;
12899 else
12900 names = att_names_xmm;
12901 break;
12902 case 512:
12903 if (ins->vex.w
12904 || bytemode != vex_vsib_q_w_dq_mode)
12905 names = att_names_zmm;
12906 else
12907 names = att_names_ymm;
12908 break;
12909 default:
12910 abort ();
12911 }
12912 }
12913 else
12914 names = att_names_xmm;
12915 oappend_register (ins, names[reg]);
12916 }
12917
12918 static bool
OP_XMM(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)12919 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12920 {
12921 unsigned int reg = ins->modrm.reg;
12922
12923 USED_REX (REX_R);
12924 if (ins->rex & REX_R)
12925 reg += 8;
12926 if (ins->vex.evex)
12927 {
12928 if (ins->rex2 & REX_R)
12929 reg += 16;
12930 }
12931
12932 if (bytemode == tmm_mode)
12933 ins->modrm.reg = reg;
12934 else if (bytemode == scalar_mode)
12935 ins->vex.no_broadcast = true;
12936
12937 print_vector_reg (ins, reg, bytemode);
12938 return true;
12939 }
12940
12941 static bool
OP_EM(instr_info * ins,int bytemode,int sizeflag)12942 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12943 {
12944 int reg;
12945 const char (*names)[8];
12946
12947 if (ins->modrm.mod != 3)
12948 {
12949 if (ins->intel_syntax
12950 && (bytemode == v_mode || bytemode == v_swap_mode))
12951 {
12952 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12953 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12954 }
12955 return OP_E (ins, bytemode, sizeflag);
12956 }
12957
12958 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12959 swap_operand (ins);
12960
12961 /* Skip mod/rm byte. */
12962 MODRM_CHECK;
12963 ins->codep++;
12964 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12965 reg = ins->modrm.rm;
12966 if (ins->prefixes & PREFIX_DATA)
12967 {
12968 names = att_names_xmm;
12969 USED_REX (REX_B);
12970 if (ins->rex & REX_B)
12971 reg += 8;
12972 }
12973 else
12974 names = att_names_mm;
12975 oappend_register (ins, names[reg]);
12976 return true;
12977 }
12978
12979 /* cvt* are the only instructions in sse2 which have
12980 both SSE and MMX operands and also have 0x66 prefix
12981 in their opcode. 0x66 was originally used to differentiate
12982 between SSE and MMX instruction(operands). So we have to handle the
12983 cvt* separately using OP_EMC and OP_MXC */
12984 static bool
OP_EMC(instr_info * ins,int bytemode,int sizeflag)12985 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12986 {
12987 if (ins->modrm.mod != 3)
12988 {
12989 if (ins->intel_syntax && bytemode == v_mode)
12990 {
12991 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12992 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12993 }
12994 return OP_E (ins, bytemode, sizeflag);
12995 }
12996
12997 /* Skip mod/rm byte. */
12998 MODRM_CHECK;
12999 ins->codep++;
13000 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13001 oappend_register (ins, att_names_mm[ins->modrm.rm]);
13002 return true;
13003 }
13004
13005 static bool
OP_MXC(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13006 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13007 int sizeflag ATTRIBUTE_UNUSED)
13008 {
13009 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13010 oappend_register (ins, att_names_mm[ins->modrm.reg]);
13011 return true;
13012 }
13013
13014 static bool
OP_EX(instr_info * ins,int bytemode,int sizeflag)13015 OP_EX (instr_info *ins, int bytemode, int sizeflag)
13016 {
13017 int reg;
13018
13019 /* Skip mod/rm byte. */
13020 MODRM_CHECK;
13021 ins->codep++;
13022
13023 if (bytemode == dq_mode)
13024 bytemode = ins->vex.w ? q_mode : d_mode;
13025
13026 if (ins->modrm.mod != 3)
13027 return OP_E_memory (ins, bytemode, sizeflag);
13028
13029 reg = ins->modrm.rm;
13030 USED_REX (REX_B);
13031 if (ins->rex & REX_B)
13032 reg += 8;
13033 if (ins->rex2 & REX_B)
13034 reg += 16;
13035 if (ins->vex.evex)
13036 {
13037 USED_REX (REX_X);
13038 if ((ins->rex & REX_X))
13039 reg += 16;
13040 }
13041
13042 if ((sizeflag & SUFFIX_ALWAYS)
13043 && (bytemode == x_swap_mode
13044 || bytemode == w_swap_mode
13045 || bytemode == d_swap_mode
13046 || bytemode == q_swap_mode))
13047 swap_operand (ins);
13048
13049 if (bytemode == tmm_mode)
13050 ins->modrm.rm = reg;
13051
13052 print_vector_reg (ins, reg, bytemode);
13053 return true;
13054 }
13055
13056 static bool
OP_R(instr_info * ins,int bytemode,int sizeflag)13057 OP_R (instr_info *ins, int bytemode, int sizeflag)
13058 {
13059 if (ins->modrm.mod != 3)
13060 return BadOp (ins);
13061
13062 switch (bytemode)
13063 {
13064 case d_mode:
13065 case dq_mode:
13066 case q_mode:
13067 case mask_mode:
13068 return OP_E (ins, bytemode, sizeflag);
13069 case q_mm_mode:
13070 return OP_EM (ins, x_mode, sizeflag);
13071 case xmm_mode:
13072 if (ins->vex.length <= 128)
13073 break;
13074 return BadOp (ins);
13075 }
13076
13077 return OP_EX (ins, bytemode, sizeflag);
13078 }
13079
13080 static bool
OP_M(instr_info * ins,int bytemode,int sizeflag)13081 OP_M (instr_info *ins, int bytemode, int sizeflag)
13082 {
13083 /* Skip mod/rm byte. */
13084 MODRM_CHECK;
13085 ins->codep++;
13086
13087 if (ins->modrm.mod == 3)
13088 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13089 return BadOp (ins);
13090
13091 if (bytemode == x_mode)
13092 ins->vex.no_broadcast = true;
13093
13094 return OP_E_memory (ins, bytemode, sizeflag);
13095 }
13096
13097 static bool
OP_0f07(instr_info * ins,int bytemode,int sizeflag)13098 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13099 {
13100 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13101 return BadOp (ins);
13102 return OP_E (ins, bytemode, sizeflag);
13103 }
13104
13105 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13106 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13107
13108 static bool
NOP_Fixup(instr_info * ins,int opnd,int sizeflag)13109 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13110 {
13111 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13112 {
13113 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13114 return true;
13115 }
13116 if (opnd == 0)
13117 return OP_REG (ins, eAX_reg, sizeflag);
13118 return OP_IMREG (ins, eAX_reg, sizeflag);
13119 }
13120
13121 static const char *const Suffix3DNow[] = {
13122 /* 00 */ NULL, NULL, NULL, NULL,
13123 /* 04 */ NULL, NULL, NULL, NULL,
13124 /* 08 */ NULL, NULL, NULL, NULL,
13125 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13126 /* 10 */ NULL, NULL, NULL, NULL,
13127 /* 14 */ NULL, NULL, NULL, NULL,
13128 /* 18 */ NULL, NULL, NULL, NULL,
13129 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13130 /* 20 */ NULL, NULL, NULL, NULL,
13131 /* 24 */ NULL, NULL, NULL, NULL,
13132 /* 28 */ NULL, NULL, NULL, NULL,
13133 /* 2C */ NULL, NULL, NULL, NULL,
13134 /* 30 */ NULL, NULL, NULL, NULL,
13135 /* 34 */ NULL, NULL, NULL, NULL,
13136 /* 38 */ NULL, NULL, NULL, NULL,
13137 /* 3C */ NULL, NULL, NULL, NULL,
13138 /* 40 */ NULL, NULL, NULL, NULL,
13139 /* 44 */ NULL, NULL, NULL, NULL,
13140 /* 48 */ NULL, NULL, NULL, NULL,
13141 /* 4C */ NULL, NULL, NULL, NULL,
13142 /* 50 */ NULL, NULL, NULL, NULL,
13143 /* 54 */ NULL, NULL, NULL, NULL,
13144 /* 58 */ NULL, NULL, NULL, NULL,
13145 /* 5C */ NULL, NULL, NULL, NULL,
13146 /* 60 */ NULL, NULL, NULL, NULL,
13147 /* 64 */ NULL, NULL, NULL, NULL,
13148 /* 68 */ NULL, NULL, NULL, NULL,
13149 /* 6C */ NULL, NULL, NULL, NULL,
13150 /* 70 */ NULL, NULL, NULL, NULL,
13151 /* 74 */ NULL, NULL, NULL, NULL,
13152 /* 78 */ NULL, NULL, NULL, NULL,
13153 /* 7C */ NULL, NULL, NULL, NULL,
13154 /* 80 */ NULL, NULL, NULL, NULL,
13155 /* 84 */ NULL, NULL, NULL, NULL,
13156 /* 88 */ NULL, NULL, "pfnacc", NULL,
13157 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13158 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13159 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13160 /* 98 */ NULL, NULL, "pfsub", NULL,
13161 /* 9C */ NULL, NULL, "pfadd", NULL,
13162 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13163 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13164 /* A8 */ NULL, NULL, "pfsubr", NULL,
13165 /* AC */ NULL, NULL, "pfacc", NULL,
13166 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13167 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13168 /* B8 */ NULL, NULL, NULL, "pswapd",
13169 /* BC */ NULL, NULL, NULL, "pavgusb",
13170 /* C0 */ NULL, NULL, NULL, NULL,
13171 /* C4 */ NULL, NULL, NULL, NULL,
13172 /* C8 */ NULL, NULL, NULL, NULL,
13173 /* CC */ NULL, NULL, NULL, NULL,
13174 /* D0 */ NULL, NULL, NULL, NULL,
13175 /* D4 */ NULL, NULL, NULL, NULL,
13176 /* D8 */ NULL, NULL, NULL, NULL,
13177 /* DC */ NULL, NULL, NULL, NULL,
13178 /* E0 */ NULL, NULL, NULL, NULL,
13179 /* E4 */ NULL, NULL, NULL, NULL,
13180 /* E8 */ NULL, NULL, NULL, NULL,
13181 /* EC */ NULL, NULL, NULL, NULL,
13182 /* F0 */ NULL, NULL, NULL, NULL,
13183 /* F4 */ NULL, NULL, NULL, NULL,
13184 /* F8 */ NULL, NULL, NULL, NULL,
13185 /* FC */ NULL, NULL, NULL, NULL,
13186 };
13187
13188 static bool
OP_3DNowSuffix(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13189 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13190 int sizeflag ATTRIBUTE_UNUSED)
13191 {
13192 const char *mnemonic;
13193
13194 if (!fetch_code (ins->info, ins->codep + 1))
13195 return false;
13196 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13197 place where an 8-bit immediate would normally go. ie. the last
13198 byte of the instruction. */
13199 ins->obufp = ins->mnemonicendp;
13200 mnemonic = Suffix3DNow[*ins->codep++];
13201 if (mnemonic)
13202 ins->obufp = stpcpy (ins->obufp, mnemonic);
13203 else
13204 {
13205 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13206 of the opcode (0x0f0f) and the opcode suffix, we need to do
13207 all the ins->modrm processing first, and don't know until now that
13208 we have a bad opcode. This necessitates some cleaning up. */
13209 ins->op_out[0][0] = '\0';
13210 ins->op_out[1][0] = '\0';
13211 BadOp (ins);
13212 }
13213 ins->mnemonicendp = ins->obufp;
13214 return true;
13215 }
13216
13217 static const struct op simd_cmp_op[] =
13218 {
13219 { STRING_COMMA_LEN ("eq") },
13220 { STRING_COMMA_LEN ("lt") },
13221 { STRING_COMMA_LEN ("le") },
13222 { STRING_COMMA_LEN ("unord") },
13223 { STRING_COMMA_LEN ("neq") },
13224 { STRING_COMMA_LEN ("nlt") },
13225 { STRING_COMMA_LEN ("nle") },
13226 { STRING_COMMA_LEN ("ord") }
13227 };
13228
13229 static const struct op vex_cmp_op[] =
13230 {
13231 { STRING_COMMA_LEN ("eq_uq") },
13232 { STRING_COMMA_LEN ("nge") },
13233 { STRING_COMMA_LEN ("ngt") },
13234 { STRING_COMMA_LEN ("false") },
13235 { STRING_COMMA_LEN ("neq_oq") },
13236 { STRING_COMMA_LEN ("ge") },
13237 { STRING_COMMA_LEN ("gt") },
13238 { STRING_COMMA_LEN ("true") },
13239 { STRING_COMMA_LEN ("eq_os") },
13240 { STRING_COMMA_LEN ("lt_oq") },
13241 { STRING_COMMA_LEN ("le_oq") },
13242 { STRING_COMMA_LEN ("unord_s") },
13243 { STRING_COMMA_LEN ("neq_us") },
13244 { STRING_COMMA_LEN ("nlt_uq") },
13245 { STRING_COMMA_LEN ("nle_uq") },
13246 { STRING_COMMA_LEN ("ord_s") },
13247 { STRING_COMMA_LEN ("eq_us") },
13248 { STRING_COMMA_LEN ("nge_uq") },
13249 { STRING_COMMA_LEN ("ngt_uq") },
13250 { STRING_COMMA_LEN ("false_os") },
13251 { STRING_COMMA_LEN ("neq_os") },
13252 { STRING_COMMA_LEN ("ge_oq") },
13253 { STRING_COMMA_LEN ("gt_oq") },
13254 { STRING_COMMA_LEN ("true_us") },
13255 };
13256
13257 static bool
CMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13258 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13259 int sizeflag ATTRIBUTE_UNUSED)
13260 {
13261 unsigned int cmp_type;
13262
13263 if (!fetch_code (ins->info, ins->codep + 1))
13264 return false;
13265 cmp_type = *ins->codep++;
13266 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13267 {
13268 char suffix[3];
13269 char *p = ins->mnemonicendp - 2;
13270 suffix[0] = p[0];
13271 suffix[1] = p[1];
13272 suffix[2] = '\0';
13273 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13274 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13275 }
13276 else if (ins->need_vex
13277 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13278 {
13279 char suffix[3];
13280 char *p = ins->mnemonicendp - 2;
13281 suffix[0] = p[0];
13282 suffix[1] = p[1];
13283 suffix[2] = '\0';
13284 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13285 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13286 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13287 }
13288 else
13289 {
13290 /* We have a reserved extension byte. Output it directly. */
13291 oappend_immediate (ins, cmp_type);
13292 }
13293 return true;
13294 }
13295
13296 static bool
OP_Mwait(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13297 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13298 {
13299 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13300 if (!ins->intel_syntax)
13301 {
13302 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13303 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13304 if (bytemode == eBX_reg)
13305 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13306 ins->two_source_ops = true;
13307 }
13308 /* Skip mod/rm byte. */
13309 MODRM_CHECK;
13310 ins->codep++;
13311 return true;
13312 }
13313
13314 static bool
OP_Monitor(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13315 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13316 int sizeflag ATTRIBUTE_UNUSED)
13317 {
13318 /* monitor %{e,r,}ax,%ecx,%edx" */
13319 if (!ins->intel_syntax)
13320 {
13321 const char (*names)[8] = (ins->address_mode == mode_64bit
13322 ? att_names64 : att_names32);
13323
13324 if (ins->prefixes & PREFIX_ADDR)
13325 {
13326 /* Remove "addr16/addr32". */
13327 ins->all_prefixes[ins->last_addr_prefix] = 0;
13328 names = (ins->address_mode != mode_32bit
13329 ? att_names32 : att_names16);
13330 ins->used_prefixes |= PREFIX_ADDR;
13331 }
13332 else if (ins->address_mode == mode_16bit)
13333 names = att_names16;
13334 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13335 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13336 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13337 ins->two_source_ops = true;
13338 }
13339 /* Skip mod/rm byte. */
13340 MODRM_CHECK;
13341 ins->codep++;
13342 return true;
13343 }
13344
13345 static bool
REP_Fixup(instr_info * ins,int bytemode,int sizeflag)13346 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13347 {
13348 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13349 lods and stos. */
13350 if (ins->prefixes & PREFIX_REPZ)
13351 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13352
13353 switch (bytemode)
13354 {
13355 case al_reg:
13356 case eAX_reg:
13357 case indir_dx_reg:
13358 return OP_IMREG (ins, bytemode, sizeflag);
13359 case eDI_reg:
13360 return OP_ESreg (ins, bytemode, sizeflag);
13361 case eSI_reg:
13362 return OP_DSreg (ins, bytemode, sizeflag);
13363 default:
13364 abort ();
13365 break;
13366 }
13367 return true;
13368 }
13369
13370 static bool
SEP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13371 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13372 int sizeflag ATTRIBUTE_UNUSED)
13373 {
13374 if (ins->isa64 != amd64)
13375 return true;
13376
13377 ins->obufp = ins->obuf;
13378 BadOp (ins);
13379 ins->mnemonicendp = ins->obufp;
13380 ++ins->codep;
13381 return true;
13382 }
13383
13384 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13385 "bnd". */
13386
13387 static bool
BND_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13388 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13389 int sizeflag ATTRIBUTE_UNUSED)
13390 {
13391 if (ins->prefixes & PREFIX_REPNZ)
13392 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13393 return true;
13394 }
13395
13396 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13397 "notrack". */
13398
13399 static bool
NOTRACK_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13400 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13401 int sizeflag ATTRIBUTE_UNUSED)
13402 {
13403 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13404 we've seen a PREFIX_DS. */
13405 if ((ins->prefixes & PREFIX_DS) != 0
13406 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13407 {
13408 /* NOTRACK prefix is only valid on indirect branch instructions.
13409 NB: DATA prefix is unsupported for Intel64. */
13410 ins->active_seg_prefix = 0;
13411 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13412 }
13413 return true;
13414 }
13415
13416 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13417 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13418 */
13419
13420 static bool
HLE_Fixup1(instr_info * ins,int bytemode,int sizeflag)13421 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13422 {
13423 if (ins->modrm.mod != 3
13424 && (ins->prefixes & PREFIX_LOCK) != 0)
13425 {
13426 if (ins->prefixes & PREFIX_REPZ)
13427 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13428 if (ins->prefixes & PREFIX_REPNZ)
13429 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13430 }
13431
13432 return OP_E (ins, bytemode, sizeflag);
13433 }
13434
13435 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13436 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13437 */
13438
13439 static bool
HLE_Fixup2(instr_info * ins,int bytemode,int sizeflag)13440 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13441 {
13442 if (ins->modrm.mod != 3)
13443 {
13444 if (ins->prefixes & PREFIX_REPZ)
13445 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13446 if (ins->prefixes & PREFIX_REPNZ)
13447 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13448 }
13449
13450 return OP_E (ins, bytemode, sizeflag);
13451 }
13452
13453 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13454 "xrelease" for memory operand. No check for LOCK prefix. */
13455
13456 static bool
HLE_Fixup3(instr_info * ins,int bytemode,int sizeflag)13457 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13458 {
13459 if (ins->modrm.mod != 3
13460 && ins->last_repz_prefix > ins->last_repnz_prefix
13461 && (ins->prefixes & PREFIX_REPZ) != 0)
13462 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13463
13464 return OP_E (ins, bytemode, sizeflag);
13465 }
13466
13467 static bool
CMPXCHG8B_Fixup(instr_info * ins,int bytemode,int sizeflag)13468 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13469 {
13470 USED_REX (REX_W);
13471 if (ins->rex & REX_W)
13472 {
13473 /* Change cmpxchg8b to cmpxchg16b. */
13474 char *p = ins->mnemonicendp - 2;
13475 ins->mnemonicendp = stpcpy (p, "16b");
13476 bytemode = o_mode;
13477 }
13478 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13479 {
13480 if (ins->prefixes & PREFIX_REPZ)
13481 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13482 if (ins->prefixes & PREFIX_REPNZ)
13483 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13484 }
13485
13486 return OP_M (ins, bytemode, sizeflag);
13487 }
13488
13489 static bool
XMM_Fixup(instr_info * ins,int reg,int sizeflag ATTRIBUTE_UNUSED)13490 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13491 {
13492 const char (*names)[8] = att_names_xmm;
13493
13494 if (ins->need_vex)
13495 {
13496 switch (ins->vex.length)
13497 {
13498 case 128:
13499 break;
13500 case 256:
13501 names = att_names_ymm;
13502 break;
13503 default:
13504 abort ();
13505 }
13506 }
13507 oappend_register (ins, names[reg]);
13508 return true;
13509 }
13510
13511 static bool
FXSAVE_Fixup(instr_info * ins,int bytemode,int sizeflag)13512 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13513 {
13514 /* Add proper suffix to "fxsave" and "fxrstor". */
13515 USED_REX (REX_W);
13516 if (ins->rex & REX_W)
13517 {
13518 char *p = ins->mnemonicendp;
13519 *p++ = '6';
13520 *p++ = '4';
13521 *p = '\0';
13522 ins->mnemonicendp = p;
13523 }
13524 return OP_M (ins, bytemode, sizeflag);
13525 }
13526
13527 /* Display the destination register operand for instructions with
13528 VEX. */
13529
13530 static bool
OP_VEX(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13531 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13532 {
13533 int reg, modrm_reg, sib_index = -1;
13534 const char (*names)[8];
13535
13536 if (!ins->need_vex)
13537 return true;
13538
13539 if (ins->evex_type == evex_from_legacy)
13540 {
13541 ins->evex_used |= EVEX_b_used;
13542 if (!ins->vex.nd)
13543 return true;
13544 }
13545
13546 reg = ins->vex.register_specifier;
13547 ins->vex.register_specifier = 0;
13548 if (ins->address_mode != mode_64bit)
13549 {
13550 if (ins->vex.evex && !ins->vex.v)
13551 {
13552 oappend (ins, "(bad)");
13553 return true;
13554 }
13555
13556 reg &= 7;
13557 }
13558 else if (ins->vex.evex && !ins->vex.v)
13559 reg += 16;
13560
13561 switch (bytemode)
13562 {
13563 case scalar_mode:
13564 oappend_register (ins, att_names_xmm[reg]);
13565 return true;
13566
13567 case vex_vsib_d_w_dq_mode:
13568 case vex_vsib_q_w_dq_mode:
13569 /* This must be the 3rd operand. */
13570 if (ins->obufp != ins->op_out[2])
13571 abort ();
13572 if (ins->vex.length == 128
13573 || (bytemode != vex_vsib_d_w_dq_mode
13574 && !ins->vex.w))
13575 oappend_register (ins, att_names_xmm[reg]);
13576 else
13577 oappend_register (ins, att_names_ymm[reg]);
13578
13579 /* All 3 XMM/YMM registers must be distinct. */
13580 modrm_reg = ins->modrm.reg;
13581 if (ins->rex & REX_R)
13582 modrm_reg += 8;
13583
13584 if (ins->has_sib && ins->modrm.rm == 4)
13585 {
13586 sib_index = ins->sib.index;
13587 if (ins->rex & REX_X)
13588 sib_index += 8;
13589 }
13590
13591 if (reg == modrm_reg || reg == sib_index)
13592 strcpy (ins->obufp, "/(bad)");
13593 if (modrm_reg == sib_index || modrm_reg == reg)
13594 strcat (ins->op_out[0], "/(bad)");
13595 if (sib_index == modrm_reg || sib_index == reg)
13596 strcat (ins->op_out[1], "/(bad)");
13597
13598 return true;
13599
13600 case tmm_mode:
13601 /* All 3 TMM registers must be distinct. */
13602 if (reg >= 8)
13603 oappend (ins, "(bad)");
13604 else
13605 {
13606 /* This must be the 3rd operand. */
13607 if (ins->obufp != ins->op_out[2])
13608 abort ();
13609 oappend_register (ins, att_names_tmm[reg]);
13610 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13611 strcpy (ins->obufp, "/(bad)");
13612 }
13613
13614 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13615 || ins->modrm.rm == reg)
13616 {
13617 if (ins->modrm.reg <= 8
13618 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13619 strcat (ins->op_out[0], "/(bad)");
13620 if (ins->modrm.rm <= 8
13621 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13622 strcat (ins->op_out[1], "/(bad)");
13623 }
13624
13625 return true;
13626 }
13627
13628 switch (ins->vex.length)
13629 {
13630 case 128:
13631 switch (bytemode)
13632 {
13633 case x_mode:
13634 names = att_names_xmm;
13635 ins->evex_used |= EVEX_len_used;
13636 break;
13637 case v_mode:
13638 case dq_mode:
13639 if (ins->rex & REX_W)
13640 names = att_names64;
13641 else if (bytemode == v_mode
13642 && !(sizeflag & DFLAG))
13643 names = att_names16;
13644 else
13645 names = att_names32;
13646 break;
13647 case b_mode:
13648 names = att_names8rex;
13649 break;
13650 case q_mode:
13651 names = att_names64;
13652 break;
13653 case mask_bd_mode:
13654 case mask_mode:
13655 if (reg > 0x7)
13656 {
13657 oappend (ins, "(bad)");
13658 return true;
13659 }
13660 names = att_names_mask;
13661 break;
13662 default:
13663 abort ();
13664 return true;
13665 }
13666 break;
13667 case 256:
13668 switch (bytemode)
13669 {
13670 case x_mode:
13671 names = att_names_ymm;
13672 ins->evex_used |= EVEX_len_used;
13673 break;
13674 case mask_bd_mode:
13675 case mask_mode:
13676 if (reg <= 0x7)
13677 {
13678 names = att_names_mask;
13679 break;
13680 }
13681 /* Fall through. */
13682 default:
13683 /* See PR binutils/20893 for a reproducer. */
13684 oappend (ins, "(bad)");
13685 return true;
13686 }
13687 break;
13688 case 512:
13689 names = att_names_zmm;
13690 ins->evex_used |= EVEX_len_used;
13691 break;
13692 default:
13693 abort ();
13694 break;
13695 }
13696 oappend_register (ins, names[reg]);
13697 return true;
13698 }
13699
13700 static bool
OP_VexR(instr_info * ins,int bytemode,int sizeflag)13701 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13702 {
13703 if (ins->modrm.mod == 3)
13704 return OP_VEX (ins, bytemode, sizeflag);
13705 return true;
13706 }
13707
13708 static bool
OP_VexW(instr_info * ins,int bytemode,int sizeflag)13709 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13710 {
13711 OP_VEX (ins, bytemode, sizeflag);
13712
13713 if (ins->vex.w)
13714 {
13715 /* Swap 2nd and 3rd operands. */
13716 char *tmp = ins->op_out[2];
13717
13718 ins->op_out[2] = ins->op_out[1];
13719 ins->op_out[1] = tmp;
13720 }
13721 return true;
13722 }
13723
13724 static bool
OP_REG_VexI4(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13725 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13726 {
13727 int reg;
13728 const char (*names)[8] = att_names_xmm;
13729
13730 if (!fetch_code (ins->info, ins->codep + 1))
13731 return false;
13732 reg = *ins->codep++;
13733
13734 if (bytemode != x_mode && bytemode != scalar_mode)
13735 abort ();
13736
13737 reg >>= 4;
13738 if (ins->address_mode != mode_64bit)
13739 reg &= 7;
13740
13741 if (bytemode == x_mode && ins->vex.length == 256)
13742 names = att_names_ymm;
13743
13744 oappend_register (ins, names[reg]);
13745
13746 if (ins->vex.w)
13747 {
13748 /* Swap 3rd and 4th operands. */
13749 char *tmp = ins->op_out[3];
13750
13751 ins->op_out[3] = ins->op_out[2];
13752 ins->op_out[2] = tmp;
13753 }
13754 return true;
13755 }
13756
13757 static bool
OP_VexI4(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13758 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13759 int sizeflag ATTRIBUTE_UNUSED)
13760 {
13761 oappend_immediate (ins, ins->codep[-1] & 0xf);
13762 return true;
13763 }
13764
13765 static bool
VPCMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13766 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13767 int sizeflag ATTRIBUTE_UNUSED)
13768 {
13769 unsigned int cmp_type;
13770
13771 if (!ins->vex.evex)
13772 abort ();
13773
13774 if (!fetch_code (ins->info, ins->codep + 1))
13775 return false;
13776 cmp_type = *ins->codep++;
13777 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13778 If it's the case, print suffix, otherwise - print the immediate. */
13779 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13780 && cmp_type != 3
13781 && cmp_type != 7)
13782 {
13783 char suffix[3];
13784 char *p = ins->mnemonicendp - 2;
13785
13786 /* vpcmp* can have both one- and two-lettered suffix. */
13787 if (p[0] == 'p')
13788 {
13789 p++;
13790 suffix[0] = p[0];
13791 suffix[1] = '\0';
13792 }
13793 else
13794 {
13795 suffix[0] = p[0];
13796 suffix[1] = p[1];
13797 suffix[2] = '\0';
13798 }
13799
13800 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13801 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13802 }
13803 else
13804 {
13805 /* We have a reserved extension byte. Output it directly. */
13806 oappend_immediate (ins, cmp_type);
13807 }
13808 return true;
13809 }
13810
13811 static const struct op xop_cmp_op[] =
13812 {
13813 { STRING_COMMA_LEN ("lt") },
13814 { STRING_COMMA_LEN ("le") },
13815 { STRING_COMMA_LEN ("gt") },
13816 { STRING_COMMA_LEN ("ge") },
13817 { STRING_COMMA_LEN ("eq") },
13818 { STRING_COMMA_LEN ("neq") },
13819 { STRING_COMMA_LEN ("false") },
13820 { STRING_COMMA_LEN ("true") }
13821 };
13822
13823 static bool
VPCOM_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13824 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13825 int sizeflag ATTRIBUTE_UNUSED)
13826 {
13827 unsigned int cmp_type;
13828
13829 if (!fetch_code (ins->info, ins->codep + 1))
13830 return false;
13831 cmp_type = *ins->codep++;
13832 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13833 {
13834 char suffix[3];
13835 char *p = ins->mnemonicendp - 2;
13836
13837 /* vpcom* can have both one- and two-lettered suffix. */
13838 if (p[0] == 'm')
13839 {
13840 p++;
13841 suffix[0] = p[0];
13842 suffix[1] = '\0';
13843 }
13844 else
13845 {
13846 suffix[0] = p[0];
13847 suffix[1] = p[1];
13848 suffix[2] = '\0';
13849 }
13850
13851 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13852 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13853 }
13854 else
13855 {
13856 /* We have a reserved extension byte. Output it directly. */
13857 oappend_immediate (ins, cmp_type);
13858 }
13859 return true;
13860 }
13861
13862 static const struct op pclmul_op[] =
13863 {
13864 { STRING_COMMA_LEN ("lql") },
13865 { STRING_COMMA_LEN ("hql") },
13866 { STRING_COMMA_LEN ("lqh") },
13867 { STRING_COMMA_LEN ("hqh") }
13868 };
13869
13870 static bool
PCLMUL_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13871 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13872 int sizeflag ATTRIBUTE_UNUSED)
13873 {
13874 unsigned int pclmul_type;
13875
13876 if (!fetch_code (ins->info, ins->codep + 1))
13877 return false;
13878 pclmul_type = *ins->codep++;
13879 switch (pclmul_type)
13880 {
13881 case 0x10:
13882 pclmul_type = 2;
13883 break;
13884 case 0x11:
13885 pclmul_type = 3;
13886 break;
13887 default:
13888 break;
13889 }
13890 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13891 {
13892 char suffix[4];
13893 char *p = ins->mnemonicendp - 3;
13894 suffix[0] = p[0];
13895 suffix[1] = p[1];
13896 suffix[2] = p[2];
13897 suffix[3] = '\0';
13898 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13899 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13900 }
13901 else
13902 {
13903 /* We have a reserved extension byte. Output it directly. */
13904 oappend_immediate (ins, pclmul_type);
13905 }
13906 return true;
13907 }
13908
13909 static bool
MOVSXD_Fixup(instr_info * ins,int bytemode,int sizeflag)13910 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13911 {
13912 /* Add proper suffix to "movsxd". */
13913 char *p = ins->mnemonicendp;
13914
13915 switch (bytemode)
13916 {
13917 case movsxd_mode:
13918 if (!ins->intel_syntax)
13919 {
13920 USED_REX (REX_W);
13921 if (ins->rex & REX_W)
13922 {
13923 *p++ = 'l';
13924 *p++ = 'q';
13925 break;
13926 }
13927 }
13928
13929 *p++ = 'x';
13930 *p++ = 'd';
13931 break;
13932 default:
13933 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13934 break;
13935 }
13936
13937 ins->mnemonicendp = p;
13938 *p = '\0';
13939 return OP_E (ins, bytemode, sizeflag);
13940 }
13941
13942 static bool
DistinctDest_Fixup(instr_info * ins,int bytemode,int sizeflag)13943 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13944 {
13945 unsigned int reg = ins->vex.register_specifier;
13946 unsigned int modrm_reg = ins->modrm.reg;
13947 unsigned int modrm_rm = ins->modrm.rm;
13948
13949 /* Calc destination register number. */
13950 if (ins->rex & REX_R)
13951 modrm_reg += 8;
13952 if (ins->rex2 & REX_R)
13953 modrm_reg += 16;
13954
13955 /* Calc src1 register number. */
13956 if (ins->address_mode != mode_64bit)
13957 reg &= 7;
13958 else if (ins->vex.evex && !ins->vex.v)
13959 reg += 16;
13960
13961 /* Calc src2 register number. */
13962 if (ins->modrm.mod == 3)
13963 {
13964 if (ins->rex & REX_B)
13965 modrm_rm += 8;
13966 if (ins->rex & REX_X)
13967 modrm_rm += 16;
13968 }
13969
13970 /* Destination and source registers must be distinct, output bad if
13971 dest == src1 or dest == src2. */
13972 if (modrm_reg == reg
13973 || (ins->modrm.mod == 3
13974 && modrm_reg == modrm_rm))
13975 {
13976 oappend (ins, "(bad)");
13977 return true;
13978 }
13979 return OP_XMM (ins, bytemode, sizeflag);
13980 }
13981
13982 static bool
OP_Rounding(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13983 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13984 {
13985 if (ins->modrm.mod != 3 || !ins->vex.b)
13986 return true;
13987
13988 switch (bytemode)
13989 {
13990 case evex_rounding_64_mode:
13991 if (ins->address_mode != mode_64bit || !ins->vex.w)
13992 return true;
13993 /* Fall through. */
13994 case evex_rounding_mode:
13995 ins->evex_used |= EVEX_b_used;
13996 oappend (ins, names_rounding[ins->vex.ll]);
13997 break;
13998 case evex_sae_mode:
13999 ins->evex_used |= EVEX_b_used;
14000 oappend (ins, "{");
14001 break;
14002 default:
14003 abort ();
14004 }
14005 oappend (ins, "sae}");
14006 return true;
14007 }
14008
14009 static bool
PREFETCHI_Fixup(instr_info * ins,int bytemode,int sizeflag)14010 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
14011 {
14012 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
14013 {
14014 if (ins->intel_syntax)
14015 {
14016 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
14017 }
14018 else
14019 {
14020 USED_REX (REX_W);
14021 if (ins->rex & REX_W)
14022 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
14023 else
14024 {
14025 if (sizeflag & DFLAG)
14026 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
14027 else
14028 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
14029 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
14030 }
14031 }
14032 bytemode = v_mode;
14033 }
14034
14035 return OP_M (ins, bytemode, sizeflag);
14036 }
14037
14038 static bool
PUSH2_POP2_Fixup(instr_info * ins,int bytemode,int sizeflag)14039 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
14040 {
14041 if (ins->modrm.mod != 3)
14042 return true;
14043
14044 unsigned int vvvv_reg = ins->vex.register_specifier
14045 | (!ins->vex.v << 4);
14046 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
14047 + (ins->rex2 & REX_B ? 16 : 0);
14048
14049 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
14050 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
14051 || (!ins->modrm.reg
14052 && vvvv_reg == rm_reg))
14053 {
14054 oappend (ins, "(bad)");
14055 return true;
14056 }
14057
14058 return OP_VEX (ins, bytemode, sizeflag);
14059 }
14060
14061 static bool
JMPABS_Fixup(instr_info * ins,int bytemode,int sizeflag)14062 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
14063 {
14064 if (ins->last_rex2_prefix >= 0)
14065 {
14066 uint64_t op;
14067
14068 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
14069 || (ins->rex & REX_W) != 0x0)
14070 {
14071 oappend (ins, "(bad)");
14072 return true;
14073 }
14074
14075 if (bytemode == eAX_reg)
14076 return true;
14077
14078 if (!get64 (ins, &op))
14079 return false;
14080
14081 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14082 ins->rex2 |= REX2_SPECIAL;
14083 oappend_immediate (ins, op);
14084
14085 return true;
14086 }
14087
14088 if (bytemode == eAX_reg)
14089 return OP_IMREG (ins, bytemode, sizeflag);
14090 return OP_OFF64 (ins, bytemode, sizeflag);
14091 }
14092