1 /* Simulation code for the CR16 processor.
2 Copyright (C) 2008-2024 Free Software Foundation, Inc.
3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com>
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20
21 #include <stdio.h>
22 #include <ctype.h>
23 #include <limits.h>
24 #include "ansidecl.h"
25 #include "sim/callback.h"
26 #include "opcode/cr16.h"
27 #include "bfd.h"
28 #include "sim-main.h"
29
30 #define DEBUG_TRACE 0x00000001
31 #define DEBUG_VALUES 0x00000002
32 #define DEBUG_LINE_NUMBER 0x00000004
33 #define DEBUG_MEMSIZE 0x00000008
34 #define DEBUG_INSTRUCTION 0x00000010
35 #define DEBUG_TRAP 0x00000020
36 #define DEBUG_MEMORY 0x00000040
37
38 #ifndef DEBUG
39 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
40 #endif
41
42 extern int cr16_debug;
43
44 #include "sim/sim.h"
45 #include "sim-config.h"
46 #include "sim-types.h"
47
48 /* FIXME: CR16 defines */
49 typedef uint16_t reg_t;
50 typedef uint32_t creg_t;
51
52 struct simops
53 {
54 char mnemonic[12];
55 uint32_t size;
56 uint32_t mask;
57 uint32_t opcode;
58 int format;
59 char fname[12];
60 void (*func)(SIM_DESC, SIM_CPU *);
61 int numops;
62 operand_desc operands[4];
63 };
64
65 enum _ins_type
66 {
67 INS_UNKNOWN, /* unknown instruction */
68 INS_NO_TYPE_INS,
69 INS_ARITH_INS,
70 INS_LD_STOR_INS,
71 INS_BRANCH_INS,
72 INS_ARITH_BYTE_INS,
73 INS_SHIFT_INS,
74 INS_BRANCH_NEQ_INS,
75 INS_STOR_IMM_INS,
76 INS_CSTBIT_INS,
77 INS_MAX
78 };
79
80 extern unsigned long ins_type_counters[ (int)INS_MAX ];
81
82 enum {
83 SP_IDX = 15,
84 };
85
86 /* Write-back slots */
87 union slot_data {
88 unsigned_1 _1;
89 unsigned_2 _2;
90 unsigned_4 _4;
91 };
92 struct slot {
93 void *dest;
94 int size;
95 union slot_data data;
96 union slot_data mask;
97 };
98 enum {
99 NR_SLOTS = 16
100 };
101 #define SLOT (State.slot)
102 #define SLOT_NR (State.slot_nr)
103 #define SLOT_PEND_MASK(DEST, MSK, VAL) \
104 do \
105 { \
106 SLOT[SLOT_NR].dest = &(DEST); \
107 SLOT[SLOT_NR].size = sizeof (DEST); \
108 switch (sizeof (DEST)) \
109 { \
110 case 1: \
111 SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
112 SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
113 break; \
114 case 2: \
115 SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
116 SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
117 break; \
118 case 4: \
119 SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
120 SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
121 break; \
122 } \
123 SLOT_NR = (SLOT_NR + 1); \
124 } \
125 while (0)
126 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
127 #define SLOT_DISCARD() (SLOT_NR = 0)
128 #define SLOT_FLUSH() \
129 do \
130 { \
131 int i; \
132 for (i = 0; i < SLOT_NR; i++) \
133 { \
134 switch (SLOT[i].size) \
135 { \
136 case 1: \
137 *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
138 *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
139 break; \
140 case 2: \
141 *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
142 *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
143 break; \
144 case 4: \
145 *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
146 *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
147 break; \
148 } \
149 } \
150 SLOT_NR = 0; \
151 } \
152 while (0)
153 #define SLOT_DUMP() \
154 do \
155 { \
156 int i; \
157 for (i = 0; i < SLOT_NR; i++) \
158 { \
159 switch (SLOT[i].size) \
160 { \
161 case 1: \
162 printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
163 (long) SLOT[i].dest, \
164 (unsigned) SLOT[i].mask._1, \
165 (unsigned) SLOT[i].data._1); \
166 break; \
167 case 2: \
168 printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
169 (long) SLOT[i].dest, \
170 (unsigned) SLOT[i].mask._2, \
171 (unsigned) SLOT[i].data._2); \
172 break; \
173 case 4: \
174 printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
175 (long) SLOT[i].dest, \
176 (unsigned) SLOT[i].mask._4, \
177 (unsigned) SLOT[i].data._4); \
178 break; \
179 case 8: \
180 printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
181 (long) SLOT[i].dest, \
182 (unsigned) (SLOT[i].mask._8 >> 32), \
183 (unsigned) SLOT[i].mask._8, \
184 (unsigned) (SLOT[i].data._8 >> 32), \
185 (unsigned) SLOT[i].data._8); \
186 break; \
187 } \
188 } \
189 } \
190 while (0)
191
192 struct _state
193 {
194 creg_t regs[16]; /* general-purpose registers */
195 #define GPR(N) (State.regs[(N)] + 0)
196 #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL))
197
198 #define GPR32(N) \
199 (N < 12) ? \
200 ((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \
201 : GPR (N)
202
203 #define SET_GPR32(N,VAL) do { \
204 if (N < 11) \
205 { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \
206 else { if ( N == 11) \
207 { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \
208 SET_GPR (N, ((VAL) & 0xffff));} \
209 else SET_GPR (N, (VAL));} \
210 } while (0)
211
212 creg_t cregs[16]; /* control registers */
213 #define CREG(N) (State.cregs[(N)] + 0)
214 #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
215 #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
216
217 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
218 #define HELD_SP(N) (State.sp[(N)] + 0)
219 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
220
221 /* writeback info */
222 struct slot slot[NR_SLOTS];
223 int slot_nr;
224
225 /* trace data */
226 struct {
227 uint16_t psw;
228 } trace;
229
230 int pc_changed;
231
232 /* NOTE: everything below this line is not reset by
233 sim_create_inferior() */
234
235 enum _ins_type ins_type;
236
237 };
238
239 extern struct _state State;
240
241
242 extern uint32_t OP[4];
243 extern uint32_t sign_flag;
244 extern struct simops Simops[];
245
246 enum
247 {
248 PC_CR = 0,
249 BDS_CR = 1,
250 BSR_CR = 2,
251 DCR_CR = 3,
252 CAR0_CR = 5,
253 CAR1_CR = 7,
254 CFG_CR = 9,
255 PSR_CR = 10,
256 INTBASE_CR = 11,
257 ISP_CR = 13,
258 USP_CR = 15
259 };
260
261 enum
262 {
263 PSR_I_BIT = 0x0800,
264 PSR_P_BIT = 0x0400,
265 PSR_E_BIT = 0x0200,
266 PSR_N_BIT = 0x0080,
267 PSR_Z_BIT = 0x0040,
268 PSR_F_BIT = 0x0020,
269 PSR_U_BIT = 0x0008,
270 PSR_L_BIT = 0x0004,
271 PSR_T_BIT = 0x0002,
272 PSR_C_BIT = 0x0001
273 };
274
275 #define PSR CREG (PSR_CR)
276 #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL))
277 #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL))
278 #define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1)
279
280 #define PSR_SM ((PSR & PSR_SM_BIT) != 0)
281 #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL))
282
283 #define PSR_I ((PSR & PSR_I_BIT) != 0)
284 #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL))
285
286 #define PSR_DB ((PSR & PSR_DB_BIT) != 0)
287 #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL))
288
289 #define PSR_P ((PSR & PSR_P_BIT) != 0)
290 #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL))
291
292 #define PSR_E ((PSR & PSR_E_BIT) != 0)
293 #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL))
294
295 #define PSR_N ((PSR & PSR_N_BIT) != 0)
296 #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL))
297
298 #define PSR_Z ((PSR & PSR_Z_BIT) != 0)
299 #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL))
300
301 #define PSR_F ((PSR & PSR_F_BIT) != 0)
302 #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL))
303
304 #define PSR_U ((PSR & PSR_U_BIT) != 0)
305 #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL))
306
307 #define PSR_L ((PSR & PSR_L_BIT) != 0)
308 #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL))
309
310 #define PSR_T ((PSR & PSR_T_BIT) != 0)
311 #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL))
312
313 #define PSR_C ((PSR & PSR_C_BIT) != 0)
314 #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL))
315
316 /* See simopsc.:move_to_cr() for registers that can not be read-from
317 or assigned-to directly */
318
319 #define PC CREG (PC_CR)
320 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
321 //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL))
322
323 #define BPSR CREG (BPSR_CR)
324 #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL))
325
326 #define BPC CREG (BPC_CR)
327 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
328
329 #define DPSR CREG (DPSR_CR)
330 #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL))
331
332 #define DPC CREG (DPC_CR)
333 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
334
335 #define RPT_C CREG (RPT_C_CR)
336 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
337
338 #define RPT_S CREG (RPT_S_CR)
339 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
340
341 #define RPT_E CREG (RPT_E_CR)
342 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
343
344 #define MOD_S CREG (MOD_S_CR)
345 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
346
347 #define MOD_E CREG (MOD_E_CR)
348 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
349
350 #define IBA CREG (IBA_CR)
351 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
352
353
354 #define SIG_CR16_STOP -1
355 #define SIG_CR16_EXIT -2
356 #define SIG_CR16_BUS -3
357 #define SIG_CR16_IAD -4
358
359 /* TODO: Resolve conflicts with common headers. */
360 #undef SEXT8
361 #undef SEXT16
362 #undef SEXT32
363
364 #define SEXT3(x) ((((x)&0x7)^(~3))+4)
365
366 /* sign-extend a 4-bit number */
367 #define SEXT4(x) ((((x)&0xf)^(~7))+8)
368
369 /* sign-extend an 8-bit number */
370 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
371
372 /* sign-extend a 16-bit number */
373 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
374
375 /* sign-extend a 24-bit number */
376 #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000)
377
378 /* sign-extend a 32-bit number */
379 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000)
380
381 #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data)
382 #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr)
383 #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data)
384 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr)
385 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data)
386
387 /* Yes, this is as whacked as it looks. The sim currently reads little endian
388 for 16 bits, but then merge them like big endian to get 32 bits. */
get_longword(SIM_CPU * cpu,address_word addr)389 static inline uint32_t get_longword (SIM_CPU *cpu, address_word addr)
390 {
391 return (RW (addr) << 16) | RW (addr + 2);
392 }
393 #define RLW(addr) get_longword (cpu, addr)
394
395 #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
396
397 #define RIE_VECTOR_START 0xffc2
398 #define AE_VECTOR_START 0xffc3
399 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
400 #define DBT_VECTOR_START 0xffd4
401 #define SDBT_VECTOR_START 0xffd5
402
403 #define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */
404 #define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/
405 #define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */
406 #define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */
407 #define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */
408 #define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */
409
410
411 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
412 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
413 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for
414 PSR is masked for zero bits. */
415
416 extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p);
417
418 #ifndef SIGTRAP
419 #define SIGTRAP 5
420 #endif
421 /* Special purpose trap */
422 #define TRAP_BREAKPOINT 8
423