1 /* $NetBSD: tc_machdep.h,v 1.9 2025/03/09 01:06:42 thorpej Exp $ */
2 
3 /*
4  * Copyright (c) 1994, 1995 Carnegie-Mellon University.
5  * All rights reserved.
6  *
7  * Author: Chris G. Demetriou
8  *
9  * Permission to use, copy, modify and distribute this software and
10  * its documentation is hereby granted, provided that both the copyright
11  * notice and this permission notice appear in all copies of the
12  * software, derivative works or modified versions, and any portions
13  * thereof, and that both notices appear in supporting documentation.
14  *
15  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18  *
19  * Carnegie Mellon requests users of this software to return to
20  *
21  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
22  *  School of Computer Science
23  *  Carnegie Mellon University
24  *  Pittsburgh PA 15213-3890
25  *
26  * any improvements or extensions that they make and grant Carnegie the
27  * rights to redistribute these changes.
28  */
29 
30 /*
31  * Machine-specific definitions for TURBOchannel support.
32  *
33  * This file must typedef the following types:
34  *
35  *        tc_addr_t TURBOchannel bus address
36  *        tc_offset_t         TURBOchannel bus address difference (offset)
37  *
38  * This file must prototype or define the following functions
39  * or macros (one or more of which may be no-ops):
40  *
41  *        tc_mb()             read/write memory barrier (any CPU<->memory
42  *                            reads/writes before must complete before any
43  *                            CPU<->memory reads/writes after).
44  *        tc_wmb()  write memory barrier (any CPU<->memory writes
45  *                            before must complete before any CPU<->memory
46  *                            writes after).
47  *        tc_syncbus()        sync TC bus; make sure CPU writes are
48  *                            propagated across the TURBOchannel bus.
49  *        tc_badaddr()        return non-zero if the given address is invalid.
50  *        TC_DENSE_TO_SPARSE()
51  *                            convert the given physical address in
52  *                            TURBOchannel dense space to the corresponding
53  *                            address in TURBOchannel sparse space.
54  *        TC_PHYS_TO_UNCACHED()
55  *                            convert the given system memory physical address
56  *                            to the physical address of the corresponding
57  *                            region that is not cached.
58  */
59 
60 typedef uint64_t    tc_addr_t;
61 typedef int32_t               tc_offset_t;
62 
63 #define   tc_mb()             alpha_mb()
64 #define   tc_wmb()  alpha_wmb()
65 
66 /*
67  * A junk address to read from, to make sure writes are complete.  See
68  * System Programmer's Manual, section 9.3 (p. 9-4), and sacrifice a
69  * chicken.
70  */
71 #define   tc_syncbus()                                                                    \
72     do {                                                                        \
73           volatile uint32_t no_optimize;                                                  \
74           /*                                                                              \
75            * WMB does not order reads with respect to writes, so a    \
76            * MB is required here.                                                         \
77            */                                                                             \
78           alpha_mb();                                                                     \
79           no_optimize =                                                                   \
80               *(volatile uint32_t *)ALPHA_PHYS_TO_K0SEG(0x00000001f0080220); \
81           __USE(no_optimize);                                                   \
82     } while (/*CONSTCOND*/0)
83 
84 #define   tc_badaddr(tcaddr)                                                    \
85     badaddr((void *)(tcaddr), sizeof (uint32_t))
86 
87 #define   TC_SPACE_IND                  0xffffffffe0000003
88 #define   TC_SPACE_DENSE                0x0000000000000000
89 #define TC_SPACE_DENSE_OFFSET 0x0000000007fffffc
90 #define   TC_SPACE_SPARSE               0x0000000010000000
91 #define   TC_SPACE_SPARSE_OFFSET        0x000000000ffffff8
92 
93 #define   TC_DENSE_TO_SPARSE(addr)                                              \
94     (((addr) & TC_SPACE_IND) | TC_SPACE_SPARSE |                      \
95           (((addr) & TC_SPACE_DENSE_OFFSET) << 1))
96 
97 #define   TC_PHYS_TO_UNCACHED(addr)                                             \
98     (addr)
99 
100 /*
101  * These functions are private, and may not be called by
102  * machine-independent code.
103  */
104 void                tc_find_bootdev(device_t, void *);
105 bus_space_tag_t     tc_bus_mem_init(void *memv);
106 void                tc_dma_init(void);
107 
108 /*
109  * Address of scatter/gather SRAM on the 3000/500-series.
110  *
111  * There is room for 32K entries, yielding 256M of sgva space.
112  * The page table is readable in both dense and sparse space.
113  * The page table is writable only in sparse space.
114  *
115  * In sparse space, the 32-bit PTEs are followed by 32-bits
116  * of pad.
117  */
118 #define   TC_SGSRAM_DENSE               0x0000001c2800000UL
119 #define   TC_SGSRAM_SPARSE    0x0000001d5000000UL
120