1 /* $Id: imx_space.c,v 1.7 2023/04/21 15:00:48 skrll Exp $ */
2
3 /* derived from: */
4 /* $NetBSD: imx_space.c,v 1.7 2023/04/21 15:00:48 skrll Exp $ */
5
6 /*
7 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
8 * All rights reserved.
9 *
10 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed for the NetBSD Project by
23 * Wasabi Systems, Inc.
24 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
25 * or promote products derived from this software without specific prior
26 * written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40 /*
41 * Copyright (c) 1997 Mark Brinicombe.
42 * Copyright (c) 1997 Causality Limited.
43 * All rights reserved.
44 *
45 * This code is derived from software contributed to The NetBSD Foundation
46 * by Ichiro FUKUHARA.
47 *
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that the following conditions
50 * are met:
51 * 1. Redistributions of source code must retain the above copyright
52 * notice, this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright
54 * notice, this list of conditions and the following disclaimer in the
55 * documentation and/or other materials provided with the distribution.
56 * 3. All advertising materials mentioning features or use of this software
57 * must display the following acknowledgement:
58 * This product includes software developed by Mark Brinicombe.
59 * 4. The name of the company nor the name of the author may be used to
60 * endorse or promote products derived from this software without specific
61 * prior written permission.
62 *
63 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
64 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
65 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
66 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
67 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
68 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
69 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
73 * SUCH DAMAGE.
74 */
75
76 /*
77 * bus_space(9) support for Freescale iMX31 processor
78 */
79
80 #include <sys/param.h>
81 #include <sys/systm.h>
82 #include <uvm/uvm_extern.h>
83 #include <sys/bus.h>
84
85 bs_protos(imx);
86 bs_protos(generic);
87 bs_protos(generic_armv4);
88 bs_protos(bs_notimpl);
89
90 struct bus_space imx_bs_tag = {
91 /* cookie */
92 .bs_cookie = (void *) 0,
93
94 /* mapping/unmapping */
95 .bs_map = imx_bs_map,
96 .bs_unmap = imx_bs_unmap,
97 .bs_subregion = imx_bs_subregion,
98
99 /* allocation/deallocation */
100 .bs_alloc = imx_bs_alloc, /* not implemented */
101 .bs_free = imx_bs_free, /* not implemented */
102
103 /* get kernel virtual address */
104 .bs_vaddr = imx_bs_vaddr,
105
106 /* mmap */
107 .bs_mmap = bs_notimpl_bs_mmap,
108
109 /* barrier */
110 .bs_barrier = imx_bs_barrier,
111
112 /* read (single) */
113 .bs_r_1 = generic_bs_r_1,
114 .bs_r_2 = generic_armv4_bs_r_2,
115 .bs_r_4 = generic_bs_r_4,
116 .bs_r_8 = bs_notimpl_bs_r_8,
117
118 /* read multiple */
119 .bs_rm_1 = generic_bs_rm_1,
120 .bs_rm_2 = generic_armv4_bs_rm_2,
121 .bs_rm_4 = generic_bs_rm_4,
122 .bs_rm_8 = bs_notimpl_bs_rm_8,
123
124 /* read region */
125 .bs_rr_1 = generic_bs_rr_1,
126 .bs_rr_2 = generic_armv4_bs_rr_2,
127 .bs_rr_4 = generic_bs_rr_4,
128 .bs_rr_8 = bs_notimpl_bs_rr_8,
129
130 /* write (single) */
131 .bs_w_1 = generic_bs_w_1,
132 .bs_w_2 = generic_armv4_bs_w_2,
133 .bs_w_4 = generic_bs_w_4,
134 .bs_w_8 = bs_notimpl_bs_w_8,
135
136 /* write multiple */
137 .bs_wm_1 = generic_bs_wm_1,
138 .bs_wm_2 = generic_armv4_bs_wm_2,
139 .bs_wm_4 = generic_bs_wm_4,
140 .bs_wm_8 = bs_notimpl_bs_wm_8,
141
142 /* write region */
143 .bs_wr_1 = generic_bs_wr_1,
144 .bs_wr_2 = generic_armv4_bs_wr_2,
145 .bs_wr_4 = generic_bs_wr_4,
146 .bs_wr_8 = bs_notimpl_bs_wr_8,
147
148 /* set multiple */
149 .bs_sm_1 = bs_notimpl_bs_sm_1,
150 .bs_sm_2 = bs_notimpl_bs_sm_2,
151 .bs_sm_4 = bs_notimpl_bs_sm_4,
152 .bs_sm_8 = bs_notimpl_bs_sm_8,
153
154 /* set region */
155 .bs_sr_1 = generic_bs_sr_1,
156 .bs_sr_2 = generic_armv4_bs_sr_2,
157 .bs_sr_4 = bs_notimpl_bs_sr_4,
158 .bs_sr_8 = bs_notimpl_bs_sr_8,
159
160 /* copy */
161 .bs_c_1 = bs_notimpl_bs_c_1,
162 .bs_c_2 = generic_armv4_bs_c_2,
163 .bs_c_4 = bs_notimpl_bs_c_4,
164 .bs_c_8 = bs_notimpl_bs_c_8,
165
166 #ifdef __BUS_SPACE_HAS_STREAM_METHODS
167 /* read (single) */
168 .bs_r_1_s = generic_bs_r_1,
169 .bs_r_2_s = generic_armv4_bs_r_2,
170 .bs_r_4_s = generic_bs_r_4,
171 .bs_r_8_s = bs_notimpl_bs_r_8,
172
173 /* read multiple */
174 .bs_rm_1_s = generic_bs_rm_1,
175 .bs_rm_2_s = generic_armv4_bs_rm_2,
176 .bs_rm_4_s = generic_bs_rm_4,
177 .bs_rm_8_s = bs_notimpl_bs_rm_8,
178
179 /* read region */
180 .bs_rr_1_s = generic_bs_rr_1,
181 .bs_rr_2_s = generic_armv4_bs_rr_2,
182 .bs_rr_4_s = generic_bs_rr_4,
183 .bs_rr_8_s = bs_notimpl_bs_rr_8,
184
185 /* write (single) */
186 .bs_w_1_s = generic_bs_w_1,
187 .bs_w_2_s = generic_armv4_bs_w_2,
188 .bs_w_4_s = generic_bs_w_4,
189 .bs_w_8_s = bs_notimpl_bs_w_8,
190
191 /* write multiple */
192 .bs_wm_1_s = generic_bs_wm_1,
193 .bs_wm_2_s = generic_armv4_bs_wm_2,
194 .bs_wm_4_s = generic_bs_wm_4,
195 .bs_wm_8_s = bs_notimpl_bs_wm_8,
196
197 /* write region */
198 .bs_wr_1_s = generic_bs_wr_1,
199 .bs_wr_2_s = generic_armv4_bs_wr_2,
200 .bs_wr_4_s = generic_bs_wr_4,
201 .bs_wr_8_s = bs_notimpl_bs_wr_8,
202 #endif
203 };
204
205 int
imx_bs_map(void * t,bus_addr_t bpa,bus_size_t size,int flag,bus_space_handle_t * bshp)206 imx_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
207 int flag, bus_space_handle_t *bshp)
208 {
209 const struct pmap_devmap *pd;
210 paddr_t startpa, endpa, pa;
211 vaddr_t va;
212
213 if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
214 /* Device was statically mapped. */
215 *bshp = pd->pd_va + (bpa - pd->pd_pa);
216 return 0;
217 }
218
219 startpa = trunc_page(bpa);
220 endpa = round_page(bpa + size);
221
222 /* XXX use extent manager to check duplicate mapping */
223
224 va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
225 UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
226 if (! va)
227 return(ENOMEM);
228
229 *bshp = (bus_space_handle_t)(va + (bpa - startpa));
230
231 for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
232 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE,
233 (flag & BUS_SPACE_MAP_CACHEABLE) ? 0 : PMAP_NOCACHE);
234 }
235 pmap_update(pmap_kernel());
236
237 return(0);
238 }
239
240 void
imx_bs_unmap(void * t,bus_space_handle_t bsh,bus_size_t size)241 imx_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
242 {
243 vaddr_t va;
244 vsize_t sz;
245
246 if (pmap_devmap_find_va(bsh, size) != NULL) {
247 /* Device was statically mapped; nothing to do. */
248 return;
249 }
250
251 va = trunc_page(bsh);
252 sz = round_page(bsh + size) - va;
253
254 pmap_kremove(va, sz);
255 pmap_update(pmap_kernel());
256 uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
257 }
258
259
260 int
imx_bs_subregion(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t size,bus_space_handle_t * nbshp)261 imx_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
262 bus_size_t size, bus_space_handle_t *nbshp)
263 {
264
265 *nbshp = bsh + offset;
266 return (0);
267 }
268
269 void
imx_bs_barrier(void * t,bus_space_handle_t bsh,bus_size_t offset,bus_size_t len,int flags)270 imx_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
271 bus_size_t len, int flags)
272 {
273
274 /* Nothing to do. */
275 }
276
277 void *
imx_bs_vaddr(void * t,bus_space_handle_t bsh)278 imx_bs_vaddr(void *t, bus_space_handle_t bsh)
279 {
280
281 return ((void *)bsh);
282 }
283
284
285 int
imx_bs_alloc(void * t,bus_addr_t rstart,bus_addr_t rend,bus_size_t size,bus_size_t alignment,bus_size_t boundary,int flags,bus_addr_t * bpap,bus_space_handle_t * bshp)286 imx_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
287 bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
288 bus_addr_t *bpap, bus_space_handle_t *bshp)
289 {
290
291 panic("imx_io_bs_alloc(): not implemented\n");
292 }
293
294 void
imx_bs_free(void * t,bus_space_handle_t bsh,bus_size_t size)295 imx_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
296 {
297
298 panic("imx_io_bs_free(): not implemented\n");
299 }
300
301
302