1 /* $NetBSD: mv78xx0reg.h,v 1.3 2022/10/31 20:30:22 andvar Exp $ */ 2 /* 3 * Copyright (c) 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _MV78XX0REG_H_ 29 #define _MV78XX0REG_H_ 30 31 #include <arm/marvell/mvsocreg.h> 32 33 /* 34 * MHz PCIe GbE SATA TDMI COM 35 * MV76100: 800, 2 x2, x1, -, x3 36 * MV78100: 1.2, 2 x4, x2, x2, x2, x4 37 * MV78200: 1.0 x2, 2 x4, x4, x2, x2, x4 38 */ 39 40 #define MV78XX0_UNITID_DDR MVSOC_UNITID_DDR 41 #define MV78XX0_UNITID_DEVBUS MVSOC_UNITID_DEVBUS 42 #define MV78XX0_UNITID_LMB MVSOC_UNITID_MLMB 43 #define MV78XX0_UNITID_GBE23 0x3 /* Gigabit Ethernet registers */ 44 #define MV78XX0_UNITID_PEX MVSOC_UNITID_PEX 45 #define MV78XX0_UNITID_USB 0x5 /* USB registers */ 46 #define MV78XX0_UNITID_IDMA 0x6 /* IDMA registers */ 47 #define MV78XX0_UNITID_XOR 0x6 /* XOR registers */ 48 #define MV78XX0_UNITID_GBE01 0x7 /* Gigabit Ethernet registers */ 49 #define MV78XX0_UNITID_PEX1 0x8 50 #define MV78XX0_UNITID_CRYPT 0x9 /* Cryptographic Engine reg */ 51 #define MV78XX0_UNITID_SA 0x9 /* Security Accelerator reg */ 52 #define MV78XX0_UNITID_SATA 0xa /* SATA registers */ 53 #define MV78XX0_UNITID_TDM 0xb /* TDM registers */ 54 55 #define MV78XX0_ATTR_DEVICE_CS0 0x3e 56 #define MV78XX0_ATTR_DEVICE_CS1 0x3d 57 #define MV78XX0_ATTR_DEVICE_CS2 0x3b 58 #define MV78XX0_ATTR_DEVICE_CS3 0x37 59 #define MV78XX0_ATTR_BOOT_CS 0x2f 60 #define MV78XX0_ATTR_SPI 0x1f 61 #define MV78XX0_ATTR_PEX_0_IO 0xe0 /* PCIe x1 Port 0.0 */ 62 #define MV78XX0_ATTR_PEX_0_MEM 0xe8 63 #define MV78XX0_ATTR_PEX_1_IO 0xd0 /* PCIe x1 Port 0.1 */ 64 #define MV78XX0_ATTR_PEX_1_MEM 0xd8 65 #define MV78XX0_ATTR_PEX_2_IO 0xb0 /* PCIe x1 Port 0.2 */ 66 #define MV78XX0_ATTR_PEX_2_MEM 0xb8 67 #define MV78XX0_ATTR_PEX_3_IO 0x70 /* PCIe x1 Port 0.3 */ 68 #define MV78XX0_ATTR_PEX_3_MEM 0x78 69 #define MV78XX0_ATTR_CRYPT 0x00/* 0:Bswap,1:No,2:B&Wswap,3:Wswap */ 70 71 #define MV78XX0_IRQ_ERRSUM 0 /* Sum of Main Intr Err Cause */ 72 #define MV78XX0_IRQ_SPI 1 /* SPI */ 73 #define MV78XX0_IRQ_TWSI0 2 /* TWSI0 */ 74 #define MV78XX0_IRQ_TWSI1 3 /* TWSI1 */ 75 #define MV78XX0_IRQ_IDMA0 4 /* IDMA Channel0 completion */ 76 #define MV78XX0_IRQ_IDMA1 5 /* IDMA Channel1 completion */ 77 #define MV78XX0_IRQ_IDMA2 6 /* IDMA Channel2 completion */ 78 #define MV78XX0_IRQ_IDMA3 7 /* IDMA Channel3 completion */ 79 #define MV78XX0_IRQ_TIMER0 8 /* Timer0 */ 80 #define MV78XX0_IRQ_TIMER1 9 /* Timer1 */ 81 #define MV78XX0_IRQ_TIMER2 10 /* Timer2 */ 82 #define MV78XX0_IRQ_TIMER3 11 /* Timer3 */ 83 #define MV78XX0_IRQ_UART0 12 /* UART0 */ 84 #define MV78XX0_IRQ_UART1 13 /* UART1 */ 85 #define MV78XX0_IRQ_UART2 14 /* UART2 */ 86 #define MV78XX0_IRQ_UART3 15 /* UART3 */ 87 #define MV78XX0_IRQ_USB0 16 /* USB0 */ 88 #define MV78XX0_IRQ_USB1 17 /* USB1 */ 89 #define MV78XX0_IRQ_USB2 18 /* USB2 */ 90 #define MV78XX0_IRQ_CRYPTO 19 /* Crypto engine completion */ 91 #define MV78XX0_IRQ_XOR0 22 /* XOR engine 0 completion */ 92 #define MV78XX0_IRQ_XOR1 23 /* XOR engine 1 completion */ 93 #define MV78XX0_IRQ_SATA 26 /* SATA ports */ 94 #define MV78XX0_IRQ_TDMI_INT 27 /* TDM */ 95 #define MV78XX0_IRQ_PEX00INTA 32 /* PCIe Port0.0 INTA/B/C/D */ 96 #define MV78XX0_IRQ_PEX01INTA 33 /* PCIe Port0.1 INTA/B/C/D */ 97 #define MV78XX0_IRQ_PEX02INTA 34 /* PCIe Port0.2 INTA/B/C/D */ 98 #define MV78XX0_IRQ_PEX03INTA 35 /* PCIe Port0.3 INTA/B/C/D */ 99 #define MV78XX0_IRQ_PEX10INTA 36 /* PCIe Port1.0 INTA/B/C/D */ 100 #define MV78XX0_IRQ_PEX11INTA 37 /* PCIe Port1.1 INTA/B/C/D */ 101 #define MV78XX0_IRQ_PEX12INTA 38 /* PCIe Port1.2 INTA/B/C/D */ 102 #define MV78XX0_IRQ_PEX13INTA 39 /* PCIe Port1.3 INTA/B/C/D */ 103 #define MV78XX0_IRQ_GE00SUM 40 /* Gigabit Ethernet Port0 sum */ 104 #define MV78XX0_IRQ_GE00RX 41 /* Gigabit Ethernet Port0 Rx */ 105 #define MV78XX0_IRQ_GE00TX 42 /* Gigabit Ethernet Port0 Tx */ 106 #define MV78XX0_IRQ_GE00MISC 43 /* Gigabit Ethernet Port0 misc*/ 107 #define MV78XX0_IRQ_GE01SUM 44 /* Gigabit Ethernet Port1 sum */ 108 #define MV78XX0_IRQ_GE01RX 45 /* Gigabit Ethernet Port1 Rx */ 109 #define MV78XX0_IRQ_GE01TX 46 /* Gigabit Ethernet Port1 Tx */ 110 #define MV78XX0_IRQ_GE01MISC 47 /* Gigabit Ethernet Port1 misc*/ 111 #define MV78XX0_IRQ_GE10SUM 48 /* Gigabit Ethernet Port2 sum */ 112 #define MV78XX0_IRQ_GE10RX 49 /* Gigabit Ethernet Port2 Rx */ 113 #define MV78XX0_IRQ_GE10TX 50 /* Gigabit Ethernet Port2 Tx */ 114 #define MV78XX0_IRQ_GE10MISC 51 /* Gigabit Ethernet Port2 misc*/ 115 #define MV78XX0_IRQ_GE11SUM 52 /* Gigabit Ethernet Port3 sum */ 116 #define MV78XX0_IRQ_GE11RX 53 /* Gigabit Ethernet Port3 Rx */ 117 #define MV78XX0_IRQ_GE11TX 54 /* Gigabit Ethernet Port3 Tx */ 118 #define MV78XX0_IRQ_GE11MISC 55 /* Gigabit Ethernet Port3 misc*/ 119 #define MV78XX0_IRQ_GPIO0_7 56 /* GPIO[7:0] */ 120 #define MV78XX0_IRQ_GPIO8_15 57 /* GPIO[15:8] */ 121 #define MV78XX0_IRQ_GPIO16_23 58 /* GPIO[23:16] */ 122 #define MV78XX0_IRQ_GPIO24_31 59 /* GPIO[31:24] */ 123 #define MV78XX0_IRQ_DB_IN 60 /*Summary of Inbound Doorbell Cause*/ 124 #define MV78XX0_IRQ_DB_OUT 61/*Summary of Outbound Doorbell Cause*/ 125 126 127 /* 128 * Physical address of integrated peripherals 129 */ 130 131 #define MV78XX0_UNITID2PHYS(uid) ((MV78XX0_UNITID_ ## uid) << 16) 132 133 /* 134 * General Purpose Port Registers 135 */ 136 #define MV78XX0_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100) 137 #define MV78XX0_GPP_SIZE 0x100 138 139 /* 140 * Two-Wire Serial Interface Registers 141 */ 142 #define MV78XX0_TWSI1_BASE (MVSOC_DEVBUS_BASE + 0x1100) 143 144 /* 145 * UART Interface Registers 146 */ 147 /* NS16550 compatible */ 148 #define MV78XX0_COM2_BASE (MVSOC_DEVBUS_BASE + 0x2200) 149 #define MV78XX0_COM3_BASE (MVSOC_DEVBUS_BASE + 0x2300) 150 151 /* 152 * Reset Registers 153 */ 154 #define MV78XX0_SAMPLE_AT_RESET_LOW (MVSOC_DEVBUS_BASE + 0x0030) 155 #define MV78XX0_SAMPLE_AT_RESET_HIGH (MVSOC_DEVBUS_BASE + 0x0034) 156 157 158 /* 159 * Mbus-L to Mbus Bridge Registers 160 */ 161 /* CPU Address Map Registers */ 162 #define MV78XX0_MLMB_NWINDOW 14 163 #define MV78XX0_MLMB_NREMAP 8 164 165 #define MV78XX0_ICI_BASE(cpu) ((cpu)->ci_cpuid << 14) 166 167 /* Interrupt Controller Interface Registers */ 168 #define MV78XX0_ICI_MIECR 0x200 /* Main Interrupt Error Cause */ 169 #define MV78XX0_ICI_MICLR 0x204 /* Main Interrupt Cause Low */ 170 #define MV78XX0_ICI_MICHR 0x208 /* Main Interrupt Cause High */ 171 #define MV78XX0_ICI_IRQIMER 0x20c /* IRQ Interrupt Mask Error */ 172 #define MV78XX0_ICI_IRQIMLR 0x210 /* IRQ Interrupt Mask Low */ 173 #define MV78XX0_ICI_IRQIMHR 0x214 /* IRQ Interrupt Mask High */ 174 #define MV78XX0_ICI_IRQSCR 0x218 /* IRQ Select Cause */ 175 #define MV78XX0_ICI_FIQIMER 0x21c /* FIQ Interrupt Mask Error */ 176 #define MV78XX0_ICI_FIQIMLR 0x220 /* FIQ Interrupt Mask Low */ 177 #define MV78XX0_ICI_FIQIMHR 0x224 /* FIQ Interrupt Mask High */ 178 #define MV78XX0_ICI_FIQSCR 0x228 /* FIQ Select Cause */ 179 #define MV78XX0_ICI_EIMER 0x22c /* Endpoint Intr Mask Error */ 180 #define MV78XX0_ICI_EIMLR 0x230 /* Endpoint Intr Mask Low */ 181 #define MV78XX0_ICI_EIMHR 0x234 /* Endpoint Intr Mask High */ 182 #define MV78XX0_ICI_ESCR 0x238 /* Endpoint Select Cause */ 183 184 /* CPU Timers Registers */ 185 186 #define IRQ_IS_TIMER(n, irq) ((irq) == MV78XX0_IRQ_TIMER ## n) 187 #define MLMBI_TIMER(n) MVSOC_MLMB_MLMBI_CPUTIMER ## n ## INTREQ 188 #define TIMER_IRQ2MLMBIMR(irq) \ 189 IRQ_IS_TIMER(0, irq) ? MLMBI_TIMER(0) : \ 190 (IRQ_IS_TIMER(1, irq) ? MLMBI_TIMER(1) : \ 191 (IRQ_IS_TIMER(2, irq) ? MLMBI_TIMER(2) : MLMBI_TIMER(3))) 192 193 194 /* 195 * PCI Express Interface Registers 196 */ 197 #define MV78XX0_PEX1_BASE (MV78XX0_UNITID2PHYS(PEX1)) /* 0x80000 */ 198 199 /* 200 * USB 2.0 Interface Registers 201 */ 202 #define MV78XX0_USB_BASE (MV78XX0_UNITID2PHYS(USB)) /* 0x50000 */ 203 204 /* 205 * IDMA Controller and XOR Engine Registers 206 */ 207 #define MV78XX0_IDMAC_BASE (MV78XX0_UNITID2PHYS(IDMA)) /* 0x60000 */ 208 209 /* 210 * Gigabit Ethernet Registers 211 */ 212 #define MV78XX0_GBE0_BASE (MV78XX0_UNITID2PHYS(GBE01)) /* 0x70000 */ 213 #define MV78XX0_GBE1_BASE (MV78XX0_UNITID2PHYS(GBE01) + MVGBE_SIZE) 214 #define MV78XX0_GBE2_BASE (MV78XX0_UNITID2PHYS(GBE23)) /* 0x30000 */ 215 #define MV78XX0_GBE3_BASE (MV78XX0_UNITID2PHYS(GBE23) + MVGBE_SIZE) 216 217 /* 218 * Cryptographic Engine and Security Accelerator Registers 219 */ 220 #define MV78XX0_CESA_BASE (MV78XX0_UNITID2PHYS(CRYPT) + 0xd000)/*0x9d000*/ 221 222 /* 223 * Serial-ATA Host Controller (SATAHC) Registers 224 */ 225 #define MV78XX0_SATAHC_BASE (MV78XX0_UNITID2PHYS(SATA)) /* 0xa0000 */ 226 227 /* 228 * Time Division Multiplexing (TDM) Unit Registers 229 */ 230 #define MV78XX0_TDM_BASE (MV78XX0_UNITID2PHYS(TDM)) /* 0xb0000 */ 231 232 #endif /* _MV78XX0REG_H_ */ 233