1 /* $NetBSD: pci_machdep.c,v 1.16 2020/05/14 08:34:20 msaitoh Exp $ */
2 /*
3 * Copyright (c) 2008 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.16 2020/05/14 08:34:20 msaitoh Exp $");
30
31 #include "opt_mvsoc.h"
32 #include "gtpci.h"
33 #include "mvpex.h"
34 #include "pci.h"
35
36 #include <sys/param.h>
37 #include <sys/device.h>
38 #include <sys/extent.h>
39
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pciconf.h>
42
43 #include <arm/marvell/mvsocreg.h>
44 #include <arm/marvell/mvsocvar.h>
45 #include <arm/marvell/mvsocgppvar.h>
46 #if NGTPCI > 0
47 #include <dev/marvell/gtpcireg.h>
48 #include <dev/marvell/gtpcivar.h>
49 #endif
50 #if NMVPEX > 0
51 #include <dev/marvell/mvpexreg.h>
52 #include <dev/marvell/mvpexvar.h>
53 #endif
54
55 #include <machine/pci_machdep.h>
56
57 #if defined(ORION)
58 #include <arm/marvell/orionreg.h>
59 #endif
60 #if defined(KIRKWOOD)
61 #include <arm/marvell/kirkwoodreg.h>
62 #endif
63 #include <dev/marvell/marvellreg.h>
64
65
66 #if NGTPCI > 0
67 #if NGTPCI_MBUS > 0
68 static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int);
69 static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t);
70 #endif
71 static int gtpci_gpp_intr_map(const struct pci_attach_args *,
72 pci_intr_handle_t *);
73 static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t,
74 char *, size_t);
75 static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t);
76 static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *, const char *);
77 static void gtpci_gpp_intr_disestablish(void *, void *);
78
79 struct arm32_pci_chipset arm32_gtpci_chipset = {
80 .pc_attach_hook = gtpci_attach_hook,
81 .pc_bus_maxdevs = gtpci_bus_maxdevs,
82 .pc_make_tag = gtpci_make_tag,
83 .pc_decompose_tag = gtpci_decompose_tag,
84 #if NGTPCI_MBUS > 0
85 .pc_conf_read = gtpci_mbus_conf_read, /* XXXX: always this functions */
86 .pc_conf_write = gtpci_mbus_conf_write,
87 #else
88 .pc_conf_read = gtpci_conf_read,
89 .pc_conf_write = gtpci_conf_write,
90 #endif
91 .pc_intr_map = gtpci_gpp_intr_map,
92 .pc_intr_string = gtpci_gpp_intr_string,
93 .pc_intr_evcnt = gtpci_gpp_intr_evcnt,
94 .pc_intr_establish = gtpci_gpp_intr_establish,
95 .pc_intr_disestablish = gtpci_gpp_intr_disestablish,
96 #ifdef __HAVE_PCI_CONF_HOOK
97 .pc_conf_hook = gtpci_conf_hook,
98 #endif
99 .pc_conf_interrupt = gtpci_conf_interrupt,
100 };
101 #endif
102
103 #if NMVPEX > 0
104 #if NMVPEX_MBUS > 0
105 static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int);
106 #endif
107
108 struct arm32_pci_chipset arm32_mvpex0_chipset = {
109 .pc_attach_hook = mvpex_attach_hook,
110 .pc_bus_maxdevs = mvpex_bus_maxdevs,
111 .pc_make_tag = mvpex_make_tag,
112 .pc_decompose_tag = mvpex_decompose_tag,
113 #if NMVPEX_MBUS > 0
114 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
115 #else
116 .pc_conf_read = mvpex_conf_read,
117 #endif
118 .pc_conf_write = mvpex_conf_write,
119 .pc_intr_map = mvpex_intr_map,
120 .pc_intr_string = mvpex_intr_string,
121 .pc_intr_evcnt = mvpex_intr_evcnt,
122 .pc_intr_establish = mvpex_intr_establish,
123 .pc_intr_disestablish = mvpex_intr_disestablish,
124 #ifdef __HAVE_PCI_CONF_HOOK
125 .pc_conf_hook = mvpex_conf_hook,
126 #endif
127 .pc_conf_interrupt = mvpex_conf_interrupt,
128 };
129 struct arm32_pci_chipset arm32_mvpex1_chipset = {
130 .pc_attach_hook = mvpex_attach_hook,
131 .pc_bus_maxdevs = mvpex_bus_maxdevs,
132 .pc_make_tag = mvpex_make_tag,
133 .pc_decompose_tag = mvpex_decompose_tag,
134 #if NMVPEX_MBUS > 0
135 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
136 #else
137 .pc_conf_read = mvpex_conf_read,
138 #endif
139 .pc_conf_write = mvpex_conf_write,
140 .pc_intr_map = mvpex_intr_map,
141 .pc_intr_string = mvpex_intr_string,
142 .pc_intr_evcnt = mvpex_intr_evcnt,
143 .pc_intr_establish = mvpex_intr_establish,
144 .pc_intr_disestablish = mvpex_intr_disestablish,
145 #ifdef __HAVE_PCI_CONF_HOOK
146 .pc_conf_hook = mvpex_conf_hook,
147 #endif
148 .pc_conf_interrupt = mvpex_conf_interrupt,
149 };
150 struct arm32_pci_chipset arm32_mvpex2_chipset = {
151 .pc_attach_hook = mvpex_attach_hook,
152 .pc_bus_maxdevs = mvpex_bus_maxdevs,
153 .pc_make_tag = mvpex_make_tag,
154 .pc_decompose_tag = mvpex_decompose_tag,
155 #if NMVPEX_MBUS > 0
156 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
157 #else
158 .pc_conf_read = mvpex_conf_read,
159 #endif
160 .pc_conf_write = mvpex_conf_write,
161 .pc_intr_map = mvpex_intr_map,
162 .pc_intr_string = mvpex_intr_string,
163 .pc_intr_evcnt = mvpex_intr_evcnt,
164 .pc_intr_establish = mvpex_intr_establish,
165 .pc_intr_disestablish = mvpex_intr_disestablish,
166 #ifdef __HAVE_PCI_CONF_HOOK
167 .pc_conf_hook = mvpex_conf_hook,
168 #endif
169 .pc_conf_interrupt = mvpex_conf_interrupt,
170 };
171 struct arm32_pci_chipset arm32_mvpex3_chipset = {
172 .pc_attach_hook = mvpex_attach_hook,
173 .pc_bus_maxdevs = mvpex_bus_maxdevs,
174 .pc_make_tag = mvpex_make_tag,
175 .pc_decompose_tag = mvpex_decompose_tag,
176 #if NMVPEX_MBUS > 0
177 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
178 #else
179 .pc_conf_read = mvpex_conf_read,
180 #endif
181 .pc_conf_write = mvpex_conf_write,
182 .pc_intr_map = mvpex_intr_map,
183 .pc_intr_string = mvpex_intr_string,
184 .pc_intr_evcnt = mvpex_intr_evcnt,
185 .pc_intr_establish = mvpex_intr_establish,
186 .pc_intr_disestablish = mvpex_intr_disestablish,
187 #ifdef __HAVE_PCI_CONF_HOOK
188 .pc_conf_hook = mvpex_conf_hook,
189 #endif
190 .pc_conf_interrupt = mvpex_conf_interrupt,
191 };
192 struct arm32_pci_chipset arm32_mvpex4_chipset = {
193 .pc_attach_hook = mvpex_attach_hook,
194 .pc_bus_maxdevs = mvpex_bus_maxdevs,
195 .pc_make_tag = mvpex_make_tag,
196 .pc_decompose_tag = mvpex_decompose_tag,
197 #if NMVPEX_MBUS > 0
198 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
199 #else
200 .pc_conf_read = mvpex_conf_read,
201 #endif
202 .pc_conf_write = mvpex_conf_write,
203 .pc_intr_map = mvpex_intr_map,
204 .pc_intr_string = mvpex_intr_string,
205 .pc_intr_evcnt = mvpex_intr_evcnt,
206 .pc_intr_establish = mvpex_intr_establish,
207 .pc_intr_disestablish = mvpex_intr_disestablish,
208 #ifdef __HAVE_PCI_CONF_HOOK
209 .pc_conf_hook = mvpex_conf_hook,
210 #endif
211 .pc_conf_interrupt = mvpex_conf_interrupt,
212 };
213 struct arm32_pci_chipset arm32_mvpex5_chipset = {
214 .pc_attach_hook = mvpex_attach_hook,
215 .pc_bus_maxdevs = mvpex_bus_maxdevs,
216 .pc_make_tag = mvpex_make_tag,
217 .pc_decompose_tag = mvpex_decompose_tag,
218 #if NMVPEX_MBUS > 0
219 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
220 #else
221 .pc_conf_read = mvpex_conf_read,
222 #endif
223 .pc_conf_write = mvpex_conf_write,
224 .pc_intr_map = mvpex_intr_map,
225 .pc_intr_string = mvpex_intr_string,
226 .pc_intr_evcnt = mvpex_intr_evcnt,
227 .pc_intr_establish = mvpex_intr_establish,
228 .pc_intr_disestablish = mvpex_intr_disestablish,
229 #ifdef __HAVE_PCI_CONF_HOOK
230 .pc_conf_hook = mvpex_conf_hook,
231 #endif
232 .pc_conf_interrupt = mvpex_conf_interrupt,
233 };
234 struct arm32_pci_chipset arm32_mvpex6_chipset = {
235 .pc_attach_hook = mvpex_attach_hook,
236 .pc_bus_maxdevs = mvpex_bus_maxdevs,
237 .pc_make_tag = mvpex_make_tag,
238 .pc_decompose_tag = mvpex_decompose_tag,
239 #if NMVPEX_MBUS > 0
240 .pc_conf_read = mvpex_mbus_conf_read, /* XXXX: always this functions */
241 #else
242 .pc_conf_read = mvpex_conf_read,
243 #endif
244 .pc_conf_write = mvpex_conf_write,
245 .pc_intr_map = mvpex_intr_map,
246 .pc_intr_string = mvpex_intr_string,
247 .pc_intr_evcnt = mvpex_intr_evcnt,
248 .pc_intr_establish = mvpex_intr_establish,
249 .pc_intr_disestablish = mvpex_intr_disestablish,
250 #ifdef __HAVE_PCI_CONF_HOOK
251 .pc_conf_hook = mvpex_conf_hook,
252 #endif
253 .pc_conf_interrupt = mvpex_conf_interrupt,
254 };
255 #endif /* NMVPEX > 0 */
256
257 #if NGTPCI > 0
258 /* ARGSUSED */
259 void
gtpci_conf_interrupt(void * v,int bus,int dev,int pin,int swiz,int * iline)260 gtpci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz, int *iline)
261 {
262
263 /* nothing */
264 }
265
266 #if NGTPCI_MBUS > 0
267 #define GTPCI_MBUS_CA 0x0c78 /* Configuration Address */
268 #define GTPCI_MBUS_CD 0x0c7c /* Configuration Data */
269
270 static pcireg_t
gtpci_mbus_conf_read(void * v,pcitag_t tag,int reg)271 gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg)
272 {
273 struct gtpci_softc *sc = v;
274 const pcireg_t addr = tag | reg;
275
276 if ((unsigned int)reg >= PCI_CONF_SIZE)
277 return -1;
278
279 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
280 addr | GTPCI_CA_CONFIGEN);
281 if ((addr | GTPCI_CA_CONFIGEN) !=
282 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
283 return -1;
284
285 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD);
286 }
287
288 static void
gtpci_mbus_conf_write(void * v,pcitag_t tag,int reg,pcireg_t data)289 gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
290 {
291 struct gtpci_softc *sc = v;
292 pcireg_t addr = tag | (reg & 0xfc);
293
294 if ((unsigned int)reg >= PCI_CONF_SIZE)
295 return;
296
297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
298 addr | GTPCI_CA_CONFIGEN);
299 if ((addr | GTPCI_CA_CONFIGEN) !=
300 bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
301 return;
302
303 bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data);
304 }
305 #endif /* NGTPCI_MBUS */
306
307 /*
308 * We assume to use GPP interrupt as PCI interrupts.
309 * pci_intr_map() shall returns number of GPP between 0 and 31. However
310 * returns 0xff, because we do not know the connected pin number for GPP
311 * of your board.
312 * pci_intr_string() shall returns string "gpp <num>".
313 * pci_intr_establish() established interrupt in the pin of all GPP.
314 * Moreover, the return value will be disregarded. For instance, the
315 * setting for interrupt is not done.
316 */
317
318 /* ARGSUSED */
319 static int
gtpci_gpp_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)320 gtpci_gpp_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
321 {
322
323 *ihp = pa->pa_intrpin;
324 return 0;
325 }
326
327 /* ARGSUSED */
328 static const char *
gtpci_gpp_intr_string(void * v,pci_intr_handle_t pin,char * buf,size_t len)329 gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin, char *buf, size_t len)
330 {
331 struct gtpci_softc *sc = v;
332 prop_array_t int2gpp;
333 prop_object_t gpp;
334
335 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
336 gpp = prop_array_get(int2gpp, pin);
337 snprintf(buf, len, "gpp %d", (int)prop_number_integer_value(gpp));
338
339 return buf;
340 }
341
342 /* ARGSUSED */
343 static const struct evcnt *
gtpci_gpp_intr_evcnt(void * v,pci_intr_handle_t pin)344 gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin)
345 {
346
347 return NULL;
348 }
349
350 static void *
gtpci_gpp_intr_establish(void * v,pci_intr_handle_t int_pin,int ipl,int (* intrhand)(void *),void * intrarg,const char * xname)351 gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl,
352 int (*intrhand)(void *), void *intrarg, const char *xname)
353 {
354 struct gtpci_softc *sc = v;
355 prop_array_t int2gpp;
356 prop_object_t gpp;
357 int gpp_pin;
358
359 int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
360 gpp = prop_array_get(int2gpp, int_pin);
361 gpp_pin = prop_number_integer_value(gpp);
362 return mvsocgpp_intr_establish(gpp_pin, ipl, IST_LEVEL_LOW, intrhand,
363 intrarg);
364 }
365
366 static void
gtpci_gpp_intr_disestablish(void * v,void * ih)367 gtpci_gpp_intr_disestablish(void *v, void *ih)
368 {
369
370 mvsocgpp_intr_disestablish(ih);
371 }
372 #endif
373
374 #if NMVPEX_MBUS > 0
375 /* ARGSUSED */
376 void
mvpex_conf_interrupt(void * v,int bus,int dev,int ipin,int swiz,int * ilinep)377 mvpex_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep)
378 {
379
380 /* nothing */
381 }
382
383 static pcireg_t
mvpex_mbus_conf_read(void * v,pcitag_t tag,int reg)384 mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg)
385 {
386 struct mvpex_softc *sc = v;
387 pcireg_t addr, data, pci_cs;
388 uint32_t stat;
389 int bus, dev, func, pexbus, pexdev;
390
391 if ((unsigned int)reg >= PCI_CONF_SIZE)
392 return -1;
393
394 mvpex_decompose_tag(v, tag, &bus, &dev, &func);
395
396 stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
397 pexbus = MVPEX_STAT_PEXBUSNUM(stat);
398 pexdev = MVPEX_STAT_PEXDEVNUM(stat);
399 if (bus != pexbus || dev != pexdev)
400 if (stat & MVPEX_STAT_DLDOWN)
401 return -1;
402
403 if (bus == pexbus) {
404 if (pexdev == 0) {
405 if (dev != 1 && dev != pexdev)
406 return -1;
407 } else {
408 if (dev != 0 && dev != pexdev)
409 return -1;
410 }
411 if (func != 0)
412 return -1;
413 }
414
415 addr = ((reg & 0xf00) << 24) | tag | (reg & 0xfc);
416
417 #if defined(ORION)
418 /*
419 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration
420 * This guideline is relevant for all devices except of the following
421 * devices:
422 * 88F5281-BO and above, and 88F5181L-A0 and above
423 */
424 if ((bus != pexbus || dev != pexdev) &&
425 !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) &&
426 !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) {
427
428 /* PCI-Express configuration read work-around */
429 /*
430 * We will use one of the Punit (AHBToMbus) windows to
431 * access the xbar and read the data from there
432 *
433 * Need to configure the 2 free Punit (AHB to MBus bridge)
434 * address decoding windows:
435 * Configure the flash Window to handle Configuration space
436 * requests for PEX0/1:
437 *
438 * Configuration transactions from the CPU should write/read
439 * the data to/from address of the form:
440 * addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1)
441 * addr[27:24]: extended register number
442 * addr[23:16]: bus number
443 * addr[15:11]: device number
444 * addr[10: 8]: function number
445 * addr[ 7: 0]: register number
446 */
447
448 struct mvsoc_softc *soc =
449 device_private(device_parent(sc->sc_dev));
450 bus_space_handle_t pcicfg_ioh;
451 uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size;
452 int window, target, attr, base, size, s;
453 const int pex_pcicfg_tag =
454 (sc->sc_model == MARVELL_ORION_1_88F1181) ?
455 ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM;
456
457 window = mvsoc_target(pex_pcicfg_tag,
458 &target, &attr, &base, &size);
459 if (window >= nwindow) {
460 aprint_error_dev(sc->sc_dev,
461 "can't read pcicfg space\n");
462 return -1;
463 }
464
465 s = splhigh();
466
467 remapl = remaph = 0;
468 if (window == 0 || window == 1) {
469 remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window));
470 remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window));
471 }
472
473 wc =
474 MVSOC_MLMB_WCR_WINEN |
475 MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG) |
476 MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16);
477 if (sc->sc_model == MARVELL_ORION_1_88F1181) {
478 pcicfg_addr = base;
479 pcicfg_size = size;
480 } else if (sc->sc_model == MARVELL_ORION_1_88F5182) {
481 #define PEX_PCICFG_RW_WA_BASE 0x50000000
482 #define PEX_PCICFG_RW_WA_5182_BASE 0xf0000000
483 #define PEX_PCICFG_RW_WA_SIZE (16 * 1024 * 1024)
484 pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE;
485 pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
486 } else {
487 pcicfg_addr = PEX_PCICFG_RW_WA_BASE;
488 pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
489 }
490 write_mlmbreg(MVSOC_MLMB_WCR(window),
491 wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size));
492 write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr);
493
494 if (window == 0 || window == 1) {
495 write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr);
496 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
497 }
498
499 if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0,
500 &pcicfg_ioh) == 0) {
501 data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr);
502 bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size);
503 } else
504 data = -1;
505
506 write_mlmbreg(MVSOC_MLMB_WCR(window),
507 MVSOC_MLMB_WCR_WINEN |
508 MVSOC_MLMB_WCR_ATTR(attr) |
509 MVSOC_MLMB_WCR_TARGET(target) |
510 MVSOC_MLMB_WCR_SIZE(size));
511 write_mlmbreg(MVSOC_MLMB_WBR(window), base);
512 if (window == 0 || window == 1) {
513 write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl);
514 write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph);
515 }
516
517 splx(s);
518 #else
519 if (0) {
520 #endif
521 } else {
522 bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA,
523 addr | MVPEX_CA_CONFIGEN);
524 if ((addr | MVPEX_CA_CONFIGEN) !=
525 bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA))
526 return -1;
527
528 pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
529 PCI_COMMAND_STATUS_REG);
530 bus_space_write_4(sc->sc_iot, sc->sc_ioh,
531 PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT);
532
533 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD);
534 }
535
536 return data;
537 }
538 #endif
539