1 /* $NetBSD: s3c24x0_clk.c,v 1.15 2020/05/29 12:30:39 rin Exp $ */
2
3 /*
4 * Copyright (c) 2003 Genetec corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of Genetec corporation may not be used to endorse
16 * or promote products derived from this software without specific prior
17 * written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: s3c24x0_clk.c,v 1.15 2020/05/29 12:30:39 rin Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/atomic.h>
39 #include <sys/time.h>
40 #include <sys/timetc.h>
41
42 #include <sys/bus.h>
43 #include <machine/intr.h>
44 #include <arm/cpufunc.h>
45
46 #include <arm/s3c2xx0/s3c24x0reg.h>
47 #include <arm/s3c2xx0/s3c24x0var.h>
48
49
50 #ifndef STATHZ
51 #define STATHZ 64
52 #endif
53
54 #define TIMER_FREQUENCY(pclk) ((pclk)/16) /* divider=1/16 */
55
56 static uint32_t timer4_reload_value;
57 static uint32_t timer4_prescaler;
58 static uint32_t timer4_mseccount;
59
60 #define usec_to_counter(t) \
61 ((timer4_mseccount*(t))/1000)
62
63 #define counter_to_usec(c,pclk) \
64 (((c)*timer4_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000))
65
66 static u_int s3c24x0_get_timecount(struct timecounter *);
67
68 static struct timecounter s3c24x0_timecounter = {
69 .tc_get_timecount = s3c24x0_get_timecount,
70 .tc_counter_mask = 0xffffffff,
71 .tc_name = "s3c24x0",
72 .tc_quality = 100,
73 };
74
75 static volatile uint32_t s3c24x0_base;
76
77 static u_int
s3c24x0_get_timecount(struct timecounter * tc)78 s3c24x0_get_timecount(struct timecounter *tc)
79 {
80 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc;
81 int save, int_pend0, int_pend1, count;
82 int int_pend;
83
84 save = disable_interrupts(I32_bit);
85
86 again:
87 int_pend = bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh,
88 INTCTL_SRCPND);
89 int_pend0 = (1<<S3C24X0_INT_TIMER4) & int_pend;
90 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh,
91 TIMER_TCNTO(4));
92
93 for (;;) {
94
95 int_pend1 = bus_space_read_4(sc->sc_sx.sc_iot,
96 sc->sc_sx.sc_intctl_ioh, INTCTL_SRCPND);
97 int_pend1 &= (1<<S3C24X0_INT_TIMER4);
98 if( int_pend0 == int_pend1 )
99 break;
100
101 /*
102 * Down counter reached to zero while we were reading
103 * timer values. do it again to get consistent values.
104 */
105 int_pend0 = int_pend1;
106 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh,
107 TIMER_TCNTO(4));
108 }
109
110 if (__predict_false(count > timer4_reload_value)) {
111 /*
112 * Buggy Hardware Warning --- sometimes timer counter
113 * reads bogus value like 0xffff. I guess it happens when
114 * the timer is reloaded.
115 */
116 printf("Bogus value from timer counter: %d\n", count);
117 goto again;
118 }
119
120 restore_interrupts(save);
121
122 if (int_pend1 && count > 0) {
123 count -= timer4_reload_value;
124 }
125
126 return s3c24x0_base - count;
127 }
128
129 static inline int
read_timer(struct s3c24x0_softc * sc)130 read_timer(struct s3c24x0_softc *sc)
131 {
132 int count;
133
134 do {
135 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_timer_ioh,
136 TIMER_TCNTO(4));
137 } while ( __predict_false(count > timer4_reload_value) );
138
139 return count;
140 }
141
142 /*
143 * delay:
144 *
145 * Delay for at least N microseconds.
146 */
147 void
delay(u_int n)148 delay(u_int n)
149 {
150 struct s3c24x0_softc *sc = (struct s3c24x0_softc *) s3c2xx0_softc;
151 int v0, v1, delta;
152 u_int ucnt;
153
154 if ( timer4_reload_value == 0 ){
155 /* not initialized yet */
156 while ( n-- > 0 ){
157 int m;
158
159 for (m=0; m<100; ++m )
160 ;
161 }
162 return;
163 }
164
165 /* read down counter */
166 v0 = read_timer(sc);
167
168 ucnt = usec_to_counter(n);
169
170 while( ucnt > 0 ) {
171 v1 = read_timer(sc);
172 delta = v0 - v1;
173 if ( delta < 0 )
174 delta += timer4_reload_value;
175 #ifdef DEBUG
176 if (delta < 0 || delta > timer4_reload_value)
177 panic("wrong value from timer counter");
178 #endif
179
180 if((u_int)delta < ucnt){
181 ucnt -= (u_int)delta;
182 v0 = v1;
183 }
184 else {
185 ucnt = 0;
186 }
187 }
188 /*NOTREACHED*/
189 }
190
191 void
setstatclockrate(int newhz)192 setstatclockrate(int newhz)
193 {
194 }
195
196 static int
hardintr(void * arg)197 hardintr(void *arg)
198 {
199 atomic_add_32(&s3c24x0_base, timer4_reload_value);
200
201 hardclock((struct clockframe *)arg);
202
203 return 1;
204 }
205
206 static int
statintr(void * arg)207 statintr(void *arg)
208 {
209 statclock((struct clockframe *)arg);
210
211 return 1;
212 }
213
214 void
cpu_initclocks(void)215 cpu_initclocks(void)
216 {
217 struct s3c24x0_softc *sc = (struct s3c24x0_softc *)s3c2xx0_softc;
218 long tc;
219 int prescaler, h;
220 int pclk = s3c2xx0_softc->sc_pclk;
221 bus_space_tag_t iot = sc->sc_sx.sc_iot;
222 bus_space_handle_t ioh = sc->sc_timer_ioh;
223 uint32_t reg;
224
225 stathz = STATHZ;
226 profhz = stathz;
227
228 #define time_constant(hz) (TIMER_FREQUENCY(pclk) /(hz)/ prescaler)
229 #define calc_time_constant(hz) \
230 do { \
231 prescaler = 1; \
232 do { \
233 ++prescaler; \
234 tc = time_constant(hz); \
235 } while( tc > 65536 ); \
236 } while(0)
237
238
239 /* Use the channels 4 and 3 for hardclock and statclock, respectively */
240
241 /* stop all timers */
242 bus_space_write_4(iot, ioh, TIMER_TCON, 0);
243
244 /* calc suitable prescaler value */
245 h = MIN(hz,stathz);
246 calc_time_constant(h);
247
248 timer4_prescaler = prescaler;
249 timer4_reload_value = (TIMER_FREQUENCY(pclk) / hz / prescaler) - 1;
250 timer4_mseccount = TIMER_FREQUENCY(pclk)/timer4_prescaler/1000 ;
251
252 bus_space_write_4(iot, ioh, TIMER_TCNTB(4),
253 /*((prescaler - 1) << 16) |*/ (timer4_reload_value ));
254
255 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n",
256 hz, stathz, pclk, prescaler, tc);
257
258 bus_space_write_4(iot, ioh, TIMER_TCNTB(3),
259 /*((prescaler - 1) << 16) |*/ (time_constant(stathz)));
260
261 s3c24x0_intr_establish(S3C24X0_INT_TIMER4, IPL_CLOCK,
262 IST_NONE, hardintr, 0);
263 s3c24x0_intr_establish(S3C24X0_INT_TIMER3, IPL_HIGH,
264 IST_NONE, statintr, 0);
265
266 /* set prescaler1 */
267 reg = bus_space_read_4(iot, ioh, TIMER_TCFG0);
268 bus_space_write_4(iot, ioh, TIMER_TCFG0,
269 (reg & ~0xff00) | ((prescaler-1) << 8));
270
271 /* divider 1/16 for ch #3 and #4 */
272 reg = bus_space_read_4(iot, ioh, TIMER_TCFG1);
273 bus_space_write_4(iot, ioh, TIMER_TCFG1,
274 (reg & ~(TCFG1_MUX_MASK(3)|TCFG1_MUX_MASK(4))) |
275 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(3)) |
276 (TCFG1_MUX_DIV16 << TCFG1_MUX_SHIFT(4)) );
277
278
279 /* start timers */
280 reg = bus_space_read_4(iot, ioh, TIMER_TCON);
281 reg &= ~(TCON_MASK(3)|TCON_MASK(4));
282
283 s3c24x0_base = timer4_reload_value;
284
285 /* load the time constant */
286 bus_space_write_4(iot, ioh, TIMER_TCON, reg |
287 TCON_MANUALUPDATE(3) | TCON_MANUALUPDATE(4));
288 /* set auto reload and start */
289 bus_space_write_4(iot, ioh, TIMER_TCON, reg |
290 TCON_AUTORELOAD(3) | TCON_START(3) |
291 TCON_AUTORELOAD(4) | TCON_START(4) );
292
293 s3c24x0_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer4_prescaler;
294 tc_init(&s3c24x0_timecounter);
295 }
296
297
298 #if 0
299 /* test routine for delay() */
300
301 void delay_test(void);
302 void
303 delay_test(void)
304 {
305 struct s3c2xx0_softc *sc = s3c2xx0_softc;
306 volatile int *pdatc = (volatile int *)
307 ((char *)bus_space_vaddr(sc->sc_iot, sc->sc_gpio_ioh) + GPIO_PDATC);
308 static const int d[] = {0, 1, 5, 10, 50, 100, 500, 1000, -1};
309 int i;
310 int v = *pdatc & ~0x07;
311
312 for (;;) {
313 *pdatc = v | 2;
314
315 for (i=0; d[i] >= 0; ++i) {
316 *pdatc = v | 3;
317 delay(d[i]);
318 *pdatc = v | 2;
319 }
320 *pdatc = v;
321 }
322 }
323 #endif
324
325