1 /* $NetBSD: s3c2xx0_intr.h,v 1.15 2014/03/14 21:39:29 matt Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2003 Fujitsu Component Limited
5 * Copyright (c) 2002, 2003 Genetec Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of The Fujitsu Component Limited nor the name of
17 * Genetec corporation may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 /* Derived from i80321_intr.h */
36
37 /*
38 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
39 * All rights reserved.
40 *
41 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. All advertising materials mentioning features or use of this software
52 * must display the following acknowledgement:
53 * This product includes software developed for the NetBSD Project by
54 * Wasabi Systems, Inc.
55 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
56 * or promote products derived from this software without specific prior
57 * written permission.
58 *
59 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
61 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
62 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
63 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
64 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
65 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
66 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
67 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
68 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
69 * POSSIBILITY OF SUCH DAMAGE.
70 */
71
72 #ifndef _S3C2XX0_INTR_H_
73 #define _S3C2XX0_INTR_H_
74
75 #include <sys/evcnt.h>
76
77 #include <arm/cpu.h>
78 #include <arm/armreg.h>
79 #include <arm/cpufunc.h>
80 #include <machine/intr.h>
81
82 #include <arm/s3c2xx0/s3c2xx0reg.h>
83
84 typedef int (* s3c2xx0_irq_handler_t)(void *);
85
86 extern volatile uint32_t *s3c2xx0_intr_mask_reg;
87
88 extern volatile int intr_mask;
89 extern volatile int global_intr_mask;
90 #ifdef __HAVE_FAST_SOFTINTS
91 extern volatile int softint_pending;
92 #endif
93 extern int s3c2xx0_imask[];
94 extern int s3c2xx0_ilevel[];
95
96 void s3c2xx0_update_intr_masks( int, int );
97
98 static inline void
s3c2xx0_mask_interrupts(int mask)99 s3c2xx0_mask_interrupts(int mask)
100 {
101 int save = disable_interrupts(I32_bit);
102 global_intr_mask &= ~mask;
103 s3c2xx0_update_hw_mask();
104 restore_interrupts(save);
105 }
106
107 static inline void
s3c2xx0_unmask_interrupts(int mask)108 s3c2xx0_unmask_interrupts(int mask)
109 {
110 int save = disable_interrupts(I32_bit);
111 global_intr_mask |= mask;
112 s3c2xx0_update_hw_mask();
113 restore_interrupts(save);
114 }
115
116 static inline void
s3c2xx0_setipl(int new)117 s3c2xx0_setipl(int new)
118 {
119 set_curcpl(new);
120 intr_mask = s3c2xx0_imask[curcpl()];
121 s3c2xx0_update_hw_mask();
122 #ifdef __HAVE_FAST_SOFTINTS
123 update_softintr_mask();
124 #endif
125 }
126
127
128 static inline void
s3c2xx0_splx(int new)129 s3c2xx0_splx(int new)
130 {
131 int psw;
132
133 psw = disable_interrupts(I32_bit);
134 s3c2xx0_setipl(new);
135 restore_interrupts(psw);
136
137 #ifdef __HAVE_FAST_SOFTINTS
138 cpu_dosoftints();
139 #endif
140 }
141
142
143 static inline int
s3c2xx0_splraise(int ipl)144 s3c2xx0_splraise(int ipl)
145 {
146 int old, psw;
147
148 old = curcpl();
149 if( ipl > old ){
150 psw = disable_interrupts(I32_bit);
151 s3c2xx0_setipl(ipl);
152 restore_interrupts(psw);
153 }
154
155 return (old);
156 }
157
158 static inline int
s3c2xx0_spllower(int ipl)159 s3c2xx0_spllower(int ipl)
160 {
161 int old = curcpl();
162 int psw = disable_interrupts(I32_bit);
163 s3c2xx0_splx(ipl);
164 restore_interrupts(psw);
165 return(old);
166 }
167
168 int _splraise(int);
169 int _spllower(int);
170 void splx(int);
171
172 #if !defined(EVBARM_SPL_NOINLINE)
173
174 #define splx(new) s3c2xx0_splx(new)
175 #define _spllower(ipl) s3c2xx0_spllower(ipl)
176 #define _splraise(ipl) s3c2xx0_splraise(ipl)
177
178 #endif /* !EVBARM_SPL_NOINTR */
179
180
181 /*
182 * interrupt dispatch table.
183 */
184 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
185 struct intrhand {
186 TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
187 s3c2xx0_irq_handler_t ih_func; /* handler */
188 void *ih_arg; /* arg for handler */
189 };
190 #endif
191
192 #define IRQNAMESIZE sizeof("s3c2xx0 irq xx")
193
194 struct s3c2xx0_intr_dispatch {
195 #ifdef MULTIPLE_HANDLERS_ON_ONE_IRQ
196 TAILQ_HEAD(,intrhand) list;
197 #else
198 s3c2xx0_irq_handler_t func;
199 #endif
200 void *cookie; /* NULL for stackframe */
201 int level;
202 struct evcnt ev;
203 char name[IRQNAMESIZE];
204 };
205
206 /* used by s3c2{80,40,41}0 interrupt handler */
207 void s3c2xx0_intr_init(struct s3c2xx0_intr_dispatch *, int );
208
209 /* initialize some variable so that splfoo() doesn't touch ileegal
210 address during bootstrap */
211 void s3c2xx0_intr_bootstrap(vaddr_t);
212
213 #endif /* _S3C2XX0_INTR_H_ */
214