1/*        $NetBSD: hdlg_start.S,v 1.2 2011/01/31 06:28:03 matt Exp $  */
2
3/*
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *        This product includes software developed for the NetBSD Project by
20 *        Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38#include <machine/asm.h>
39#include <arm/armreg.h>
40#include "assym.h"
41
42RCSID("$NetBSD: hdlg_start.S,v 1.2 2011/01/31 06:28:03 matt Exp $")
43
44          .section .start,"ax",%progbits
45
46          .global   _C_LABEL(hdlg_start)
47_C_LABEL(hdlg_start):
48          /*
49           * We will go ahead and disable the MMU here so that we don't
50           * have to worry about flushing caches, etc.
51           *
52           * Note that we may not currently be running VA==PA, which means
53           * we'll need to leap to the next insn after disabing the MMU.
54           */
55          adr       r8, Lunmapped
56          bic       r8, r8, #0xff000000 /* clear upper 8 bits */
57          orr       r8, r8, #0xa0000000 /* OR in physical base address */
58
59          mrc       p15, 0, r2, c1, c0, 0
60          bic       r2, r2, #CPU_CONTROL_MMU_ENABLE
61          mcr       p15, 0, r2, c1, c0, 0
62
63          nop
64          nop
65          nop
66
67          mov       pc, r8                        /* Heave-ho! */
68
69Lunmapped:
70          /* reloc */
71          adr       r1, _C_LABEL(hdlg_start)
72          adr       r0, .Lstart
73          ldmia     r0, {r0, r2}
74          bic       r0, r0, #0xff000000
75          orr       r0, r0, #0xa0000000
76          bic       r2, r2, #0xff000000
77          orr       r2, r2, #0xa0000000
78          sub       r2, r2, r0          /* size = _edata - start */
79          cmp       r1, r0
80          beq       .Lreloc_done        /* if (dst == src) */
81          bcc       .Lreloc_backwards
82
831:        ldrb      r3, [r1], #1
84          strb      r3, [r0], #1
85          subs      r2, r2, #1
86          bne       1b
87          b         .Lreloc
88
89.Lreloc_backwards:
90          add       r0, r0, r2
91          add       r1, r1, r2
92          sub       r0, r0, #1
93          sub       r1, r1, #1
941:        ldrb      r3, [r1], #-1
95          strb      r3, [r0], #-1
96          subs      r2, r2, #1
97          bne       1b
98
99.Lreloc:
100          ldr       r0, .Lreloc_done
101          bic       r0, r0, #0xff000000
102          orr       r0, r0, #0xa0000000
103          mov       pc, r0
104
105.Lstart:
106          .word     _C_LABEL(hdlg_start)
107          .word     _edata
108
109.Lreloc_done:
110          .word     Lreloc_done
111
112Lreloc_done:
113          /*
114           * We want to construct a memory map that maps us
115           * VA==PA (SDRAM at 0xa0000000) and also double-maps
116           * that space at 0xc0000000 (where the kernel address
117           * space starts).  We create these mappings uncached
118           * and unbuffered to be safe.
119           *
120           * We also want to map the various devices we want to
121           * talk to VA==PA during bootstrap.
122           *
123           * We just use section mappings for all of this to make it easy.
124           *
125           * We will put the L1 table to do all this at 0xa0004000, which
126           * is also where RedBoot puts it.
127           */
128
129          /*
130           * Step 1: Map the entire address space VA==PA.
131           */
132          adr       r0, Ltable
133          ldr       r0, [r0]                      /* r0 = &l1table */
134
135          mov       r3, #(L1_S_AP_KRW)
136          orr       r3, r3, #(L1_TYPE_S)
137          mov       r2, #0x100000                           /* advance by 1MB */
138          mov       r1, #0x1000                             /* 4096MB */
1391:
140          str       r3, [r0], #0x04
141          add       r3, r3, r2
142          subs      r1, r1, #1
143          bgt       1b
144
145          /*
146           * Step 2: Map VA 0xc0000000->0xc7ffffff to PA 0xa0000000->0xa7ffffff.
147           */
148          adr       r0, Ltable                              /* r0 = &l1table */
149          ldr       r0, [r0]
150
151          mov       r3, #(L1_S_AP_KRW)
152          orr       r3, r3, #(L1_TYPE_S)
153          orr       r3, r3, #0xa0000000
154          add       r0, r0, #(0xc00 * 4)                    /* offset to 0xc00xxxxx */
155          mov       r1, #0x80                     /* 128MB */
1561:
157          str       r3, [r0], #0x04
158          add       r3, r3, r2
159          subs      r1, r1, #1
160          bgt       1b
161
162          /* OK!  Page table is set up.  Give it to the CPU. */
163          adr       r0, Ltable                              /* r0 = &l1table */
164          ldr       r0, [r0]
165          mcr       p15, 0, r0, c2, c0, 0
166
167          /* Flush the old TLBs, just in case. */
168          mcr       p15, 0, r0, c8, c7, 0
169
170          /* Set the Domain Access register.  Very important! */
171          mov       r0, #1
172          mcr       p15, 0, r0, c3, c0, 0
173
174          /* Get ready to jump to the "real" kernel entry point... */
175          ldr       r0, Lstart
176
177          /* OK, let's enable the MMU. */
178          mrc       p15, 0, r2, c1, c0, 0
179          orr       r2, r2, #CPU_CONTROL_MMU_ENABLE
180          mcr       p15, 0, r2, c1, c0, 0
181
182          nop
183          nop
184          nop
185
186          /* CPWAIT sequence to make sure the MMU is on... */
187          mrc       p15, 0, r2, c2, c0, 0         /* arbitrary read of CP15 */
188          mov       r2, r2                        /* force it to complete */
189          mov       pc, r0                        /* leap to kernel entry point! */
190
191Ltable:
192          .word     0xa0004000
193
194Lstart:
195          .word     start
196