1/* $NetBSD: ixm1200_start.S,v 1.6 2022/05/24 20:50:18 andvar Exp $ */ 2 3/* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ichiro FUKUHARA and Naoto Shimazaki. 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Jason R. Thorpe. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 36#include <arm/asm.h> 37#include <arm/armreg.h> 38#include "assym.h" 39 40 .section .start,"ax",%progbits 41 42RCSID("$NetBSD: ixm1200_start.S,v 1.6 2022/05/24 20:50:18 andvar Exp $") 43 44 .global _C_LABEL(ixm1200_start) 45_C_LABEL(ixm1200_start): 46 /* 47 * Disable IRQ and FIQ 48 */ 49 mrs r3, cpsr 50 orr r1, r3, #(I32_bit | F32_bit) 51 msr cpsr_all, r1 52 53 /* 54 * Setup coprocessor 15. 55 * 56 * We assume we've been loaded VA == PA, or that the MMU is 57 * disabled. We will go ahead and disable the MMU here 58 * so that we don't have to worry about flushing caches, etc. 59 */ 60 61 /* CONTROL_CP15 */ 62 mrc p15, 0, r0, c1, c0 ,0 /* read ctrl */ 63 bic r0, r0, #CPU_CONTROL_MMU_ENABLE 64 bic r0, r0, #CPU_CONTROL_AFLT_ENABLE 65 orr r0, r0, #CPU_CONTROL_DC_ENABLE 66 orr r0, r0, #CPU_CONTROL_WBUF_ENABLE 67 bic r0, r0, #CPU_CONTROL_BEND_ENABLE 68 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 69 bic r0, r0, #CPU_CONTROL_ROM_ENABLE 70 orr r0, r0, #CPU_CONTROL_IC_ENABLE 71 bic r0, r0, #CPU_CONTROL_VECRELOC 72 mcr p15, 0, r0, c1, c0 ,0 /* write ctrl */ 73 74 nop 75 nop 76 nop 77 78 /* TRANSLATION_TABLE_BASE */ 79 mov r0, #0 80 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 81 82 /* DOMAIN_ACCESS_CONTROL */ 83 mov r0, #0x00000001 /* use domain 0 as client */ 84 mcr p15, 0, r0, c3, c0 ,0 /* write domain */ 85 86 /* CACHE_CONTROL_OPERATIONS */ 87 mrc p15, 0, r0, c7, c7 ,0 /* flush D and I cache */ 88 mrc p15, 0, r0, c7, c10 ,4 /* drain write buffer */ 89 90 /* TLB_OPERATIONS */ 91 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 92 93 /* READ_BUFFER_OPERATIONS */ 94 mcr p15, 0, r0, c9, c0 ,0 /* flush all entries */ 95 mcr p15, 0, r0, c9, c0 ,4 /* disable user mode MCR access */ 96 97 /* PROCESS_ID_VIRTUAL_ADDR_MAPPING */ 98 mov r0, #0 99 mcr p15, 0, r0, c13, c0 ,0 /* process ID 0 100 101 /* BREAKPOINT_DEBUG_SUPPORT */ 102 mov r0, #0 103 mcr p15, 0, r0, c15, c0 ,0 /* DBAR = 0 */ 104 mcr p15, 0, r0, c15, c1 ,0 /* DBVR = 0 */ 105 mcr p15, 0, r0, c15, c2 ,0 /* DBMR = 0 */ 106 mcr p15, 0, r0, c15, c3 ,0 /* DBCR = 0 (never watch) */ 107 mcr p15, 0, r0, c15, c8 ,0 /* IBCR = 0 (never watch) */ 108 109 /* 110 * We want to construct a memory map that maps us 111 * VA == PA (SDRAM at 0xc0000000). We create these mappings 112 * uncached and unbuffered to be safe. 113 * 114 * We also want to map the various devices we want to 115 * talk to VA == PA during bootstrap. 116 * 117 * We also want to map the v0xf0000000 == p0x90000000 118 * to output early bootstrup messages to the console. 119 * 120 * We just use section mappings for all of this to make it easy. 121 * 122 * We will put the L1 table to do all this at c01fc000 123 * where is our KERNEL_TEXT_BASE - sizeof(L1 table). 124 */ 125 126 /* 127 * Step 1: Map the entire address space VA == PA. 128 */ 129 ldr r0, Ltable 130 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 131 mov r2, #(L1_S_SIZE) /* 1MB / section */ 132 mov r3, #(L1_S_AP_KRW) /* kernel read/write */ 133 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 1341: 135 str r3, [r0], #4 136 add r3, r3, r2 137 subs r1, r1, #1 138 bgt 1b 139 140 /* 141 * Step 2: Map VA 0xf0000000->0xf0100000 to PA 0x90000000->0x90100000. 142 */ 143 ldr r0, Ltable 144 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 145 mov r3, #0x90000000 146 add r3, r3, #0x00100000 /* set 0x90100000 to r3 */ 147 orr r3, r3, #(L1_S_AP_KRW) /* kernel read/write */ 148 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 149 str r3, [r0] 150 151 /* OK! Page table is set up. Give it to the CPU. */ 152 ldr r0, Ltable 153 mcr p15, 0, r0, c2, c0 ,0 /* write trans table base */ 154 mcr p15, 0, r0, c8, c7 ,0 /* flush D and I TLB */ 155 156 /* Get ready to jump to the "real" kernel entry point... */ 157 ldr r0, Lstart 158 159 /* OK, let's enable the MMU. */ 160 mrc p15, 0, r1, c1, c0 ,0 /* read ctrl */ 161 orr r1, r1, #CPU_CONTROL_MMU_ENABLE 162 mcr p15, 0, r1, c1, c0 ,0 /* write ctrl */ 163 164 nop 165 nop 166 nop 167 168 /* CPWAIT sequence to make sure the MMU is on... */ 169 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 170 mov r2, r2 /* force it to complete */ 171 mov pc, r0 /* leap to kernel entry point! */ 172 173Lstart: 174 .word start 175 176Ltable: 177 .word 0xc0200000 - 0x4000 /* our KERNEL_TEXT_BASE - 16KB */ 178 179/* end of ixm1200_start.S */ 180