1/* $NetBSD: mmnet_start.S,v 1.1 2011/11/04 17:40:48 aymeric Exp $ */ 2/* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33/* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62#include <machine/asm.h> 63#include <arm/armreg.h> 64#include <arm/arm32/pte.h> 65#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 66 67#ifndef SDRAM_START 68#define SDRAM_START 0x20000000 69#endif 70 71/* 72 * CPWAIT -- Canonical method to wait for CP15 update. 73 * NOTE: Clobbers the specified temp reg. 74 * copied from arm/arm/cpufunc_asm_xscale.S 75 * XXX: better be in a common header file. 76 */ 77#define CPWAIT_BRANCH \ 78 sub pc, pc, #4 79 80#define CPWAIT(tmp) \ 81 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 82 mov tmp, tmp /* wait for it to complete */ ;\ 83 CPWAIT_BRANCH /* branch to next insn */ 84 85/* 86 * Kernel start routine for the Propox MMnet 1002 87 * this code is executed at the very beginning after the kernel is loaded 88 * by U-Boot. 89 */ 90 .text 91 92 .global _C_LABEL(mmnet_start) 93_C_LABEL(mmnet_start): 94 /* 95 * Kernel is loaded in SDRAM (0x20200000), and is expected to run 96 * in VA 0xc0200000.. 97 */ 98 /* save u-boot's args */ 99 adr r4, u_boot_args 100 nop 101 nop 102 nop 103 stmia r4!, {r0, r1, r2, r3} 104 nop 105 nop 106 nop 107 108 /* Calculate RAM size */ 109 adr r4, ram_size 110 ldr r0, [r4] 1110: 112 add r3, r4, r0 113 ldr r1, [r3] 114 cmp r0, r1 115 beq 2f 1161: 117 add r0, r0, r0 /* r0 <<= 1 */ 118 str r0, [r4] 119 b 0b 1202: 121 mvn r1, r1 /* r1 ^= 0xffffffff */ 122 str r1, [r3] 123 ldr r2, [r4] 124 cmp r1, r2 125 beq 3f 126 str r0, [r3] /* restore */ 127 b 1b 1283: 129 str r0, [r4] 130 131 /* build page table from scratch */ 132 ldr r0, Lstartup_pagetable /* pagetable */ 133 adr r4, mmu_init_table 134 b 5f 135 1364: 137 str r3, [r0, r2] 138 add r2, r2, #4 139 add r3, r3, #(L1_S_SIZE) 140 adds r1, r1, #-1 141 bhi 4b 1425: 143 ldmia r4!, {r1, r2, r3} /* # of sections, PA|attr, VA */ 144 cmp r1, #0 145 bne 4b 146 147 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 148 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 149 150 /* Set the Domain Access register. Very important! */ 151 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 152 mcr p15, 0, r0, c3, c0, 0 153 154 /* Enable MMU */ 155 mrc p15, 0, r0, c1, c0, 0 156 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 157 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 158 mcr p15, 0, r0, c1, c0, 0 159 CPWAIT(r0) 160 161 /* Jump to kernel code in TRUE VA */ 162 adr r0, Lstart 163 ldr pc, [r0] 164 165Lstart: 166 .word start 167 168#ifndef STARTUP_PAGETABLE_ADDR 169#define STARTUP_PAGETABLE_ADDR 0x20000000 /* aligned 16kByte */ 170#endif 171Lstartup_pagetable: 172 .word STARTUP_PAGETABLE_ADDR 173 174 .globl _C_LABEL(u_boot_args) 175u_boot_args: 176 .space 16 /* r0, r1, r2, r3 */ 177 178 .globl _C_LABEL(ram_size) 179ram_size: 180 .word 0x04000000 /* 64Mbyte */ 181 182 183#define MMU_INIT(va,pa,n_sec,attr) \ 184 .word n_sec ; \ 185 .word 4 * ((va) >> L1_S_SHIFT) ; \ 186 .word (pa) | (attr) ; 187 188mmu_init_table: 189 /* fill all table VA==PA */ 190 MMU_INIT(0x00000000, 0x00000000, 191 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP(AP_KRW)) 192 193 /* map SDRAM VA==PA, WT cacheable */ 194 MMU_INIT(SDRAM_START, SDRAM_START, 195 64, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 196 197 /* map VA 0xc0000000..0xc3ffffff to PA 0x20000000..0x23ffffff */ 198 MMU_INIT(0xc0000000, SDRAM_START, 199 64, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 200 201 .word 0 /* end of table */ 202