1 /* $NetBSD: if_gfe.c,v 1.61 2024/07/05 04:31:51 rin Exp $ */
2
3 /*
4 * Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Allegro Networks, Inc., and Wasabi Systems, Inc.
19 * 4. The name of Allegro Networks, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
21 * written permission.
22 * 5. The name of Wasabi Systems, Inc. may not be used to endorse
23 * or promote products derived from this software without specific prior
24 * written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
27 * WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
28 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * if_gfe.c -- GT ethernet MAC driver
42 */
43
44 #include <sys/cdefs.h>
45 __KERNEL_RCSID(0, "$NetBSD: if_gfe.c,v 1.61 2024/07/05 04:31:51 rin Exp $");
46
47 #include "opt_inet.h"
48
49 #include <sys/param.h>
50 #include <sys/bus.h>
51 #include <sys/callout.h>
52 #include <sys/device.h>
53 #include <sys/errno.h>
54 #include <sys/ioctl.h>
55 #include <sys/mbuf.h>
56 #include <sys/mutex.h>
57 #include <sys/socket.h>
58
59 #include <net/if.h>
60 #include <net/if_dl.h>
61 #include <net/if_ether.h>
62 #include <net/if_media.h>
63
64 #ifdef INET
65 #include <netinet/in.h>
66 #include <netinet/if_inarp.h>
67 #endif
68 #include <net/bpf.h>
69 #include <sys/rndsource.h>
70
71 #include <dev/mii/mii.h>
72 #include <dev/mii/miivar.h>
73
74 #include <dev/marvell/gtreg.h>
75 #include <dev/marvell/gtvar.h>
76 #include <dev/marvell/gtethreg.h>
77 #include <dev/marvell/if_gfevar.h>
78 #include <dev/marvell/marvellreg.h>
79 #include <dev/marvell/marvellvar.h>
80
81 #include <prop/proplib.h>
82
83 #include "locators.h"
84
85
86 #define GE_READ(sc, reg) \
87 bus_space_read_4((sc)->sc_memt, (sc)->sc_memh, (reg))
88 #define GE_WRITE(sc, reg, v) \
89 bus_space_write_4((sc)->sc_memt, (sc)->sc_memh, (reg), (v))
90
91 #define GE_DEBUG
92 #if 0
93 #define GE_NOHASH
94 #define GE_NORX
95 #endif
96
97 #ifdef GE_DEBUG
98 #define GE_DPRINTF(sc, a) \
99 do { \
100 if ((sc)->sc_ec.ec_if.if_flags & IFF_DEBUG) \
101 printf a; \
102 } while (0 /* CONSTCOND */)
103 #define GE_FUNC_ENTER(sc, func) GE_DPRINTF(sc, ("[" func))
104 #define GE_FUNC_EXIT(sc, str) GE_DPRINTF(sc, (str "]"))
105 #else
106 #define GE_DPRINTF(sc, a) do { } while (0)
107 #define GE_FUNC_ENTER(sc, func) do { } while (0)
108 #define GE_FUNC_EXIT(sc, str) do { } while (0)
109 #endif
110 enum gfe_whack_op {
111 GE_WHACK_START, GE_WHACK_RESTART,
112 GE_WHACK_CHANGE, GE_WHACK_STOP
113 };
114
115 enum gfe_hash_op {
116 GE_HASH_ADD, GE_HASH_REMOVE,
117 };
118
119 #if 1
120 #define htogt32(a) htobe32(a)
121 #define gt32toh(a) be32toh(a)
122 #else
123 #define htogt32(a) htole32(a)
124 #define gt32toh(a) le32toh(a)
125 #endif
126
127 #define GE_RXDSYNC(sc, rxq, n, ops) \
128 bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \
129 (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \
130 (ops))
131 #define GE_RXDPRESYNC(sc, rxq, n) \
132 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)
133 #define GE_RXDPOSTSYNC(sc, rxq, n) \
134 GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)
135
136 #define GE_TXDSYNC(sc, txq, n, ops) \
137 bus_dmamap_sync((sc)->sc_dmat, (txq)->txq_desc_mem.gdm_map, \
138 (n) * sizeof((txq)->txq_descs[0]), sizeof((txq)->txq_descs[0]), \
139 (ops))
140 #define GE_TXDPRESYNC(sc, txq, n) \
141 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)
142 #define GE_TXDPOSTSYNC(sc, txq, n) \
143 GE_TXDSYNC(sc, txq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)
144
145 #define STATIC
146
147
148 STATIC int gfec_match(device_t, cfdata_t, void *);
149 STATIC void gfec_attach(device_t, device_t, void *);
150
151 STATIC int gfec_print(void *, const char *);
152 STATIC int gfec_search(device_t, cfdata_t, const int *, void *);
153
154 STATIC int gfec_enet_phy(device_t, int);
155 STATIC int gfec_mii_read(device_t, int, int, uint16_t *);
156 STATIC int gfec_mii_write(device_t, int, int, uint16_t);
157 STATIC void gfec_mii_statchg(struct ifnet *);
158
159 STATIC int gfe_match(device_t, cfdata_t, void *);
160 STATIC void gfe_attach(device_t, device_t, void *);
161
162 STATIC int gfe_dmamem_alloc(struct gfe_softc *, struct gfe_dmamem *, int,
163 size_t, int);
164 STATIC void gfe_dmamem_free(struct gfe_softc *, struct gfe_dmamem *);
165
166 STATIC int gfe_ifioctl(struct ifnet *, u_long, void *);
167 STATIC void gfe_ifstart(struct ifnet *);
168 STATIC void gfe_ifwatchdog(struct ifnet *);
169
170 STATIC void gfe_tick(void *arg);
171
172 STATIC void gfe_tx_restart(void *);
173 STATIC int gfe_tx_enqueue(struct gfe_softc *, enum gfe_txprio);
174 STATIC uint32_t gfe_tx_done(struct gfe_softc *, enum gfe_txprio, uint32_t);
175 STATIC void gfe_tx_cleanup(struct gfe_softc *, enum gfe_txprio, int);
176 STATIC int gfe_tx_txqalloc(struct gfe_softc *, enum gfe_txprio);
177 STATIC int gfe_tx_start(struct gfe_softc *, enum gfe_txprio);
178 STATIC void gfe_tx_stop(struct gfe_softc *, enum gfe_whack_op);
179
180 STATIC void gfe_rx_cleanup(struct gfe_softc *, enum gfe_rxprio);
181 STATIC void gfe_rx_get(struct gfe_softc *, enum gfe_rxprio);
182 STATIC int gfe_rx_prime(struct gfe_softc *);
183 STATIC uint32_t gfe_rx_process(struct gfe_softc *, uint32_t, uint32_t);
184 STATIC int gfe_rx_rxqalloc(struct gfe_softc *, enum gfe_rxprio);
185 STATIC int gfe_rx_rxqinit(struct gfe_softc *, enum gfe_rxprio);
186 STATIC void gfe_rx_stop(struct gfe_softc *, enum gfe_whack_op);
187
188 STATIC int gfe_intr(void *);
189
190 STATIC int gfe_whack(struct gfe_softc *, enum gfe_whack_op);
191
192 STATIC int gfe_hash_compute(struct gfe_softc *, const uint8_t [ETHER_ADDR_LEN]);
193 STATIC int gfe_hash_entry_op(struct gfe_softc *, enum gfe_hash_op,
194 enum gfe_rxprio, const uint8_t [ETHER_ADDR_LEN]);
195 STATIC int gfe_hash_multichg(struct ethercom *, const struct ether_multi *,
196 u_long);
197 STATIC int gfe_hash_fill(struct gfe_softc *);
198 STATIC int gfe_hash_alloc(struct gfe_softc *);
199
200
201 CFATTACH_DECL_NEW(gfec, sizeof(struct gfec_softc),
202 gfec_match, gfec_attach, NULL, NULL);
203 CFATTACH_DECL_NEW(gfe, sizeof(struct gfe_softc),
204 gfe_match, gfe_attach, NULL, NULL);
205
206
207 /* ARGSUSED */
208 int
gfec_match(device_t parent,cfdata_t cf,void * aux)209 gfec_match(device_t parent, cfdata_t cf, void *aux)
210 {
211 struct marvell_attach_args *mva = aux;
212
213 if (strcmp(mva->mva_name, cf->cf_name) != 0)
214 return 0;
215 if (mva->mva_offset == MVA_OFFSET_DEFAULT)
216 return 0;
217
218 mva->mva_size = ETHC_SIZE;
219 return 1;
220 }
221
222 /* ARGSUSED */
223 void
gfec_attach(device_t parent,device_t self,void * aux)224 gfec_attach(device_t parent, device_t self, void *aux)
225 {
226 struct gfec_softc *sc = device_private(self);
227 struct marvell_attach_args *mva = aux, gfea;
228 static int gfe_irqs[] = { 32, 33, 34 };
229 int i;
230
231 aprint_naive("\n");
232 aprint_normal(": Ethernet Controller\n");
233
234 sc->sc_dev = self;
235 sc->sc_iot = mva->mva_iot;
236 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
237 mva->mva_size, &sc->sc_ioh)) {
238 aprint_error_dev(self, "Cannot map registers\n");
239 return;
240 }
241
242 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_NET);
243
244 for (i = 0; i < ETH_NUM; i++) {
245 gfea.mva_name = "gfe";
246 gfea.mva_model = mva->mva_model;
247 gfea.mva_iot = sc->sc_iot;
248 gfea.mva_ioh = sc->sc_ioh;
249 gfea.mva_unit = i;
250 gfea.mva_dmat = mva->mva_dmat;
251 gfea.mva_irq = gfe_irqs[i];
252 config_found(sc->sc_dev, &gfea, gfec_print,
253 CFARGS(.submatch = gfec_search));
254 }
255 }
256
257 int
gfec_print(void * aux,const char * pnp)258 gfec_print(void *aux, const char *pnp)
259 {
260 struct marvell_attach_args *gfea = aux;
261
262 if (pnp)
263 aprint_normal("%s at %s port %d",
264 gfea->mva_name, pnp, gfea->mva_unit);
265 else {
266 if (gfea->mva_unit != GFECCF_PORT_DEFAULT)
267 aprint_normal(" port %d", gfea->mva_unit);
268 if (gfea->mva_irq != GFECCF_IRQ_DEFAULT)
269 aprint_normal(" irq %d", gfea->mva_irq);
270 }
271 return UNCONF;
272 }
273
274 /* ARGSUSED */
275 int
gfec_search(device_t parent,cfdata_t cf,const int * ldesc,void * aux)276 gfec_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
277 {
278 struct marvell_attach_args *gfea = aux;
279
280 if (cf->cf_loc[GFECCF_PORT] == gfea->mva_unit &&
281 cf->cf_loc[GFECCF_IRQ] != GFECCF_IRQ_DEFAULT)
282 gfea->mva_irq = cf->cf_loc[GFECCF_IRQ];
283
284 return config_match(parent, cf, aux);
285 }
286
287 int
gfec_enet_phy(device_t dev,int unit)288 gfec_enet_phy(device_t dev, int unit)
289 {
290 struct gfec_softc *sc = device_private(dev);
291 uint32_t epar;
292
293 epar = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ETH_EPAR);
294 return ETH_EPAR_PhyAD_GET(epar, unit);
295 }
296
297 int
gfec_mii_read(device_t dev,int phy,int reg,uint16_t * val)298 gfec_mii_read(device_t dev, int phy, int reg, uint16_t *val)
299 {
300 struct gfec_softc *csc = device_private(device_parent(dev));
301 uint32_t data;
302 int count = 10000;
303
304 mutex_enter(&csc->sc_mtx);
305
306 do {
307 DELAY(10);
308 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR);
309 } while ((data & ETH_ESMIR_Busy) && count-- > 0);
310
311 if (count == 0) {
312 aprint_error_dev(dev,
313 "mii read for phy %d reg %d busied out\n", phy, reg);
314 mutex_exit(&csc->sc_mtx);
315 return ETIMEDOUT;
316 }
317
318 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR,
319 ETH_ESMIR_READ(phy, reg));
320
321 count = 10000;
322 do {
323 DELAY(10);
324 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR);
325 } while ((data & ETH_ESMIR_ReadValid) == 0 && count-- > 0);
326
327 mutex_exit(&csc->sc_mtx);
328
329 if (count == 0) {
330 aprint_error_dev(dev,
331 "mii read for phy %d reg %d timed out\n", phy, reg);
332 return ETIMEDOUT;
333 }
334 #if defined(GTMIIDEBUG)
335 aprint_normal_dev(dev, "mii_read(%d, %d): %#x data %#x\n",
336 phy, reg, data, ETH_ESMIR_Value_GET(data));
337 #endif
338 *val = ETH_ESMIR_Value_GET(data);
339 return 0;
340 }
341
342 int
gfec_mii_write(device_t dev,int phy,int reg,uint16_t value)343 gfec_mii_write(device_t dev, int phy, int reg, uint16_t value)
344 {
345 struct gfec_softc *csc = device_private(device_parent(dev));
346 uint32_t data;
347 int count = 10000;
348
349 mutex_enter(&csc->sc_mtx);
350
351 do {
352 DELAY(10);
353 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR);
354 } while ((data & ETH_ESMIR_Busy) && count-- > 0);
355
356 if (count == 0) {
357 aprint_error_dev(dev,
358 "mii write for phy %d reg %d busied out (busy)\n",
359 phy, reg);
360 mutex_exit(&csc->sc_mtx);
361 return ETIMEDOUT;
362 }
363
364 bus_space_write_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR,
365 ETH_ESMIR_WRITE(phy, reg, value));
366
367 count = 10000;
368 do {
369 DELAY(10);
370 data = bus_space_read_4(csc->sc_iot, csc->sc_ioh, ETH_ESMIR);
371 } while ((data & ETH_ESMIR_Busy) && count-- > 0);
372
373 mutex_exit(&csc->sc_mtx);
374
375 if (count == 0) {
376 aprint_error_dev(dev,
377 "mii write for phy %d reg %d timed out\n", phy, reg);
378 return ETIMEDOUT;
379 }
380 #if defined(GTMIIDEBUG)
381 aprint_normal_dev(dev, "mii_write(%d, %d, %#hx)\n", phy, reg, value);
382 #endif
383 return 0;
384 }
385
386 void
gfec_mii_statchg(struct ifnet * ifp)387 gfec_mii_statchg(struct ifnet *ifp)
388 {
389 /* struct gfe_softc *sc = ifp->if_softc; */
390 /* do nothing? */
391 }
392
393 /* ARGSUSED */
394 int
gfe_match(device_t parent,cfdata_t cf,void * aux)395 gfe_match(device_t parent, cfdata_t cf, void *aux)
396 {
397
398 return 1;
399 }
400
401 /* ARGSUSED */
402 void
gfe_attach(device_t parent,device_t self,void * aux)403 gfe_attach(device_t parent, device_t self, void *aux)
404 {
405 struct marvell_attach_args *mva = aux;
406 struct gfe_softc * const sc = device_private(self);
407 struct ifnet * const ifp = &sc->sc_ec.ec_if;
408 struct mii_data * const mii = &sc->sc_mii;
409 uint32_t sdcr;
410 int phyaddr, error;
411 prop_data_t ea;
412 uint8_t enaddr[6];
413
414 aprint_naive("\n");
415 aprint_normal(": Ethernet Controller\n");
416
417 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
418 mva->mva_offset, mva->mva_size, &sc->sc_memh)) {
419 aprint_error_dev(self, "failed to map registers\n");
420 return;
421 }
422 sc->sc_dev = self;
423 sc->sc_memt = mva->mva_iot;
424 sc->sc_dmat = mva->mva_dmat;
425 sc->sc_macno = (mva->mva_offset == ETH_BASE(0)) ? 0 :
426 ((mva->mva_offset == ETH_BASE(1)) ? 1 : 2);
427
428 callout_init(&sc->sc_co, 0);
429
430 phyaddr = gfec_enet_phy(parent, sc->sc_macno);
431
432 ea = prop_dictionary_get(device_properties(sc->sc_dev), "mac-addr");
433 if (ea != NULL) {
434 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
435 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
436 memcpy(enaddr, prop_data_data_nocopy(ea), ETHER_ADDR_LEN);
437 }
438
439 sc->sc_pcr = GE_READ(sc, ETH_EPCR);
440 sc->sc_pcxr = GE_READ(sc, ETH_EPCXR);
441 sc->sc_intrmask = GE_READ(sc, ETH_EIMR) | ETH_IR_MIIPhySTC;
442
443 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr));
444
445 #if defined(DEBUG)
446 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr);
447 #endif
448
449 sc->sc_pcxr &= ~ETH_EPCXR_PRIOrx_Override;
450 if (device_cfdata(self)->cf_flags & 1) {
451 aprint_normal_dev(self, "phy %d (rmii)\n", phyaddr);
452 sc->sc_pcxr |= ETH_EPCXR_RMIIEn;
453 } else {
454 aprint_normal_dev(self, "phy %d (mii)\n", phyaddr);
455 sc->sc_pcxr &= ~ETH_EPCXR_RMIIEn;
456 }
457 if (device_cfdata(self)->cf_flags & 2)
458 sc->sc_flags |= GE_NOFREE;
459 /* Set Max Frame Length is 1536 */
460 sc->sc_pcxr &= ~ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_MASK);
461 sc->sc_pcxr |= ETH_EPCXR_MFL_SET(ETH_EPCXR_MFL_1536);
462 sc->sc_max_frame_length = 1536;
463
464 if (sc->sc_pcr & ETH_EPCR_EN) {
465 int tries = 1000;
466 /*
467 * Abort transmitter and receiver and wait for them to quiese
468 */
469 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR | ETH_ESDCMR_AT);
470 do {
471 delay(100);
472 if (tries-- <= 0) {
473 aprint_error_dev(self, "Abort TX/RX failed\n");
474 break;
475 }
476 } while (GE_READ(sc, ETH_ESDCMR) &
477 (ETH_ESDCMR_AR | ETH_ESDCMR_AT));
478 }
479
480 sc->sc_pcr &=
481 ~(ETH_EPCR_EN | ETH_EPCR_RBM | ETH_EPCR_PM | ETH_EPCR_PBF);
482
483 #if defined(DEBUG)
484 printf("pcr %#x, pcxr %#x\n", sc->sc_pcr, sc->sc_pcxr);
485 #endif
486
487 /*
488 * Now turn off the GT. If it didn't quiese, too ***ing bad.
489 */
490 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr);
491 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
492 sdcr = GE_READ(sc, ETH_ESDCR);
493 ETH_ESDCR_BSZ_SET(sdcr, ETH_ESDCR_BSZ_4);
494 sdcr |= ETH_ESDCR_RIFB;
495 GE_WRITE(sc, ETH_ESDCR, sdcr);
496
497 mii->mii_ifp = ifp;
498 mii->mii_readreg = gfec_mii_read;
499 mii->mii_writereg = gfec_mii_write;
500 mii->mii_statchg = gfec_mii_statchg;
501
502 sc->sc_ec.ec_mii = mii;
503 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
504
505 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr,
506 MII_OFFSET_ANY, MIIF_NOISOLATE);
507 if (LIST_FIRST(&mii->mii_phys) == NULL) {
508 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
509 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE);
510 } else
511 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
512
513 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
514 ifp->if_softc = sc;
515 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
516 #if 0
517 ifp->if_flags |= IFF_DEBUG;
518 #endif
519 ifp->if_ioctl = gfe_ifioctl;
520 ifp->if_start = gfe_ifstart;
521 ifp->if_watchdog = gfe_ifwatchdog;
522
523 if (sc->sc_flags & GE_NOFREE) {
524 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_HI);
525 if (!error)
526 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDHI);
527 if (!error)
528 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_MEDLO);
529 if (!error)
530 error = gfe_rx_rxqalloc(sc, GE_RXPRIO_LO);
531 if (!error)
532 error = gfe_tx_txqalloc(sc, GE_TXPRIO_HI);
533 if (!error)
534 error = gfe_hash_alloc(sc);
535 if (error)
536 aprint_error_dev(self,
537 "failed to allocate resources: %d\n", error);
538 }
539
540 if_attach(ifp);
541 ether_ifattach(ifp, enaddr);
542 bpf_attach(ifp, DLT_EN10MB, sizeof(struct ether_header));
543 rnd_attach_source(&sc->sc_rnd_source, device_xname(self), RND_TYPE_NET,
544 RND_FLAG_DEFAULT);
545 marvell_intr_establish(mva->mva_irq, IPL_NET, gfe_intr, sc);
546 }
547
548 int
gfe_dmamem_alloc(struct gfe_softc * sc,struct gfe_dmamem * gdm,int maxsegs,size_t size,int flags)549 gfe_dmamem_alloc(struct gfe_softc *sc, struct gfe_dmamem *gdm, int maxsegs,
550 size_t size, int flags)
551 {
552 int error = 0;
553 GE_FUNC_ENTER(sc, "gfe_dmamem_alloc");
554
555 KASSERT(gdm->gdm_kva == NULL);
556 gdm->gdm_size = size;
557 gdm->gdm_maxsegs = maxsegs;
558
559 error = bus_dmamem_alloc(sc->sc_dmat, gdm->gdm_size, PAGE_SIZE,
560 gdm->gdm_size, gdm->gdm_segs, gdm->gdm_maxsegs, &gdm->gdm_nsegs,
561 BUS_DMA_NOWAIT);
562 if (error)
563 goto fail;
564
565 error = bus_dmamem_map(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs,
566 gdm->gdm_size, &gdm->gdm_kva, flags | BUS_DMA_NOWAIT);
567 if (error)
568 goto fail;
569
570 error = bus_dmamap_create(sc->sc_dmat, gdm->gdm_size, gdm->gdm_nsegs,
571 gdm->gdm_size, 0, BUS_DMA_ALLOCNOW |BUS_DMA_NOWAIT, &gdm->gdm_map);
572 if (error)
573 goto fail;
574
575 error = bus_dmamap_load(sc->sc_dmat, gdm->gdm_map, gdm->gdm_kva,
576 gdm->gdm_size, NULL, BUS_DMA_NOWAIT);
577 if (error)
578 goto fail;
579
580 /* invalidate from cache */
581 bus_dmamap_sync(sc->sc_dmat, gdm->gdm_map, 0, gdm->gdm_size,
582 BUS_DMASYNC_PREREAD);
583 fail:
584 if (error) {
585 gfe_dmamem_free(sc, gdm);
586 GE_DPRINTF(sc, (":err=%d", error));
587 }
588 GE_DPRINTF(sc, (":kva=%p/%#x,map=%p,nsegs=%d,pa=%x/%x",
589 gdm->gdm_kva, gdm->gdm_size, gdm->gdm_map, gdm->gdm_map->dm_nsegs,
590 gdm->gdm_map->dm_segs->ds_addr, gdm->gdm_map->dm_segs->ds_len));
591 GE_FUNC_EXIT(sc, "");
592 return error;
593 }
594
595 void
gfe_dmamem_free(struct gfe_softc * sc,struct gfe_dmamem * gdm)596 gfe_dmamem_free(struct gfe_softc *sc, struct gfe_dmamem *gdm)
597 {
598 GE_FUNC_ENTER(sc, "gfe_dmamem_free");
599 if (gdm->gdm_map)
600 bus_dmamap_destroy(sc->sc_dmat, gdm->gdm_map);
601 if (gdm->gdm_kva)
602 bus_dmamem_unmap(sc->sc_dmat, gdm->gdm_kva, gdm->gdm_size);
603 if (gdm->gdm_nsegs > 0)
604 bus_dmamem_free(sc->sc_dmat, gdm->gdm_segs, gdm->gdm_nsegs);
605 gdm->gdm_map = NULL;
606 gdm->gdm_kva = NULL;
607 gdm->gdm_nsegs = 0;
608 GE_FUNC_EXIT(sc, "");
609 }
610
611 int
gfe_ifioctl(struct ifnet * ifp,u_long cmd,void * data)612 gfe_ifioctl(struct ifnet *ifp, u_long cmd, void *data)
613 {
614 struct gfe_softc * const sc = ifp->if_softc;
615 struct ifreq *ifr = (struct ifreq *) data;
616 struct ifaddr *ifa = (struct ifaddr *) data;
617 int s, error = 0;
618
619 GE_FUNC_ENTER(sc, "gfe_ifioctl");
620 s = splnet();
621
622 switch (cmd) {
623 case SIOCINITIFADDR:
624 ifp->if_flags |= IFF_UP;
625 error = gfe_whack(sc, GE_WHACK_START);
626 switch (ifa->ifa_addr->sa_family) {
627 #ifdef INET
628 case AF_INET:
629 if (error == 0)
630 arp_ifinit(ifp, ifa);
631 break;
632 #endif
633 default:
634 break;
635 }
636 break;
637
638 case SIOCSIFFLAGS:
639 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
640 break;
641 /* XXX re-use ether_ioctl() */
642 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
643 case IFF_UP | IFF_RUNNING:/* active->active, update */
644 error = gfe_whack(sc, GE_WHACK_CHANGE);
645 break;
646 case IFF_RUNNING: /* not up, so we stop */
647 error = gfe_whack(sc, GE_WHACK_STOP);
648 break;
649 case IFF_UP: /* not running, so we start */
650 error = gfe_whack(sc, GE_WHACK_START);
651 break;
652 case 0: /* idle->idle: do nothing */
653 break;
654 }
655 break;
656
657 case SIOCSIFMTU:
658 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
659 error = EINVAL;
660 break;
661 }
662 if ((error = ifioctl_common(ifp, cmd, data)) == ENETRESET)
663 error = 0;
664 break;
665
666 default:
667 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
668 if (ifp->if_flags & IFF_RUNNING)
669 error = gfe_whack(sc, GE_WHACK_CHANGE);
670 else
671 error = 0;
672 }
673 break;
674 }
675 splx(s);
676 GE_FUNC_EXIT(sc, "");
677 return error;
678 }
679
680 void
gfe_ifstart(struct ifnet * ifp)681 gfe_ifstart(struct ifnet *ifp)
682 {
683 struct gfe_softc * const sc = ifp->if_softc;
684 struct mbuf *m;
685
686 GE_FUNC_ENTER(sc, "gfe_ifstart");
687
688 if ((ifp->if_flags & IFF_RUNNING) == 0) {
689 GE_FUNC_EXIT(sc, "$");
690 return;
691 }
692
693 for (;;) {
694 IF_POLL(&ifp->if_snd, m);
695 if (m == NULL) {
696 ifp->if_flags &= ~IFF_OACTIVE;
697 GE_FUNC_EXIT(sc, "");
698 return;
699 }
700
701 /*
702 * No space in the pending queue? try later.
703 */
704 if (IF_QFULL(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq))
705 break;
706
707 IF_DEQUEUE(&ifp->if_snd, m);
708
709 /*
710 * Try to enqueue a mbuf to the device. If that fails, we
711 * can always try to map the next mbuf.
712 */
713 IF_ENQUEUE(&sc->sc_txq[GE_TXPRIO_HI].txq_pendq, m);
714 GE_DPRINTF(sc, (">"));
715 #ifndef GE_NOTX
716 (void) gfe_tx_enqueue(sc, GE_TXPRIO_HI);
717 #endif
718 }
719
720 /*
721 * Attempt to queue the mbuf for send failed.
722 */
723 ifp->if_flags |= IFF_OACTIVE;
724 GE_FUNC_EXIT(sc, "%%");
725 }
726
727 void
gfe_ifwatchdog(struct ifnet * ifp)728 gfe_ifwatchdog(struct ifnet *ifp)
729 {
730 struct gfe_softc * const sc = ifp->if_softc;
731 struct gfe_txqueue * const txq = &sc->sc_txq[GE_TXPRIO_HI];
732
733 GE_FUNC_ENTER(sc, "gfe_ifwatchdog");
734 aprint_error_dev(sc->sc_dev, "device timeout");
735 if (ifp->if_flags & IFF_RUNNING) {
736 uint32_t curtxdnum;
737
738 curtxdnum = (GE_READ(sc, txq->txq_ectdp) -
739 txq->txq_desc_busaddr) / sizeof(txq->txq_descs[0]);
740 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi);
741 GE_TXDPOSTSYNC(sc, txq, curtxdnum);
742 aprint_error(" (fi=%d(%#x),lo=%d,cur=%d(%#x),icm=%#x) ",
743 txq->txq_fi, txq->txq_descs[txq->txq_fi].ed_cmdsts,
744 txq->txq_lo, curtxdnum, txq->txq_descs[curtxdnum].ed_cmdsts,
745 GE_READ(sc, ETH_EICR));
746 GE_TXDPRESYNC(sc, txq, txq->txq_fi);
747 GE_TXDPRESYNC(sc, txq, curtxdnum);
748 }
749 aprint_error("\n");
750 if_statinc(ifp, if_oerrors);
751 (void) gfe_whack(sc, GE_WHACK_RESTART);
752 GE_FUNC_EXIT(sc, "");
753 }
754
755 int
gfe_rx_rxqalloc(struct gfe_softc * sc,enum gfe_rxprio rxprio)756 gfe_rx_rxqalloc(struct gfe_softc *sc, enum gfe_rxprio rxprio)
757 {
758 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
759 int error;
760
761 GE_FUNC_ENTER(sc, "gfe_rx_rxqalloc");
762 GE_DPRINTF(sc, ("(%d)", rxprio));
763
764 error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1,
765 GE_RXDESC_MEMSIZE, BUS_DMA_NOCACHE);
766 if (error) {
767 GE_FUNC_EXIT(sc, "!!");
768 return error;
769 }
770
771 error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS,
772 GE_RXBUF_MEMSIZE, 0);
773 if (error) {
774 GE_FUNC_EXIT(sc, "!!!");
775 return error;
776 }
777 GE_FUNC_EXIT(sc, "");
778 return error;
779 }
780
781 int
gfe_rx_rxqinit(struct gfe_softc * sc,enum gfe_rxprio rxprio)782 gfe_rx_rxqinit(struct gfe_softc *sc, enum gfe_rxprio rxprio)
783 {
784 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
785 volatile struct gt_eth_desc *rxd;
786 const bus_dma_segment_t *ds;
787 int idx;
788 bus_addr_t nxtaddr;
789 bus_size_t boff;
790
791 GE_FUNC_ENTER(sc, "gfe_rx_rxqinit");
792 GE_DPRINTF(sc, ("(%d)", rxprio));
793
794 if ((sc->sc_flags & GE_NOFREE) == 0) {
795 int error = gfe_rx_rxqalloc(sc, rxprio);
796 if (error) {
797 GE_FUNC_EXIT(sc, "!");
798 return error;
799 }
800 } else {
801 KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL);
802 KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL);
803 }
804
805 memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE);
806
807 rxq->rxq_descs =
808 (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva;
809 rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr;
810 rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva;
811 rxq->rxq_fi = 0;
812 rxq->rxq_active = GE_RXDESC_MAX;
813 boff = 0;
814 ds = rxq->rxq_buf_mem.gdm_map->dm_segs;
815 nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd);
816 for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX;
817 idx++, rxd++, nxtaddr += sizeof(*rxd)) {
818 rxd->ed_lencnt = htogt32(GE_RXBUF_SIZE << 16);
819 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI);
820 rxd->ed_bufptr = htogt32(ds->ds_addr + boff);
821 /*
822 * update the nxtptr to point to the next txd.
823 */
824 if (idx == GE_RXDESC_MAX - 1)
825 nxtaddr = rxq->rxq_desc_busaddr;
826 rxd->ed_nxtptr = htogt32(nxtaddr);
827 boff += GE_RXBUF_SIZE;
828 if (boff == ds->ds_len) {
829 ds++;
830 boff = 0;
831 }
832 }
833 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0,
834 rxq->rxq_desc_mem.gdm_map->dm_mapsize,
835 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
836 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0,
837 rxq->rxq_buf_mem.gdm_map->dm_mapsize,
838 BUS_DMASYNC_PREREAD);
839
840 rxq->rxq_intrbits = ETH_IR_RxBuffer | ETH_IR_RxError;
841 switch (rxprio) {
842 case GE_RXPRIO_HI:
843 rxq->rxq_intrbits |= ETH_IR_RxBuffer_3 | ETH_IR_RxError_3;
844 rxq->rxq_efrdp = ETH_EFRDP3;
845 rxq->rxq_ecrdp = ETH_ECRDP3;
846 break;
847 case GE_RXPRIO_MEDHI:
848 rxq->rxq_intrbits |= ETH_IR_RxBuffer_2 | ETH_IR_RxError_2;
849 rxq->rxq_efrdp = ETH_EFRDP2;
850 rxq->rxq_ecrdp = ETH_ECRDP2;
851 break;
852 case GE_RXPRIO_MEDLO:
853 rxq->rxq_intrbits |= ETH_IR_RxBuffer_1 | ETH_IR_RxError_1;
854 rxq->rxq_efrdp = ETH_EFRDP1;
855 rxq->rxq_ecrdp = ETH_ECRDP1;
856 break;
857 case GE_RXPRIO_LO:
858 rxq->rxq_intrbits |= ETH_IR_RxBuffer_0 | ETH_IR_RxError_0;
859 rxq->rxq_efrdp = ETH_EFRDP0;
860 rxq->rxq_ecrdp = ETH_ECRDP0;
861 break;
862 }
863 GE_FUNC_EXIT(sc, "");
864 return 0;
865 }
866
867 void
gfe_rx_get(struct gfe_softc * sc,enum gfe_rxprio rxprio)868 gfe_rx_get(struct gfe_softc *sc, enum gfe_rxprio rxprio)
869 {
870 struct ifnet * const ifp = &sc->sc_ec.ec_if;
871 struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
872 struct mbuf *m = rxq->rxq_curpkt;
873
874 GE_FUNC_ENTER(sc, "gfe_rx_get");
875 GE_DPRINTF(sc, ("(%d)", rxprio));
876
877 while (rxq->rxq_active > 0) {
878 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi];
879 struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi];
880 const struct ether_header *eh;
881 unsigned int cmdsts;
882 size_t buflen;
883
884 GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi);
885 cmdsts = gt32toh(rxd->ed_cmdsts);
886 GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts));
887 rxq->rxq_cmdsts = cmdsts;
888 /*
889 * Sometimes the GE "forgets" to reset the ownership bit.
890 * But if the length has been rewritten, the packet is ours
891 * so pretend the O bit is set.
892 */
893 buflen = gt32toh(rxd->ed_lencnt) & 0xffff;
894 if ((cmdsts & RX_CMD_O) && buflen == 0) {
895 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi);
896 break;
897 }
898
899 /*
900 * If this is not a single buffer packet with no errors
901 * or for some reason it's bigger than our frame size,
902 * ignore it and go to the next packet.
903 */
904 if ((cmdsts & (RX_CMD_F | RX_CMD_L | RX_STS_ES)) !=
905 (RX_CMD_F | RX_CMD_L) ||
906 (buflen > sc->sc_max_frame_length)) {
907 GE_DPRINTF(sc, ("!"));
908 --rxq->rxq_active;
909 if_statinc(ifp, if_ipackets);
910 if_statinc(ifp, if_ierrors);
911 goto give_it_back;
912 }
913
914 /* CRC is included with the packet; trim it off. */
915 buflen -= ETHER_CRC_LEN;
916
917 if (m == NULL) {
918 MGETHDR(m, M_DONTWAIT, MT_DATA);
919 if (m == NULL) {
920 GE_DPRINTF(sc, ("?"));
921 break;
922 }
923 }
924 if ((m->m_flags & M_EXT) == 0 && buflen > MHLEN - 2) {
925 MCLGET(m, M_DONTWAIT);
926 if ((m->m_flags & M_EXT) == 0) {
927 GE_DPRINTF(sc, ("?"));
928 break;
929 }
930 }
931 m->m_data += 2;
932 m->m_len = 0;
933 m->m_pkthdr.len = 0;
934 m_set_rcvif(m, ifp);
935 rxq->rxq_cmdsts = cmdsts;
936 --rxq->rxq_active;
937
938 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map,
939 rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD);
940
941 KASSERT(m->m_len == 0 && m->m_pkthdr.len == 0);
942 memcpy(m->m_data + m->m_len, rxb->rxb_data, buflen);
943 m->m_len = buflen;
944 m->m_pkthdr.len = buflen;
945
946 eh = (const struct ether_header *) m->m_data;
947 if ((ifp->if_flags & IFF_PROMISC) ||
948 (rxq->rxq_cmdsts & RX_STS_M) == 0 ||
949 (rxq->rxq_cmdsts & RX_STS_HE) ||
950 (eh->ether_dhost[0] & 1) != 0 ||
951 memcmp(eh->ether_dhost, CLLADDR(ifp->if_sadl),
952 ETHER_ADDR_LEN) == 0) {
953 if_percpuq_enqueue(ifp->if_percpuq, m);
954 m = NULL;
955 GE_DPRINTF(sc, (">"));
956 } else {
957 m->m_len = 0;
958 m->m_pkthdr.len = 0;
959 GE_DPRINTF(sc, ("+"));
960 }
961 rxq->rxq_cmdsts = 0;
962
963 give_it_back:
964 rxd->ed_lencnt &= ~0xffff; /* zero out length */
965 rxd->ed_cmdsts = htogt32(RX_CMD_F|RX_CMD_L|RX_CMD_O|RX_CMD_EI);
966 #if 0
967 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)",
968 rxq->rxq_fi,
969 ((unsigned long *)rxd)[0], ((unsigned long *)rxd)[1],
970 ((unsigned long *)rxd)[2], ((unsigned long *)rxd)[3]));
971 #endif
972 GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi);
973 if (++rxq->rxq_fi == GE_RXDESC_MAX)
974 rxq->rxq_fi = 0;
975 rxq->rxq_active++;
976 }
977 rxq->rxq_curpkt = m;
978 GE_FUNC_EXIT(sc, "");
979 }
980
981 uint32_t
gfe_rx_process(struct gfe_softc * sc,uint32_t cause,uint32_t intrmask)982 gfe_rx_process(struct gfe_softc *sc, uint32_t cause, uint32_t intrmask)
983 {
984 struct ifnet * const ifp = &sc->sc_ec.ec_if;
985 struct gfe_rxqueue *rxq;
986 uint32_t rxbits;
987 #define RXPRIO_DECODER 0xffffaa50
988 GE_FUNC_ENTER(sc, "gfe_rx_process");
989
990 rxbits = ETH_IR_RxBuffer_GET(cause);
991 while (rxbits) {
992 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3;
993 GE_DPRINTF(sc, ("%1x", rxbits));
994 rxbits &= ~(1 << rxprio);
995 gfe_rx_get(sc, rxprio);
996 }
997
998 rxbits = ETH_IR_RxError_GET(cause);
999 while (rxbits) {
1000 enum gfe_rxprio rxprio = (RXPRIO_DECODER >> (rxbits * 2)) & 3;
1001 uint32_t masks[(GE_RXDESC_MAX + 31) / 32];
1002 int idx;
1003 rxbits &= ~(1 << rxprio);
1004 rxq = &sc->sc_rxq[rxprio];
1005 sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits);
1006 intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits);
1007 if ((sc->sc_tickflags & GE_TICK_RX_RESTART) == 0) {
1008 sc->sc_tickflags |= GE_TICK_RX_RESTART;
1009 callout_reset(&sc->sc_co, 1, gfe_tick, sc);
1010 }
1011 if_statinc(ifp, if_ierrors);
1012 GE_DPRINTF(sc, ("%s: rx queue %d filled at %u\n",
1013 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi));
1014 memset(masks, 0, sizeof(masks));
1015 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map,
1016 0, rxq->rxq_desc_mem.gdm_size,
1017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1018 for (idx = 0; idx < GE_RXDESC_MAX; idx++) {
1019 volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx];
1020
1021 if (RX_CMD_O & gt32toh(rxd->ed_cmdsts))
1022 masks[idx/32] |= 1 << (idx & 31);
1023 }
1024 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map,
1025 0, rxq->rxq_desc_mem.gdm_size,
1026 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1027 #if defined(DEBUG)
1028 printf("%s: rx queue %d filled at %u=%#x(%#x/%#x)\n",
1029 device_xname(sc->sc_dev), rxprio, rxq->rxq_fi,
1030 rxq->rxq_cmdsts, masks[0], masks[1]);
1031 #endif
1032 }
1033 if ((intrmask & ETH_IR_RxBits) == 0)
1034 intrmask &= ~(ETH_IR_RxBuffer | ETH_IR_RxError);
1035
1036 GE_FUNC_EXIT(sc, "");
1037 return intrmask;
1038 }
1039
1040 int
gfe_rx_prime(struct gfe_softc * sc)1041 gfe_rx_prime(struct gfe_softc *sc)
1042 {
1043 struct gfe_rxqueue *rxq;
1044 int error;
1045
1046 GE_FUNC_ENTER(sc, "gfe_rx_prime");
1047
1048 error = gfe_rx_rxqinit(sc, GE_RXPRIO_HI);
1049 if (error)
1050 goto bail;
1051 rxq = &sc->sc_rxq[GE_RXPRIO_HI];
1052 if ((sc->sc_flags & GE_RXACTIVE) == 0) {
1053 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr);
1054 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr);
1055 }
1056 sc->sc_intrmask |= rxq->rxq_intrbits;
1057
1058 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDHI);
1059 if (error)
1060 goto bail;
1061 if ((sc->sc_flags & GE_RXACTIVE) == 0) {
1062 rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI];
1063 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr);
1064 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr);
1065 sc->sc_intrmask |= rxq->rxq_intrbits;
1066 }
1067
1068 error = gfe_rx_rxqinit(sc, GE_RXPRIO_MEDLO);
1069 if (error)
1070 goto bail;
1071 if ((sc->sc_flags & GE_RXACTIVE) == 0) {
1072 rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO];
1073 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr);
1074 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr);
1075 sc->sc_intrmask |= rxq->rxq_intrbits;
1076 }
1077
1078 error = gfe_rx_rxqinit(sc, GE_RXPRIO_LO);
1079 if (error)
1080 goto bail;
1081 if ((sc->sc_flags & GE_RXACTIVE) == 0) {
1082 rxq = &sc->sc_rxq[GE_RXPRIO_LO];
1083 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr);
1084 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr);
1085 sc->sc_intrmask |= rxq->rxq_intrbits;
1086 }
1087
1088 bail:
1089 GE_FUNC_EXIT(sc, "");
1090 return error;
1091 }
1092
1093 void
gfe_rx_cleanup(struct gfe_softc * sc,enum gfe_rxprio rxprio)1094 gfe_rx_cleanup(struct gfe_softc *sc, enum gfe_rxprio rxprio)
1095 {
1096 struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio];
1097 GE_FUNC_ENTER(sc, "gfe_rx_cleanup");
1098 if (rxq == NULL) {
1099 GE_FUNC_EXIT(sc, "");
1100 return;
1101 }
1102
1103 m_freem(rxq->rxq_curpkt);
1104 if ((sc->sc_flags & GE_NOFREE) == 0) {
1105 gfe_dmamem_free(sc, &rxq->rxq_desc_mem);
1106 gfe_dmamem_free(sc, &rxq->rxq_buf_mem);
1107 }
1108 GE_FUNC_EXIT(sc, "");
1109 }
1110
1111 void
gfe_rx_stop(struct gfe_softc * sc,enum gfe_whack_op op)1112 gfe_rx_stop(struct gfe_softc *sc, enum gfe_whack_op op)
1113 {
1114 GE_FUNC_ENTER(sc, "gfe_rx_stop");
1115 sc->sc_flags &= ~GE_RXACTIVE;
1116 sc->sc_idlemask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError);
1117 sc->sc_intrmask &= ~(ETH_IR_RxBits | ETH_IR_RxBuffer | ETH_IR_RxError);
1118 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1119 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_AR);
1120 do {
1121 delay(10);
1122 } while (GE_READ(sc, ETH_ESDCMR) & ETH_ESDCMR_AR);
1123 gfe_rx_cleanup(sc, GE_RXPRIO_HI);
1124 gfe_rx_cleanup(sc, GE_RXPRIO_MEDHI);
1125 gfe_rx_cleanup(sc, GE_RXPRIO_MEDLO);
1126 gfe_rx_cleanup(sc, GE_RXPRIO_LO);
1127 GE_FUNC_EXIT(sc, "");
1128 }
1129
1130 void
gfe_tick(void * arg)1131 gfe_tick(void *arg)
1132 {
1133 struct gfe_softc * const sc = arg;
1134 uint32_t intrmask;
1135 unsigned int tickflags;
1136 int s;
1137
1138 GE_FUNC_ENTER(sc, "gfe_tick");
1139
1140 s = splnet();
1141
1142 tickflags = sc->sc_tickflags;
1143 sc->sc_tickflags = 0;
1144 intrmask = sc->sc_intrmask;
1145 if (tickflags & GE_TICK_TX_IFSTART)
1146 gfe_ifstart(&sc->sc_ec.ec_if);
1147 if (tickflags & GE_TICK_RX_RESTART) {
1148 intrmask |= sc->sc_idlemask;
1149 if (sc->sc_idlemask & (ETH_IR_RxBuffer_3 | ETH_IR_RxError_3)) {
1150 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI];
1151 rxq->rxq_fi = 0;
1152 GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr);
1153 GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr);
1154 }
1155 if (sc->sc_idlemask & (ETH_IR_RxBuffer_2 | ETH_IR_RxError_2)) {
1156 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI];
1157 rxq->rxq_fi = 0;
1158 GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr);
1159 GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr);
1160 }
1161 if (sc->sc_idlemask & (ETH_IR_RxBuffer_1 | ETH_IR_RxError_1)) {
1162 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO];
1163 rxq->rxq_fi = 0;
1164 GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr);
1165 GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr);
1166 }
1167 if (sc->sc_idlemask & (ETH_IR_RxBuffer_0 | ETH_IR_RxError_0)) {
1168 struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO];
1169 rxq->rxq_fi = 0;
1170 GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr);
1171 GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr);
1172 }
1173 sc->sc_idlemask = 0;
1174 }
1175 if (intrmask != sc->sc_intrmask) {
1176 sc->sc_intrmask = intrmask;
1177 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1178 }
1179 gfe_intr(sc);
1180 splx(s);
1181
1182 GE_FUNC_EXIT(sc, "");
1183 }
1184
1185 int
gfe_tx_enqueue(struct gfe_softc * sc,enum gfe_txprio txprio)1186 gfe_tx_enqueue(struct gfe_softc *sc, enum gfe_txprio txprio)
1187 {
1188 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size;
1189 struct ifnet * const ifp = &sc->sc_ec.ec_if;
1190 struct gfe_txqueue * const txq = &sc->sc_txq[txprio];
1191 volatile struct gt_eth_desc * const txd = &txq->txq_descs[txq->txq_lo];
1192 uint32_t intrmask = sc->sc_intrmask;
1193 size_t buflen;
1194 struct mbuf *m;
1195
1196 GE_FUNC_ENTER(sc, "gfe_tx_enqueue");
1197
1198 /*
1199 * Anything in the pending queue to enqueue? if not, punt. Likewise
1200 * if the txq is not yet created.
1201 * otherwise grab its dmamap.
1202 */
1203 if (txq == NULL || (m = txq->txq_pendq.ifq_head) == NULL) {
1204 GE_FUNC_EXIT(sc, "-");
1205 return 0;
1206 }
1207
1208 /*
1209 * Have we [over]consumed our limit of descriptors?
1210 * Do we have enough free descriptors?
1211 */
1212 if (GE_TXDESC_MAX == txq->txq_nactive + 2) {
1213 volatile struct gt_eth_desc * const txd2 = &txq->txq_descs[txq->txq_fi];
1214 uint32_t cmdsts;
1215 size_t pktlen;
1216 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi);
1217 cmdsts = gt32toh(txd2->ed_cmdsts);
1218 if (cmdsts & TX_CMD_O) {
1219 int nextin;
1220 /*
1221 * Sometime the Discovery forgets to update the
1222 * last descriptor. See if we own the descriptor
1223 * after it (since we know we've turned that to
1224 * the discovery and if we owned it, the Discovery
1225 * gave it back). If we do, we know the Discovery
1226 * gave back this one but forgot to mark it as ours.
1227 */
1228 nextin = txq->txq_fi + 1;
1229 if (nextin == GE_TXDESC_MAX)
1230 nextin = 0;
1231 GE_TXDPOSTSYNC(sc, txq, nextin);
1232 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) {
1233 GE_TXDPRESYNC(sc, txq, txq->txq_fi);
1234 GE_TXDPRESYNC(sc, txq, nextin);
1235 GE_FUNC_EXIT(sc, "@");
1236 return 0;
1237 }
1238 #ifdef DEBUG
1239 printf("%s: txenqueue: transmitter resynced at %d\n",
1240 device_xname(sc->sc_dev), txq->txq_fi);
1241 #endif
1242 }
1243 if (++txq->txq_fi == GE_TXDESC_MAX)
1244 txq->txq_fi = 0;
1245 txq->txq_inptr = gt32toh(txd2->ed_bufptr) - txq->txq_buf_busaddr;
1246 pktlen = (gt32toh(txd2->ed_lencnt) >> 16) & 0xffff;
1247 txq->txq_inptr += roundup(pktlen, dcache_line_size);
1248 txq->txq_nactive--;
1249
1250 /* statistics */
1251 if_statinc(ifp, if_opackets);
1252 if (cmdsts & TX_STS_ES)
1253 if_statinc(ifp, if_oerrors);
1254 GE_DPRINTF(sc, ("%%"));
1255 }
1256
1257 buflen = roundup(m->m_pkthdr.len, dcache_line_size);
1258
1259 /*
1260 * If this packet would wrap around the end of the buffer, reset back
1261 * to the beginning.
1262 */
1263 if (txq->txq_outptr + buflen > GE_TXBUF_SIZE) {
1264 txq->txq_ei_gapcount += GE_TXBUF_SIZE - txq->txq_outptr;
1265 txq->txq_outptr = 0;
1266 }
1267
1268 /*
1269 * Make sure the output packet doesn't run over the beginning of
1270 * what we've already given the GT.
1271 */
1272 if (txq->txq_nactive > 0 && txq->txq_outptr <= txq->txq_inptr &&
1273 txq->txq_outptr + buflen > txq->txq_inptr) {
1274 intrmask |= txq->txq_intrbits &
1275 (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow);
1276 if (sc->sc_intrmask != intrmask) {
1277 sc->sc_intrmask = intrmask;
1278 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1279 }
1280 GE_FUNC_EXIT(sc, "#");
1281 return 0;
1282 }
1283
1284 /*
1285 * The end-of-list descriptor we put on last time is the starting point
1286 * for this packet. The GT is supposed to terminate list processing on
1287 * a NULL nxtptr but that currently is broken so a CPU-owned descriptor
1288 * must terminate the list.
1289 */
1290 intrmask = sc->sc_intrmask;
1291
1292 m_copydata(m, 0, m->m_pkthdr.len,
1293 (char *)txq->txq_buf_mem.gdm_kva + (int)txq->txq_outptr);
1294 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map,
1295 txq->txq_outptr, buflen, BUS_DMASYNC_PREWRITE);
1296 txd->ed_bufptr = htogt32(txq->txq_buf_busaddr + txq->txq_outptr);
1297 txd->ed_lencnt = htogt32(m->m_pkthdr.len << 16);
1298 GE_TXDPRESYNC(sc, txq, txq->txq_lo);
1299
1300 /*
1301 * Request a buffer interrupt every 2/3 of the way thru the transmit
1302 * buffer.
1303 */
1304 txq->txq_ei_gapcount += buflen;
1305 if (txq->txq_ei_gapcount > 2 * GE_TXBUF_SIZE / 3) {
1306 txd->ed_cmdsts = htogt32(TX_CMD_FIRST |TX_CMD_LAST |TX_CMD_EI);
1307 txq->txq_ei_gapcount = 0;
1308 } else {
1309 txd->ed_cmdsts = htogt32(TX_CMD_FIRST | TX_CMD_LAST);
1310 }
1311 #if 0
1312 GE_DPRINTF(sc, ("([%d]->%08lx.%08lx.%08lx.%08lx)", txq->txq_lo,
1313 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1],
1314 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3]));
1315 #endif
1316 GE_TXDPRESYNC(sc, txq, txq->txq_lo);
1317
1318 txq->txq_outptr += buflen;
1319 /*
1320 * Tell the SDMA engine to "Fetch!"
1321 */
1322 GE_WRITE(sc, ETH_ESDCMR,
1323 txq->txq_esdcmrbits & (ETH_ESDCMR_TXDH | ETH_ESDCMR_TXDL));
1324
1325 GE_DPRINTF(sc, ("(%d)", txq->txq_lo));
1326
1327 /*
1328 * Update the last out appropriately.
1329 */
1330 txq->txq_nactive++;
1331 if (++txq->txq_lo == GE_TXDESC_MAX)
1332 txq->txq_lo = 0;
1333
1334 /*
1335 * Move mbuf from the pending queue to the snd queue.
1336 */
1337 IF_DEQUEUE(&txq->txq_pendq, m);
1338 bpf_mtap(ifp, m, BPF_D_OUT);
1339 m_freem(m);
1340 ifp->if_flags &= ~IFF_OACTIVE;
1341
1342 /*
1343 * Since we have put an item into the packet queue, we now want
1344 * an interrupt when the transmit queue finishes processing the
1345 * list. But only update the mask if needs changing.
1346 */
1347 intrmask |= txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow);
1348 if (sc->sc_intrmask != intrmask) {
1349 sc->sc_intrmask = intrmask;
1350 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1351 }
1352 if (ifp->if_timer == 0)
1353 ifp->if_timer = 5;
1354 GE_FUNC_EXIT(sc, "*");
1355 return 1;
1356 }
1357
1358 uint32_t
gfe_tx_done(struct gfe_softc * sc,enum gfe_txprio txprio,uint32_t intrmask)1359 gfe_tx_done(struct gfe_softc *sc, enum gfe_txprio txprio, uint32_t intrmask)
1360 {
1361 struct gfe_txqueue * const txq = &sc->sc_txq[txprio];
1362 struct ifnet * const ifp = &sc->sc_ec.ec_if;
1363
1364 GE_FUNC_ENTER(sc, "gfe_tx_done");
1365
1366 if (txq == NULL) {
1367 GE_FUNC_EXIT(sc, "");
1368 return intrmask;
1369 }
1370
1371 while (txq->txq_nactive > 0) {
1372 const int dcache_line_size = curcpu()->ci_ci.dcache_line_size;
1373 volatile struct gt_eth_desc *txd = &txq->txq_descs[txq->txq_fi];
1374 uint32_t cmdsts;
1375 size_t pktlen;
1376
1377 GE_TXDPOSTSYNC(sc, txq, txq->txq_fi);
1378 if ((cmdsts = gt32toh(txd->ed_cmdsts)) & TX_CMD_O) {
1379 int nextin;
1380
1381 if (txq->txq_nactive == 1) {
1382 GE_TXDPRESYNC(sc, txq, txq->txq_fi);
1383 GE_FUNC_EXIT(sc, "");
1384 return intrmask;
1385 }
1386 /*
1387 * Sometimes the Discovery forgets to update the
1388 * ownership bit in the descriptor. See if we own the
1389 * descriptor after it (since we know we've turned
1390 * that to the Discovery and if we own it now then the
1391 * Discovery gave it back). If we do, we know the
1392 * Discovery gave back this one but forgot to mark it
1393 * as ours.
1394 */
1395 nextin = txq->txq_fi + 1;
1396 if (nextin == GE_TXDESC_MAX)
1397 nextin = 0;
1398 GE_TXDPOSTSYNC(sc, txq, nextin);
1399 if (gt32toh(txq->txq_descs[nextin].ed_cmdsts) & TX_CMD_O) {
1400 GE_TXDPRESYNC(sc, txq, txq->txq_fi);
1401 GE_TXDPRESYNC(sc, txq, nextin);
1402 GE_FUNC_EXIT(sc, "");
1403 return intrmask;
1404 }
1405 #ifdef DEBUG
1406 printf("%s: txdone: transmitter resynced at %d\n",
1407 device_xname(sc->sc_dev), txq->txq_fi);
1408 #endif
1409 }
1410 #if 0
1411 GE_DPRINTF(sc, ("([%d]<-%08lx.%08lx.%08lx.%08lx)",
1412 txq->txq_lo,
1413 ((unsigned long *)txd)[0], ((unsigned long *)txd)[1],
1414 ((unsigned long *)txd)[2], ((unsigned long *)txd)[3]));
1415 #endif
1416 GE_DPRINTF(sc, ("(%d)", txq->txq_fi));
1417 if (++txq->txq_fi == GE_TXDESC_MAX)
1418 txq->txq_fi = 0;
1419 txq->txq_inptr = gt32toh(txd->ed_bufptr) - txq->txq_buf_busaddr;
1420 pktlen = (gt32toh(txd->ed_lencnt) >> 16) & 0xffff;
1421 bus_dmamap_sync(sc->sc_dmat, txq->txq_buf_mem.gdm_map,
1422 txq->txq_inptr, pktlen, BUS_DMASYNC_POSTWRITE);
1423 txq->txq_inptr += roundup(pktlen, dcache_line_size);
1424
1425 /* statistics */
1426 if_statinc(ifp, if_opackets);
1427 if (cmdsts & TX_STS_ES)
1428 if_statinc(ifp, if_oerrors);
1429
1430 /* txd->ed_bufptr = 0; */
1431
1432 ifp->if_timer = 5;
1433 --txq->txq_nactive;
1434 }
1435 if (txq->txq_nactive != 0)
1436 panic("%s: transmit fifo%d empty but active count (%d) > 0!",
1437 device_xname(sc->sc_dev), txprio, txq->txq_nactive);
1438 ifp->if_timer = 0;
1439 intrmask &=
1440 ~(txq->txq_intrbits & (ETH_IR_TxEndHigh | ETH_IR_TxEndLow));
1441 intrmask &=
1442 ~(txq->txq_intrbits & (ETH_IR_TxBufferHigh | ETH_IR_TxBufferLow));
1443 GE_FUNC_EXIT(sc, "");
1444 return intrmask;
1445 }
1446
1447 int
gfe_tx_txqalloc(struct gfe_softc * sc,enum gfe_txprio txprio)1448 gfe_tx_txqalloc(struct gfe_softc *sc, enum gfe_txprio txprio)
1449 {
1450 struct gfe_txqueue * const txq = &sc->sc_txq[txprio];
1451 int error;
1452
1453 GE_FUNC_ENTER(sc, "gfe_tx_txqalloc");
1454
1455 error = gfe_dmamem_alloc(sc, &txq->txq_desc_mem, 1,
1456 GE_TXDESC_MEMSIZE, BUS_DMA_NOCACHE);
1457 if (error) {
1458 GE_FUNC_EXIT(sc, "");
1459 return error;
1460 }
1461 error = gfe_dmamem_alloc(sc, &txq->txq_buf_mem, 1, GE_TXBUF_SIZE, 0);
1462 if (error) {
1463 gfe_dmamem_free(sc, &txq->txq_desc_mem);
1464 GE_FUNC_EXIT(sc, "");
1465 return error;
1466 }
1467 GE_FUNC_EXIT(sc, "");
1468 return 0;
1469 }
1470
1471 int
gfe_tx_start(struct gfe_softc * sc,enum gfe_txprio txprio)1472 gfe_tx_start(struct gfe_softc *sc, enum gfe_txprio txprio)
1473 {
1474 struct gfe_txqueue * const txq = &sc->sc_txq[txprio];
1475 volatile struct gt_eth_desc *txd;
1476 unsigned int i;
1477 bus_addr_t addr;
1478
1479 GE_FUNC_ENTER(sc, "gfe_tx_start");
1480
1481 sc->sc_intrmask &=
1482 ~(ETH_IR_TxEndHigh |
1483 ETH_IR_TxBufferHigh |
1484 ETH_IR_TxEndLow |
1485 ETH_IR_TxBufferLow);
1486
1487 if (sc->sc_flags & GE_NOFREE) {
1488 KASSERT(txq->txq_desc_mem.gdm_kva != NULL);
1489 KASSERT(txq->txq_buf_mem.gdm_kva != NULL);
1490 } else {
1491 int error = gfe_tx_txqalloc(sc, txprio);
1492 if (error) {
1493 GE_FUNC_EXIT(sc, "!");
1494 return error;
1495 }
1496 }
1497
1498 txq->txq_descs =
1499 (volatile struct gt_eth_desc *) txq->txq_desc_mem.gdm_kva;
1500 txq->txq_desc_busaddr = txq->txq_desc_mem.gdm_map->dm_segs[0].ds_addr;
1501 txq->txq_buf_busaddr = txq->txq_buf_mem.gdm_map->dm_segs[0].ds_addr;
1502
1503 txq->txq_pendq.ifq_maxlen = 10;
1504 txq->txq_ei_gapcount = 0;
1505 txq->txq_nactive = 0;
1506 txq->txq_fi = 0;
1507 txq->txq_lo = 0;
1508 txq->txq_inptr = GE_TXBUF_SIZE;
1509 txq->txq_outptr = 0;
1510 for (i = 0, txd = txq->txq_descs,
1511 addr = txq->txq_desc_busaddr + sizeof(*txd);
1512 i < GE_TXDESC_MAX - 1; i++, txd++, addr += sizeof(*txd)) {
1513 /*
1514 * update the nxtptr to point to the next txd.
1515 */
1516 txd->ed_cmdsts = 0;
1517 txd->ed_nxtptr = htogt32(addr);
1518 }
1519 txq->txq_descs[GE_TXDESC_MAX-1].ed_nxtptr =
1520 htogt32(txq->txq_desc_busaddr);
1521 bus_dmamap_sync(sc->sc_dmat, txq->txq_desc_mem.gdm_map, 0,
1522 GE_TXDESC_MEMSIZE, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1523
1524 switch (txprio) {
1525 case GE_TXPRIO_HI:
1526 txq->txq_intrbits = ETH_IR_TxEndHigh | ETH_IR_TxBufferHigh;
1527 txq->txq_esdcmrbits = ETH_ESDCMR_TXDH;
1528 txq->txq_epsrbits = ETH_EPSR_TxHigh;
1529 txq->txq_ectdp = ETH_ECTDP1;
1530 GE_WRITE(sc, ETH_ECTDP1, txq->txq_desc_busaddr);
1531 break;
1532
1533 case GE_TXPRIO_LO:
1534 txq->txq_intrbits = ETH_IR_TxEndLow | ETH_IR_TxBufferLow;
1535 txq->txq_esdcmrbits = ETH_ESDCMR_TXDL;
1536 txq->txq_epsrbits = ETH_EPSR_TxLow;
1537 txq->txq_ectdp = ETH_ECTDP0;
1538 GE_WRITE(sc, ETH_ECTDP0, txq->txq_desc_busaddr);
1539 break;
1540
1541 case GE_TXPRIO_NONE:
1542 break;
1543 }
1544 #if 0
1545 GE_DPRINTF(sc, ("(ectdp=%#x", txq->txq_ectdp));
1546 GE_WRITE(sc->sc_dev, txq->txq_ectdp, txq->txq_desc_busaddr);
1547 GE_DPRINTF(sc, (")"));
1548 #endif
1549
1550 /*
1551 * If we are restarting, there may be packets in the pending queue
1552 * waiting to be enqueued. Try enqueuing packets from both priority
1553 * queues until the pending queue is empty or there no room for them
1554 * on the device.
1555 */
1556 while (gfe_tx_enqueue(sc, txprio))
1557 continue;
1558
1559 GE_FUNC_EXIT(sc, "");
1560 return 0;
1561 }
1562
1563 void
gfe_tx_cleanup(struct gfe_softc * sc,enum gfe_txprio txprio,int flush)1564 gfe_tx_cleanup(struct gfe_softc *sc, enum gfe_txprio txprio, int flush)
1565 {
1566 struct gfe_txqueue * const txq = &sc->sc_txq[txprio];
1567
1568 GE_FUNC_ENTER(sc, "gfe_tx_cleanup");
1569 if (txq == NULL) {
1570 GE_FUNC_EXIT(sc, "");
1571 return;
1572 }
1573
1574 if (!flush) {
1575 GE_FUNC_EXIT(sc, "");
1576 return;
1577 }
1578
1579 if ((sc->sc_flags & GE_NOFREE) == 0) {
1580 gfe_dmamem_free(sc, &txq->txq_desc_mem);
1581 gfe_dmamem_free(sc, &txq->txq_buf_mem);
1582 }
1583 GE_FUNC_EXIT(sc, "-F");
1584 }
1585
1586 void
gfe_tx_stop(struct gfe_softc * sc,enum gfe_whack_op op)1587 gfe_tx_stop(struct gfe_softc *sc, enum gfe_whack_op op)
1588 {
1589 GE_FUNC_ENTER(sc, "gfe_tx_stop");
1590
1591 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_STDH | ETH_ESDCMR_STDL);
1592
1593 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, sc->sc_intrmask);
1594 sc->sc_intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, sc->sc_intrmask);
1595 sc->sc_intrmask &=
1596 ~(ETH_IR_TxEndHigh |
1597 ETH_IR_TxBufferHigh |
1598 ETH_IR_TxEndLow |
1599 ETH_IR_TxBufferLow);
1600
1601 gfe_tx_cleanup(sc, GE_TXPRIO_HI, op == GE_WHACK_STOP);
1602 gfe_tx_cleanup(sc, GE_TXPRIO_LO, op == GE_WHACK_STOP);
1603
1604 sc->sc_ec.ec_if.if_timer = 0;
1605 GE_FUNC_EXIT(sc, "");
1606 }
1607
1608 int
gfe_intr(void * arg)1609 gfe_intr(void *arg)
1610 {
1611 struct gfe_softc * const sc = arg;
1612 uint32_t cause;
1613 uint32_t intrmask = sc->sc_intrmask;
1614 int claim = 0;
1615 int cnt;
1616
1617 GE_FUNC_ENTER(sc, "gfe_intr");
1618
1619 for (cnt = 0; cnt < 4; cnt++) {
1620 if (sc->sc_intrmask != intrmask) {
1621 sc->sc_intrmask = intrmask;
1622 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1623 }
1624 cause = GE_READ(sc, ETH_EICR);
1625 cause &= sc->sc_intrmask;
1626 GE_DPRINTF(sc, (".%#x", cause));
1627 if (cause == 0)
1628 break;
1629
1630 claim = 1;
1631
1632 GE_WRITE(sc, ETH_EICR, ~cause);
1633 #ifndef GE_NORX
1634 if (cause & (ETH_IR_RxBuffer | ETH_IR_RxError))
1635 intrmask = gfe_rx_process(sc, cause, intrmask);
1636 #endif
1637
1638 #ifndef GE_NOTX
1639 if (cause & (ETH_IR_TxBufferHigh | ETH_IR_TxEndHigh))
1640 intrmask = gfe_tx_done(sc, GE_TXPRIO_HI, intrmask);
1641 if (cause & (ETH_IR_TxBufferLow | ETH_IR_TxEndLow))
1642 intrmask = gfe_tx_done(sc, GE_TXPRIO_LO, intrmask);
1643 #endif
1644 if (cause & ETH_IR_MIIPhySTC) {
1645 sc->sc_flags |= GE_PHYSTSCHG;
1646 /* intrmask &= ~ETH_IR_MIIPhySTC; */
1647 }
1648 }
1649
1650 while (gfe_tx_enqueue(sc, GE_TXPRIO_HI))
1651 continue;
1652 while (gfe_tx_enqueue(sc, GE_TXPRIO_LO))
1653 continue;
1654
1655 GE_FUNC_EXIT(sc, "");
1656 return claim;
1657 }
1658
1659 int
gfe_whack(struct gfe_softc * sc,enum gfe_whack_op op)1660 gfe_whack(struct gfe_softc *sc, enum gfe_whack_op op)
1661 {
1662 int error = 0;
1663 GE_FUNC_ENTER(sc, "gfe_whack");
1664
1665 switch (op) {
1666 case GE_WHACK_RESTART:
1667 #ifndef GE_NOTX
1668 gfe_tx_stop(sc, op);
1669 #endif
1670 /* sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING; */
1671 /* FALLTHROUGH */
1672 case GE_WHACK_START:
1673 #ifndef GE_NOHASH
1674 if (error == 0 && sc->sc_hashtable == NULL) {
1675 error = gfe_hash_alloc(sc);
1676 if (error)
1677 break;
1678 }
1679 if (op != GE_WHACK_RESTART)
1680 gfe_hash_fill(sc);
1681 #endif
1682 #ifndef GE_NORX
1683 if (op != GE_WHACK_RESTART) {
1684 error = gfe_rx_prime(sc);
1685 if (error)
1686 break;
1687 }
1688 #endif
1689 #ifndef GE_NOTX
1690 error = gfe_tx_start(sc, GE_TXPRIO_HI);
1691 if (error)
1692 break;
1693 #endif
1694 sc->sc_ec.ec_if.if_flags |= IFF_RUNNING;
1695 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN);
1696 GE_WRITE(sc, ETH_EPCXR, sc->sc_pcxr);
1697 GE_WRITE(sc, ETH_EICR, 0);
1698 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1699 #ifndef GE_NOHASH
1700 GE_WRITE(sc, ETH_EHTPR,
1701 sc->sc_hash_mem.gdm_map->dm_segs->ds_addr);
1702 #endif
1703 #ifndef GE_NORX
1704 GE_WRITE(sc, ETH_ESDCMR, ETH_ESDCMR_ERD);
1705 sc->sc_flags |= GE_RXACTIVE;
1706 #endif
1707 /* FALLTHROUGH */
1708 case GE_WHACK_CHANGE:
1709 GE_DPRINTF(sc, ("(pcr=%#x,imr=%#x)",
1710 GE_READ(sc, ETH_EPCR), GE_READ(sc, ETH_EIMR)));
1711 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr | ETH_EPCR_EN);
1712 GE_WRITE(sc, ETH_EIMR, sc->sc_intrmask);
1713 gfe_ifstart(&sc->sc_ec.ec_if);
1714 GE_DPRINTF(sc, ("(ectdp0=%#x, ectdp1=%#x)",
1715 GE_READ(sc, ETH_ECTDP0), GE_READ(sc, ETH_ECTDP1)));
1716 GE_FUNC_EXIT(sc, "");
1717 return error;
1718 case GE_WHACK_STOP:
1719 break;
1720 }
1721
1722 #ifdef GE_DEBUG
1723 if (error)
1724 GE_DPRINTF(sc, (" failed: %d\n", error));
1725 #endif
1726 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr);
1727 GE_WRITE(sc, ETH_EIMR, 0);
1728 sc->sc_ec.ec_if.if_flags &= ~IFF_RUNNING;
1729 #ifndef GE_NOTX
1730 gfe_tx_stop(sc, GE_WHACK_STOP);
1731 #endif
1732 #ifndef GE_NORX
1733 gfe_rx_stop(sc, GE_WHACK_STOP);
1734 #endif
1735 #ifndef GE_NOHASH
1736 if ((sc->sc_flags & GE_NOFREE) == 0) {
1737 gfe_dmamem_free(sc, &sc->sc_hash_mem);
1738 sc->sc_hashtable = NULL;
1739 }
1740 #endif
1741
1742 GE_FUNC_EXIT(sc, "");
1743 return error;
1744 }
1745
1746 int
gfe_hash_compute(struct gfe_softc * sc,const uint8_t eaddr[ETHER_ADDR_LEN])1747 gfe_hash_compute(struct gfe_softc *sc, const uint8_t eaddr[ETHER_ADDR_LEN])
1748 {
1749 uint32_t w0, add0, add1;
1750 uint32_t result;
1751
1752 GE_FUNC_ENTER(sc, "gfe_hash_compute");
1753 add0 = ((uint32_t) eaddr[5] << 0) |
1754 ((uint32_t) eaddr[4] << 8) |
1755 ((uint32_t) eaddr[3] << 16);
1756
1757 add0 = ((add0 & 0x00f0f0f0) >> 4) | ((add0 & 0x000f0f0f) << 4);
1758 add0 = ((add0 & 0x00cccccc) >> 2) | ((add0 & 0x00333333) << 2);
1759 add0 = ((add0 & 0x00aaaaaa) >> 1) | ((add0 & 0x00555555) << 1);
1760
1761 add1 = ((uint32_t) eaddr[2] << 0) |
1762 ((uint32_t) eaddr[1] << 8) |
1763 ((uint32_t) eaddr[0] << 16);
1764
1765 add1 = ((add1 & 0x00f0f0f0) >> 4) | ((add1 & 0x000f0f0f) << 4);
1766 add1 = ((add1 & 0x00cccccc) >> 2) | ((add1 & 0x00333333) << 2);
1767 add1 = ((add1 & 0x00aaaaaa) >> 1) | ((add1 & 0x00555555) << 1);
1768
1769 GE_DPRINTF(sc, ("%s=", ether_sprintf(eaddr)));
1770 /*
1771 * hashResult is the 15 bits Hash entry address.
1772 * ethernetADD is a 48 bit number, which is derived from the Ethernet
1773 * MAC address, by nibble swapping in every byte (i.e MAC address
1774 * of 0x123456789abc translates to ethernetADD of 0x21436587a9cb).
1775 */
1776
1777 if ((sc->sc_pcr & ETH_EPCR_HM) == 0) {
1778 /*
1779 * hashResult[14:0] = hashFunc0(ethernetADD[47:0])
1780 *
1781 * hashFunc0 calculates the hashResult in the following manner:
1782 * hashResult[ 8:0] = ethernetADD[14:8,1,0]
1783 * XOR ethernetADD[23:15] XOR ethernetADD[32:24]
1784 */
1785 result = (add0 & 3) | ((add0 >> 6) & ~3);
1786 result ^= (add0 >> 15) ^ (add1 >> 0);
1787 result &= 0x1ff;
1788 /*
1789 * hashResult[14:9] = ethernetADD[7:2]
1790 */
1791 result |= (add0 & ~3) << 7; /* excess bits will be masked */
1792 GE_DPRINTF(sc, ("0(%#x)", result & 0x7fff));
1793 } else {
1794 #define TRIBITFLIP 073516240 /* yes its in octal */
1795 /*
1796 * hashResult[14:0] = hashFunc1(ethernetADD[47:0])
1797 *
1798 * hashFunc1 calculates the hashResult in the following manner:
1799 * hashResult[08:00] = ethernetADD[06:14]
1800 * XOR ethernetADD[15:23] XOR ethernetADD[24:32]
1801 */
1802 w0 = ((add0 >> 6) ^ (add0 >> 15) ^ (add1)) & 0x1ff;
1803 /*
1804 * Now bitswap those 9 bits
1805 */
1806 result = 0;
1807 result |= ((TRIBITFLIP >> (((w0 >> 0) & 7) * 3)) & 7) << 6;
1808 result |= ((TRIBITFLIP >> (((w0 >> 3) & 7) * 3)) & 7) << 3;
1809 result |= ((TRIBITFLIP >> (((w0 >> 6) & 7) * 3)) & 7) << 0;
1810
1811 /*
1812 * hashResult[14:09] = ethernetADD[00:05]
1813 */
1814 result |= ((TRIBITFLIP >> (((add0 >> 0) & 7) * 3)) & 7) << 12;
1815 result |= ((TRIBITFLIP >> (((add0 >> 3) & 7) * 3)) & 7) << 9;
1816 GE_DPRINTF(sc, ("1(%#x)", result));
1817 }
1818 GE_FUNC_EXIT(sc, "");
1819 return result & ((sc->sc_pcr & ETH_EPCR_HS_512) ? 0x7ff : 0x7fff);
1820 }
1821
1822 int
gfe_hash_entry_op(struct gfe_softc * sc,enum gfe_hash_op op,enum gfe_rxprio prio,const uint8_t eaddr[ETHER_ADDR_LEN])1823 gfe_hash_entry_op(struct gfe_softc *sc, enum gfe_hash_op op,
1824 enum gfe_rxprio prio, const uint8_t eaddr[ETHER_ADDR_LEN])
1825 {
1826 uint64_t he;
1827 uint64_t *maybe_he_p = NULL;
1828 int limit;
1829 int hash;
1830 int maybe_hash = 0;
1831
1832 GE_FUNC_ENTER(sc, "gfe_hash_entry_op");
1833
1834 hash = gfe_hash_compute(sc, eaddr);
1835
1836 if (sc->sc_hashtable == NULL) {
1837 panic("%s:%d: hashtable == NULL!", device_xname(sc->sc_dev),
1838 __LINE__);
1839 }
1840
1841 /*
1842 * Assume we are going to insert so create the hash entry we
1843 * are going to insert. We also use it to match entries we
1844 * will be removing.
1845 */
1846 he = ((uint64_t) eaddr[5] << 43) |
1847 ((uint64_t) eaddr[4] << 35) |
1848 ((uint64_t) eaddr[3] << 27) |
1849 ((uint64_t) eaddr[2] << 19) |
1850 ((uint64_t) eaddr[1] << 11) |
1851 ((uint64_t) eaddr[0] << 3) |
1852 HSH_PRIO_INS(prio) | HSH_V | HSH_R;
1853
1854 /*
1855 * The GT will search upto 12 entries for a hit, so we must mimic that.
1856 */
1857 hash &= sc->sc_hashmask / sizeof(he);
1858 for (limit = HSH_LIMIT; limit > 0 ; --limit) {
1859 /*
1860 * Does the GT wrap at the end, stop at the, or overrun the
1861 * end? Assume it wraps for now. Stash a copy of the
1862 * current hash entry.
1863 */
1864 uint64_t *he_p = &sc->sc_hashtable[hash];
1865 uint64_t thishe = *he_p;
1866
1867 /*
1868 * If the hash entry isn't valid, that break the chain. And
1869 * this entry a good candidate for reuse.
1870 */
1871 if ((thishe & HSH_V) == 0) {
1872 maybe_he_p = he_p;
1873 break;
1874 }
1875
1876 /*
1877 * If the hash entry has the same address we are looking for
1878 * then ... if we are removing and the skip bit is set, its
1879 * already been removed. if are adding and the skip bit is
1880 * clear, then its already added. In either return EBUSY
1881 * indicating the op has already been done. Otherwise flip
1882 * the skip bit and return 0.
1883 */
1884 if (((he ^ thishe) & HSH_ADDR_MASK) == 0) {
1885 if (((op == GE_HASH_REMOVE) && (thishe & HSH_S)) ||
1886 ((op == GE_HASH_ADD) && (thishe & HSH_S) == 0))
1887 return EBUSY;
1888 *he_p = thishe ^ HSH_S;
1889 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map,
1890 hash * sizeof(he), sizeof(he),
1891 BUS_DMASYNC_PREWRITE);
1892 GE_FUNC_EXIT(sc, "^");
1893 return 0;
1894 }
1895
1896 /*
1897 * If we haven't found a slot for the entry and this entry
1898 * is currently being skipped, return this entry.
1899 */
1900 if (maybe_he_p == NULL && (thishe & HSH_S)) {
1901 maybe_he_p = he_p;
1902 maybe_hash = hash;
1903 }
1904
1905 hash = (hash + 1) & (sc->sc_hashmask / sizeof(he));
1906 }
1907
1908 /*
1909 * If we got here, then there was no entry to remove.
1910 */
1911 if (op == GE_HASH_REMOVE) {
1912 GE_FUNC_EXIT(sc, "?");
1913 return ENOENT;
1914 }
1915
1916 /*
1917 * If we couldn't find a slot, return an error.
1918 */
1919 if (maybe_he_p == NULL) {
1920 GE_FUNC_EXIT(sc, "!");
1921 return ENOSPC;
1922 }
1923
1924 /* Update the entry.
1925 */
1926 *maybe_he_p = he;
1927 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map,
1928 maybe_hash * sizeof(he), sizeof(he), BUS_DMASYNC_PREWRITE);
1929 GE_FUNC_EXIT(sc, "+");
1930 return 0;
1931 }
1932
1933 int
gfe_hash_multichg(struct ethercom * ec,const struct ether_multi * enm,u_long cmd)1934 gfe_hash_multichg(struct ethercom *ec, const struct ether_multi *enm,
1935 u_long cmd)
1936 {
1937 struct gfe_softc *sc = ec->ec_if.if_softc;
1938 int error;
1939 enum gfe_hash_op op;
1940 enum gfe_rxprio prio;
1941
1942 GE_FUNC_ENTER(sc, "hash_multichg");
1943 /*
1944 * Is this a wildcard entry? If so and its being removed, recompute.
1945 */
1946 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) {
1947 if (cmd == SIOCDELMULTI) {
1948 GE_FUNC_EXIT(sc, "");
1949 return ENETRESET;
1950 }
1951
1952 /*
1953 * Switch in
1954 */
1955 sc->sc_flags |= GE_ALLMULTI;
1956 if ((sc->sc_pcr & ETH_EPCR_PM) == 0) {
1957 sc->sc_pcr |= ETH_EPCR_PM;
1958 GE_WRITE(sc, ETH_EPCR, sc->sc_pcr);
1959 GE_FUNC_EXIT(sc, "");
1960 return 0;
1961 }
1962 GE_FUNC_EXIT(sc, "");
1963 return ENETRESET;
1964 }
1965
1966 prio = GE_RXPRIO_MEDLO;
1967 op = (cmd == SIOCDELMULTI ? GE_HASH_REMOVE : GE_HASH_ADD);
1968
1969 if (sc->sc_hashtable == NULL) {
1970 GE_FUNC_EXIT(sc, "");
1971 return 0;
1972 }
1973
1974 error = gfe_hash_entry_op(sc, op, prio, enm->enm_addrlo);
1975 if (error == EBUSY) {
1976 aprint_error_dev(sc->sc_dev, "multichg: tried to %s %s again\n",
1977 cmd == SIOCDELMULTI ? "remove" : "add",
1978 ether_sprintf(enm->enm_addrlo));
1979 GE_FUNC_EXIT(sc, "");
1980 return 0;
1981 }
1982
1983 if (error == ENOENT) {
1984 aprint_error_dev(sc->sc_dev,
1985 "multichg: failed to remove %s: not in table\n",
1986 ether_sprintf(enm->enm_addrlo));
1987 GE_FUNC_EXIT(sc, "");
1988 return 0;
1989 }
1990
1991 if (error == ENOSPC) {
1992 aprint_error_dev(sc->sc_dev, "multichg:"
1993 " failed to add %s: no space; regenerating table\n",
1994 ether_sprintf(enm->enm_addrlo));
1995 GE_FUNC_EXIT(sc, "");
1996 return ENETRESET;
1997 }
1998 GE_DPRINTF(sc, ("%s: multichg: %s: %s succeeded\n",
1999 device_xname(sc->sc_dev),
2000 cmd == SIOCDELMULTI ? "remove" : "add",
2001 ether_sprintf(enm->enm_addrlo)));
2002 GE_FUNC_EXIT(sc, "");
2003 return 0;
2004 }
2005
2006 int
gfe_hash_fill(struct gfe_softc * sc)2007 gfe_hash_fill(struct gfe_softc *sc)
2008 {
2009 struct ethercom *ec = &sc->sc_ec;
2010 struct ether_multistep step;
2011 struct ether_multi *enm;
2012 int error;
2013
2014 GE_FUNC_ENTER(sc, "gfe_hash_fill");
2015
2016 error = gfe_hash_entry_op(sc, GE_HASH_ADD, GE_RXPRIO_HI,
2017 CLLADDR(ec->ec_if.if_sadl));
2018 if (error) {
2019 GE_FUNC_EXIT(sc, "!");
2020 return error;
2021 }
2022
2023 sc->sc_flags &= ~GE_ALLMULTI;
2024 if ((ec->ec_if.if_flags & IFF_PROMISC) == 0)
2025 sc->sc_pcr &= ~ETH_EPCR_PM;
2026 ETHER_LOCK(ec);
2027 ETHER_FIRST_MULTI(step, ec, enm);
2028 while (enm != NULL) {
2029 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
2030 sc->sc_flags |= GE_ALLMULTI;
2031 sc->sc_pcr |= ETH_EPCR_PM;
2032 } else {
2033 error = gfe_hash_entry_op(sc, GE_HASH_ADD,
2034 GE_RXPRIO_MEDLO, enm->enm_addrlo);
2035 if (error == ENOSPC)
2036 break;
2037 }
2038 ETHER_NEXT_MULTI(step, enm);
2039 }
2040 ETHER_UNLOCK(ec);
2041
2042 GE_FUNC_EXIT(sc, "");
2043 return error;
2044 }
2045
2046 int
gfe_hash_alloc(struct gfe_softc * sc)2047 gfe_hash_alloc(struct gfe_softc *sc)
2048 {
2049 int error;
2050 GE_FUNC_ENTER(sc, "gfe_hash_alloc");
2051 sc->sc_hashmask = (sc->sc_pcr & ETH_EPCR_HS_512 ? 16 : 256)*1024 - 1;
2052 error = gfe_dmamem_alloc(sc, &sc->sc_hash_mem, 1, sc->sc_hashmask + 1,
2053 BUS_DMA_NOCACHE);
2054 if (error) {
2055 aprint_error_dev(sc->sc_dev,
2056 "failed to allocate %d bytes for hash table: %d\n",
2057 sc->sc_hashmask + 1, error);
2058 GE_FUNC_EXIT(sc, "");
2059 return error;
2060 }
2061 sc->sc_hashtable = (uint64_t *) sc->sc_hash_mem.gdm_kva;
2062 memset(sc->sc_hashtable, 0, sc->sc_hashmask + 1);
2063 bus_dmamap_sync(sc->sc_dmat, sc->sc_hash_mem.gdm_map,
2064 0, sc->sc_hashmask + 1, BUS_DMASYNC_PREWRITE);
2065 GE_FUNC_EXIT(sc, "");
2066 return 0;
2067 }
2068