1 /* $NetBSD: acphyreg.h,v 1.2 2001/08/25 05:57:12 thorpej Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _DEV_MII_ACPHYREG_H_ 39 #define _DEV_MII_ACPHYREG_H_ 40 41 /* 42 * Altima AC101 PHY registers. 43 * 44 * Note the AC101 and the AMD Ac79c874 are the same PHY core. There 45 * are some registers documented in the AC101 manual that are not in 46 * the Am79c874 manual, and vice-versa. I have no idea how to tell 47 * the two apart, but we don't really use the registers that fall into 48 * this category, anyhow. 49 */ 50 51 #define MII_ACPHY_PILR 0x10 /* polarity and interrupt control */ 52 #define PILR_REPEATER 0x8000 /* repeater mode */ 53 #define PILR_INTR_LEVL 0x4000 /* 1 = active high, 0 = active low */ 54 #define PILR_SQE_INHIBIT 0x0800 /* disable 10T SQE testing */ 55 #define PILR_10T_LOOP 0x0400 /* enable loopback in 10T */ 56 #define PILR_GPIO1_DATA 0x0200 /* GPIO1 pin */ 57 #define PILR_GPIO1_DIR 0x0100 /* 1 = input */ 58 #define PILR_GPIO0_DATA 0x0080 /* GPIO0 pin */ 59 #define PILR_GPIO0_DIR 0x0040 /* 1 = input */ 60 #define PILR_AUTO_POL_DIS 0x0020 /* disable auto-polarity */ 61 #define PILR_REVERSE_POL 0x0010 /* 1 = reverse, 0 = normal */ 62 #define PILR_RXCLK_CTRL 0x0001 /* disable RX_CLK when idle */ 63 64 65 #define MII_ACPHY_ICSR 0x11 /* interrupt control/status */ 66 #define ICSR_JABBER_IE 0x8000 /* jabber interrupt enable */ 67 #define ICSR_RX_ER_IE 0x4000 /* Rx error interrupt enable */ 68 #define ICSR_PAGE_RX_IE 0x2000 /* page received interrupt enable */ 69 #define ICSR_PD_FAULT_IE 0x1000 /* parallel detection fault int en */ 70 #define ICSR_LP_ACK_IE 0x0800 /* link partner ACK interrupt en */ 71 #define ICSR_LNK_NOT_OK_IE 0x0400 /* link not okay interrupt enable */ 72 #define ICSR_R_FAULT_IE 0x0200 /* remote fault interrupt enable */ 73 #define ICSR_ANEG_COMP_IE 0x0100 /* autonegotiation complete int en */ 74 #define ICSR_JABBER_INT 0x0080 /* jabber interrupt */ 75 #define ICSR_RX_ER_INT 0x0040 /* Rx error interrupt */ 76 #define ICSR_PAGE_RX_INT 0x0020 /* page received interrupt */ 77 #define ICSR_PD_FAULT_INT 0x0010 /* parallel detection fault interrupt */ 78 #define ICSR_LP_ACK_INT 0x0008 /* link partner ACK interrupt */ 79 #define ICSR_LNK_NOT_OK_INT 0x0004 /* link not okay interrupt */ 80 #define ICSR_R_FAULT_INT 0x0002 /* remote fault interrupt */ 81 #define ICSR_ANEG_COMP_INT 0x0001 /* autonegotiation complete interrupt */ 82 83 84 #define MII_ACPHY_DR 0x12 /* diagnostic register */ 85 #define DR_DPLX 0x0800 /* full-duplex resolved */ 86 #define DR_SPEED 0x0400 /* 100BASE-TX resolved */ 87 #define DR_RX_PASS 0x0200 /* manchester/signal received */ 88 #define DR_RX_LOCK 0x0100 /* PLL signal has been locked */ 89 90 91 #define MII_ACPHY_PLR 0x13 /* power/loopback register */ 92 #define PLR_TB125 0x0040 /* Tx transformer ratio 1.25:1 */ 93 #define PLR_LOW_POWER_MODE 0x0020 /* enable advanced power saving mode */ 94 #define PLR_TEST_LOOPBACK 0x0010 /* enable test loopback */ 95 #define PLR_DIGITAL_LOOPBACK 0x0008 /* enable loopback */ 96 #define PLR_LP_LPBK 0x0004 /* enable link pulse loopback */ 97 #define PLR_NLP_LINK_INT_TEST 0x0002 /* send NLP instead of FLP */ 98 #define PLR_REDUCE_TIMER 0x0001 /* reduce time constant for aneg */ 99 100 101 /* AC101 only */ 102 #define MII_ACPHY_CMR 0x14 /* cable measurement register */ 103 #define CMR_MASK 0x00f0 /* cable measurement mask */ 104 105 106 #define MII_ACPHY_MCR 0x15 /* mode control register */ 107 #define MCR_NLP_DISABLE 0x4000 /* force good 10BASE-T link */ 108 #define MCR_FORCE_LINK_UP 0x2000 /* force good 100BASE-TX link */ 109 #define MCR_JABBER_DISABLE 0x1000 /* disable jabber function */ 110 #define MCR_10BT_SEL 0x0800 /* enable 7-wire 10T operation */ 111 #define MCR_CONF_ALED 0x0400 /* 1 = ALED only Rx, 0 = ALED Rx/Tx */ 112 #define MCR_LED_SEL 0x0200 /* 1 = tqphy-compat LED config */ 113 #define MCR_FEF_DIS 0x0100 /* disable far-end-fault insertion */ 114 #define MCR_FORCE_FEF_TX 0x0080 /* force FEF transmission */ 115 #define MCR_RX_ER_CNT_FULL 0x0040 /* Rx error counter full */ 116 #define MCR_DIS_RX_ER_CNT 0x0020 /* disable Rx error counter */ 117 #define MCR_DIS_WDT 0x0010 /* disable the watchdog timer */ 118 #define MCR_EN_RPBK 0x0008 /* enable remote loopback */ 119 #define MCR_DIS_SCRM 0x0004 /* enable 100M data scrambling */ 120 #define MCR_PCSBP 0x0002 /* bypass PCS */ 121 #define MCR_FX_SEL 0x0001 /* FX mode selected */ 122 123 124 /* Am79c874 only */ 125 #define MII_ACPHY_DCR 0x17 /* disconnect counter register */ 126 127 128 #define MII_ACPHY_RECR 0x18 /* receive error counter register */ 129 130 131 #endif /* _DEV_MII_ACPHYREG_H_ */ 132