1 /* $NetBSD: if_lii.c,v 1.30 2024/02/09 22:08:36 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2008 The NetBSD Foundation.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Driver for Attansic/Atheros's L2 Fast Ethernet controller
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: if_lii.c,v 1.30 2024/02/09 22:08:36 andvar Exp $");
35
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/types.h>
40 #include <sys/device.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/sockio.h>
44
45 #include <net/if.h>
46 #include <net/if_media.h>
47 #include <net/if_ether.h>
48
49 #include <net/bpf.h>
50
51 #include <dev/mii/mii.h>
52 #include <dev/mii/miivar.h>
53
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcidevs.h>
57
58 #include <dev/pci/if_liireg.h>
59
60 /* #define LII_DEBUG */
61 #ifdef LII_DEBUG
62 #define DPRINTF(x) printf x
63 #else
64 #define DPRINTF(x)
65 #endif
66
67 struct lii_softc {
68 device_t sc_dev;
69 pci_chipset_tag_t sc_pc;
70 pcitag_t sc_tag;
71
72 bus_space_tag_t sc_mmiot;
73 bus_space_handle_t sc_mmioh;
74
75 /*
76 * We allocate a big chunk of DMA-safe memory for all data exchanges.
77 * It is unfortunate that this chip doesn't seem to do scatter-gather.
78 */
79 bus_dma_tag_t sc_dmat;
80 bus_dmamap_t sc_ringmap;
81 bus_dma_segment_t sc_ringseg;
82
83 uint8_t *sc_ring; /* the whole area */
84 size_t sc_ringsize;
85
86 struct rx_pkt *sc_rxp; /* the part used for RX */
87 struct tx_pkt_status *sc_txs; /* the parts used for TX */
88 bus_addr_t sc_txsp;
89 char *sc_txdbase;
90 bus_addr_t sc_txdp;
91
92 unsigned int sc_rxcur;
93 /* the active area is [ack; cur[ */
94 int sc_txs_cur;
95 int sc_txs_ack;
96 int sc_txd_cur;
97 int sc_txd_ack;
98 bool sc_free_tx_slots;
99
100 void *sc_ih;
101
102 struct ethercom sc_ec;
103 struct mii_data sc_mii;
104 callout_t sc_tick_ch;
105 uint8_t sc_eaddr[ETHER_ADDR_LEN];
106
107 int (*sc_memread)(struct lii_softc *, uint32_t,
108 uint32_t *);
109 };
110
111 static int lii_match(device_t, cfdata_t, void *);
112 static void lii_attach(device_t, device_t, void *);
113
114 static int lii_reset(struct lii_softc *);
115 static bool lii_eeprom_present(struct lii_softc *);
116 static int lii_read_macaddr(struct lii_softc *, uint8_t *);
117 static int lii_eeprom_read(struct lii_softc *, uint32_t, uint32_t *);
118 static void lii_spi_configure(struct lii_softc *);
119 static int lii_spi_read(struct lii_softc *, uint32_t, uint32_t *);
120 static void lii_setmulti(struct lii_softc *);
121 static void lii_tick(void *);
122
123 static int lii_alloc_rings(struct lii_softc *);
124 static int lii_free_tx_space(struct lii_softc *);
125
126 static int lii_mii_readreg(device_t, int, int, uint16_t *);
127 static int lii_mii_writereg(device_t, int, int, uint16_t);
128 static void lii_mii_statchg(struct ifnet *);
129
130 static int lii_media_change(struct ifnet *);
131 static void lii_media_status(struct ifnet *, struct ifmediareq *);
132
133 static int lii_init(struct ifnet *);
134 static void lii_start(struct ifnet *);
135 static void lii_stop(struct ifnet *, int);
136 static void lii_watchdog(struct ifnet *);
137 static int lii_ioctl(struct ifnet *, u_long, void *);
138
139 static int lii_intr(void *);
140 static void lii_rxintr(struct lii_softc *);
141 static void lii_txintr(struct lii_softc *);
142
143 CFATTACH_DECL_NEW(lii, sizeof(struct lii_softc),
144 lii_match, lii_attach, NULL, NULL);
145
146 /* #define LII_DEBUG_REGS */
147 #ifndef LII_DEBUG_REGS
148 #define AT_READ_4(sc, reg) \
149 bus_space_read_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
150 #define AT_READ_2(sc, reg) \
151 bus_space_read_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
152 #define AT_READ_1(sc, reg) \
153 bus_space_read_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg))
154 #define AT_WRITE_4(sc, reg, val) \
155 bus_space_write_4((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
156 #define AT_WRITE_2(sc, reg, val) \
157 bus_space_write_2((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
158 #define AT_WRITE_1(sc, reg, val) \
159 bus_space_write_1((sc)->sc_mmiot, (sc)->sc_mmioh, (reg), (val))
160 #else
161 static inline uint32_t
AT_READ_4(struct lii_softc * sc,bus_size_t reg)162 AT_READ_4(struct lii_softc *sc, bus_size_t reg)
163 {
164 uint32_t r = bus_space_read_4(sc->sc_mmiot, sc->sc_mmioh, reg);
165 printf("AT_READ_4(%x) = %x\n", (unsigned int)reg, r);
166 return r;
167 }
168
169 static inline uint16_t
AT_READ_2(struct lii_softc * sc,bus_size_t reg)170 AT_READ_2(struct lii_softc *sc, bus_size_t reg)
171 {
172 uint16_t r = bus_space_read_2(sc->sc_mmiot, sc->sc_mmioh, reg);
173 printf("AT_READ_2(%x) = %x\n", (unsigned int)reg, r);
174 return r;
175 }
176
177 static inline uint8_t
AT_READ_1(struct lii_softc * sc,bus_size_t reg)178 AT_READ_1(struct lii_softc *sc, bus_size_t reg)
179 {
180 uint8_t r = bus_space_read_1(sc->sc_mmiot, sc->sc_mmioh, reg);
181 printf("AT_READ_1(%x) = %x\n", (unsigned int)reg, r);
182 return r;
183 }
184
185 static inline void
AT_WRITE_4(struct lii_softc * sc,bus_size_t reg,uint32_t val)186 AT_WRITE_4(struct lii_softc *sc, bus_size_t reg, uint32_t val)
187 {
188 printf("AT_WRITE_4(%x, %x)\n", (unsigned int)reg, val);
189 bus_space_write_4(sc->sc_mmiot, sc->sc_mmioh, reg, val);
190 }
191
192 static inline void
AT_WRITE_2(struct lii_softc * sc,bus_size_t reg,uint16_t val)193 AT_WRITE_2(struct lii_softc *sc, bus_size_t reg, uint16_t val)
194 {
195 printf("AT_WRITE_2(%x, %x)\n", (unsigned int)reg, val);
196 bus_space_write_2(sc->sc_mmiot, sc->sc_mmioh, reg, val);
197 }
198
199 static inline void
AT_WRITE_1(struct lii_softc * sc,bus_size_t reg,uint8_t val)200 AT_WRITE_1(struct lii_softc *sc, bus_size_t reg, uint8_t val)
201 {
202 printf("AT_WRITE_1(%x, %x)\n", (unsigned int)reg, val);
203 bus_space_write_1(sc->sc_mmiot, sc->sc_mmioh, reg, val);
204 }
205 #endif
206
207 /*
208 * Those are the default Linux parameters.
209 */
210
211 #define AT_TXD_NUM 64
212 #define AT_TXD_BUFFER_SIZE 8192
213 #define AT_RXD_NUM 64
214
215 /*
216 * Assuming (you know what that word makes of you) the chunk of memory
217 * bus_dmamem_alloc returns us is 128-byte aligned, we won't use the
218 * first 120 bytes of it, so that the space for the packets, and not the
219 * whole descriptors themselves, are on a 128-byte boundary.
220 */
221
222 #define AT_RXD_PADDING 120
223
224 static int
lii_match(device_t parent,cfdata_t cfmatch,void * aux)225 lii_match(device_t parent, cfdata_t cfmatch, void *aux)
226 {
227 struct pci_attach_args *pa = aux;
228
229 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATTANSIC &&
230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATTANSIC_ETHERNET_100);
231 }
232
233 static void
lii_attach(device_t parent,device_t self,void * aux)234 lii_attach(device_t parent, device_t self, void *aux)
235 {
236 struct lii_softc *sc = device_private(self);
237 struct pci_attach_args *pa = aux;
238 uint8_t eaddr[ETHER_ADDR_LEN];
239 struct ifnet *ifp = &sc->sc_ec.ec_if;
240 struct mii_data *mii = &sc->sc_mii;
241 pci_intr_handle_t ih;
242 const char *intrstr;
243 pcireg_t cmd;
244 bus_size_t memsize = 0;
245 char intrbuf[PCI_INTRSTR_LEN];
246
247 aprint_naive("\n");
248 aprint_normal(": Attansic/Atheros L2 Fast Ethernet\n");
249
250 sc->sc_dev = self;
251 sc->sc_pc = pa->pa_pc;
252 sc->sc_tag = pa->pa_tag;
253 sc->sc_dmat = pa->pa_dmat;
254
255 cmd = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
256 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
257 cmd &= ~PCI_COMMAND_IO_ENABLE;
258 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmd);
259
260 switch (cmd = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START)) {
261 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
262 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M:
263 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
264 break;
265 default:
266 aprint_error_dev(self, "invalid base address register\n");
267 break;
268 }
269 if (pci_mapreg_map(pa, PCI_MAPREG_START, cmd, 0,
270 &sc->sc_mmiot, &sc->sc_mmioh, NULL, &memsize) != 0) {
271 aprint_error_dev(self, "failed to map registers\n");
272 return;
273 }
274
275 if (lii_reset(sc))
276 return;
277
278 lii_spi_configure(sc);
279
280 if (lii_eeprom_present(sc))
281 sc->sc_memread = lii_eeprom_read;
282 else
283 sc->sc_memread = lii_spi_read;
284
285 if (lii_read_macaddr(sc, eaddr))
286 return;
287 memcpy(sc->sc_eaddr, eaddr, ETHER_ADDR_LEN);
288
289 aprint_normal_dev(self, "Ethernet address %s\n",
290 ether_sprintf(eaddr));
291
292 if (pci_intr_map(pa, &ih) != 0) {
293 aprint_error_dev(self, "failed to map interrupt\n");
294 goto fail;
295 }
296 intrstr = pci_intr_string(sc->sc_pc, ih, intrbuf, sizeof(intrbuf));
297 sc->sc_ih = pci_intr_establish_xname(sc->sc_pc, ih, IPL_NET, lii_intr,
298 sc, device_xname(self));
299 if (sc->sc_ih == NULL) {
300 aprint_error_dev(self, "failed to establish interrupt");
301 if (intrstr != NULL)
302 aprint_error(" at %s", intrstr);
303 aprint_error("\n");
304 goto fail;
305 }
306 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
307
308 if (lii_alloc_rings(sc))
309 goto fail;
310
311 callout_init(&sc->sc_tick_ch, 0);
312 callout_setfunc(&sc->sc_tick_ch, lii_tick, sc);
313
314 mii->mii_ifp = ifp;
315 mii->mii_readreg = lii_mii_readreg;
316 mii->mii_writereg = lii_mii_writereg;
317 mii->mii_statchg = lii_mii_statchg;
318 sc->sc_ec.ec_mii = mii;
319 ifmedia_init(&mii->mii_media, IFM_IMASK, lii_media_change,
320 lii_media_status);
321 mii_attach(sc->sc_dev, mii, 0xffffffff, 1, MII_OFFSET_ANY, 0);
322 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
323
324 strlcpy(ifp->if_xname, device_xname(self), IFNAMSIZ);
325 ifp->if_softc = sc;
326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
327 ifp->if_ioctl = lii_ioctl;
328 ifp->if_start = lii_start;
329 ifp->if_watchdog = lii_watchdog;
330 ifp->if_init = lii_init;
331 ifp->if_stop = lii_stop;
332 IFQ_SET_READY(&ifp->if_snd);
333
334 /*
335 * While the device does support HW VLAN tagging, there is no
336 * real point using that feature.
337 */
338 sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU;
339
340 if_attach(ifp);
341 if_deferred_start_init(ifp, NULL);
342 ether_ifattach(ifp, eaddr);
343
344 if (pmf_device_register(self, NULL, NULL))
345 pmf_class_network_register(self, ifp);
346 else
347 aprint_error_dev(self, "couldn't establish power handler\n");
348
349 return;
350
351 fail:
352 if (sc->sc_ih != NULL) {
353 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
354 sc->sc_ih = NULL;
355 }
356 if (memsize)
357 bus_space_unmap(sc->sc_mmiot, sc->sc_mmioh, memsize);
358 }
359
360 static int
lii_reset(struct lii_softc * sc)361 lii_reset(struct lii_softc *sc)
362 {
363 int i;
364
365 DPRINTF(("lii_reset\n"));
366
367 AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST);
368 DELAY(1000);
369
370 for (i = 0; i < 10; ++i) {
371 if (AT_READ_4(sc, ATL2_BIS) == 0)
372 break;
373 DELAY(1000);
374 }
375
376 if (i == 10) {
377 aprint_error_dev(sc->sc_dev, "reset failed\n");
378 return 1;
379 }
380
381 AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE);
382 DELAY(10);
383
384 /* Init PCI-Express module */
385 /* Magic Numbers Warning */
386 AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF);
387 AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF);
388
389 return 0;
390 }
391
392 static bool
lii_eeprom_present(struct lii_softc * sc)393 lii_eeprom_present(struct lii_softc *sc)
394 {
395 /*
396 * The Linux driver does this, but then it has a very weird way of
397 * checking whether the PCI configuration space exposes the Vital
398 * Product Data capability, so maybe it's not really needed.
399 */
400
401 #ifdef weirdloonix
402 uint32_t val;
403
404 val = AT_READ_4(sc, ATL2_SFC);
405 if (val & SFC_EN_VPD)
406 AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD));
407 #endif
408
409 return pci_get_capability(sc->sc_pc, sc->sc_tag, PCI_CAP_VPD,
410 NULL, NULL) == 1;
411 }
412
413 static int
lii_eeprom_read(struct lii_softc * sc,uint32_t reg,uint32_t * val)414 lii_eeprom_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
415 {
416 int r = pci_vpd_read(sc->sc_pc, sc->sc_tag, reg, 1, (pcireg_t *)val);
417
418 DPRINTF(("lii_eeprom_read(%x) = %x\n", reg, *val));
419
420 return r;
421 }
422
423 static void
lii_spi_configure(struct lii_softc * sc)424 lii_spi_configure(struct lii_softc *sc)
425 {
426 /*
427 * We don't offer a way to configure the SPI Flash vendor parameter, so
428 * the table is given for reference
429 */
430 static const struct lii_spi_flash_vendor {
431 const char *sfv_name;
432 const uint8_t sfv_opcodes[9];
433 } lii_sfv[] = {
434 { "Atmel", { 0x00, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 } },
435 { "SST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 } },
436 { "ST", { 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xab, 0xd8, 0xc7 } },
437 };
438 #define SF_OPCODE_WRSR 0
439 #define SF_OPCODE_READ 1
440 #define SF_OPCODE_PRGM 2
441 #define SF_OPCODE_WREN 3
442 #define SF_OPCODE_WRDI 4
443 #define SF_OPCODE_RDSR 5
444 #define SF_OPCODE_RDID 6
445 #define SF_OPCODE_SECT_ER 7
446 #define SF_OPCODE_CHIP_ER 8
447
448 #define SF_DEFAULT_VENDOR 0
449 static const uint8_t vendor = SF_DEFAULT_VENDOR;
450
451 /*
452 * Why isn't WRDI used? Heck if I know.
453 */
454
455 AT_WRITE_1(sc, ATL2_SFOP_WRSR,
456 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WRSR]);
457 AT_WRITE_1(sc, ATL2_SFOP_READ,
458 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_READ]);
459 AT_WRITE_1(sc, ATL2_SFOP_PROGRAM,
460 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_PRGM]);
461 AT_WRITE_1(sc, ATL2_SFOP_WREN,
462 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_WREN]);
463 AT_WRITE_1(sc, ATL2_SFOP_RDSR,
464 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDSR]);
465 AT_WRITE_1(sc, ATL2_SFOP_RDID,
466 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_RDID]);
467 AT_WRITE_1(sc, ATL2_SFOP_SC_ERASE,
468 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_SECT_ER]);
469 AT_WRITE_1(sc, ATL2_SFOP_CHIP_ERASE,
470 lii_sfv[vendor].sfv_opcodes[SF_OPCODE_CHIP_ER]);
471 }
472
473 #define MAKE_SFC(cssetup, clkhi, clklo, cshold, cshi, ins) \
474 ( (((cssetup) & SFC_CS_SETUP_MASK) \
475 << SFC_CS_SETUP_SHIFT) \
476 | (((clkhi) & SFC_CLK_HI_MASK) \
477 << SFC_CLK_HI_SHIFT) \
478 | (((clklo) & SFC_CLK_LO_MASK) \
479 << SFC_CLK_LO_SHIFT) \
480 | (((cshold) & SFC_CS_HOLD_MASK) \
481 << SFC_CS_HOLD_SHIFT) \
482 | (((cshi) & SFC_CS_HI_MASK) \
483 << SFC_CS_HI_SHIFT) \
484 | (((ins) & SFC_INS_MASK) \
485 << SFC_INS_SHIFT))
486
487 /* Magic settings from the Linux driver */
488
489 #define CUSTOM_SPI_CS_SETUP 2
490 #define CUSTOM_SPI_CLK_HI 2
491 #define CUSTOM_SPI_CLK_LO 2
492 #define CUSTOM_SPI_CS_HOLD 2
493 #define CUSTOM_SPI_CS_HI 3
494
495 static int
lii_spi_read(struct lii_softc * sc,uint32_t reg,uint32_t * val)496 lii_spi_read(struct lii_softc *sc, uint32_t reg, uint32_t *val)
497 {
498 uint32_t v;
499 int i;
500
501 AT_WRITE_4(sc, ATL2_SF_DATA, 0);
502 AT_WRITE_4(sc, ATL2_SF_ADDR, reg);
503
504 v = SFC_WAIT_READY |
505 MAKE_SFC(CUSTOM_SPI_CS_SETUP, CUSTOM_SPI_CLK_HI,
506 CUSTOM_SPI_CLK_LO, CUSTOM_SPI_CS_HOLD, CUSTOM_SPI_CS_HI, 1);
507
508 AT_WRITE_4(sc, ATL2_SFC, v);
509 v |= SFC_START;
510 AT_WRITE_4(sc, ATL2_SFC, v);
511
512 for (i = 0; i < 10; ++i) {
513 DELAY(1000);
514 if (!(AT_READ_4(sc, ATL2_SFC) & SFC_START))
515 break;
516 }
517 if (i == 10)
518 return EBUSY;
519
520 *val = AT_READ_4(sc, ATL2_SF_DATA);
521 return 0;
522 }
523
524 static int
lii_read_macaddr(struct lii_softc * sc,uint8_t * ea)525 lii_read_macaddr(struct lii_softc *sc, uint8_t *ea)
526 {
527 uint32_t offset = 0x100;
528 uint32_t val, val1, addr0 = 0, addr1 = 0;
529 uint8_t found = 0;
530
531 while ((*sc->sc_memread)(sc, offset, &val) == 0) {
532 offset += 4;
533
534 /* Each chunk of data starts with a signature */
535 if ((val & 0xff) != 0x5a)
536 break;
537 if ((*sc->sc_memread)(sc, offset, &val1))
538 break;
539
540 offset += 4;
541
542 val >>= 16;
543 switch (val) {
544 case ATL2_MAC_ADDR_0:
545 addr0 = val1;
546 ++found;
547 break;
548 case ATL2_MAC_ADDR_1:
549 addr1 = val1;
550 ++found;
551 break;
552 default:
553 continue;
554 }
555 }
556
557 if (found < 2) {
558 /* Make sure we try the BIOS method before giving up */
559 addr0 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_0));
560 addr1 = htole32(AT_READ_4(sc, ATL2_MAC_ADDR_1));
561 if ((addr0 == 0xffffff && (addr1 & 0xffff) == 0xffff) ||
562 (addr0 == 0 && (addr1 & 0xffff) == 0)) {
563 aprint_error_dev(sc->sc_dev,
564 "error reading MAC address\n");
565 return 1;
566 }
567 } else {
568 addr0 = htole32(addr0);
569 addr1 = htole32(addr1);
570 }
571
572 ea[0] = (addr1 & 0x0000ff00) >> 8;
573 ea[1] = (addr1 & 0x000000ff);
574 ea[2] = (addr0 & 0xff000000) >> 24;
575 ea[3] = (addr0 & 0x00ff0000) >> 16;
576 ea[4] = (addr0 & 0x0000ff00) >> 8;
577 ea[5] = (addr0 & 0x000000ff);
578
579 return 0;
580 }
581
582 static int
lii_mii_readreg(device_t dev,int phy,int reg,uint16_t * val)583 lii_mii_readreg(device_t dev, int phy, int reg, uint16_t *val)
584 {
585 struct lii_softc *sc = device_private(dev);
586 uint32_t data;
587 int i;
588
589 data = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
590
591 data |= MDIOC_START | MDIOC_SUP_PREAMBLE;
592 data |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
593
594 data |= MDIOC_READ;
595
596 AT_WRITE_4(sc, ATL2_MDIOC, data);
597
598 for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
599 DELAY(2);
600 data = AT_READ_4(sc, ATL2_MDIOC);
601 if ((data & (MDIOC_START | MDIOC_BUSY)) == 0)
602 break;
603 }
604
605 if (i == MDIO_WAIT_TIMES) {
606 aprint_error_dev(dev, "timeout reading PHY %d reg %d\n", phy,
607 reg);
608 return ETIMEDOUT;
609 }
610
611 *val = data & 0x0000ffff;
612 return 0;
613 }
614
615 static int
lii_mii_writereg(device_t dev,int phy,int reg,uint16_t val)616 lii_mii_writereg(device_t dev, int phy, int reg, uint16_t val)
617 {
618 struct lii_softc *sc = device_private(dev);
619 uint32_t data;
620 int i;
621
622 data = (reg & MDIOC_REG_MASK) << MDIOC_REG_SHIFT;
623 data |= (val & MDIOC_DATA_MASK) << MDIOC_DATA_SHIFT;
624
625 data |= MDIOC_START | MDIOC_SUP_PREAMBLE;
626 data |= MDIOC_CLK_25_4 << MDIOC_CLK_SEL_SHIFT;
627
628 /* data |= MDIOC_WRITE; */
629
630 AT_WRITE_4(sc, ATL2_MDIOC, data);
631
632 for (i = 0; i < MDIO_WAIT_TIMES; ++i) {
633 DELAY(2);
634 data = AT_READ_4(sc, ATL2_MDIOC);
635 if ((data & (MDIOC_START | MDIOC_BUSY)) == 0)
636 break;
637 }
638
639 if (i == MDIO_WAIT_TIMES) {
640 aprint_error_dev(dev, "timeout writing PHY %d reg %d\n", phy,
641 reg);
642 return ETIMEDOUT;
643 }
644
645 return 0;
646 }
647
648 static void
lii_mii_statchg(struct ifnet * ifp)649 lii_mii_statchg(struct ifnet *ifp)
650 {
651 struct lii_softc *sc = ifp->if_softc;
652 uint32_t val;
653
654 DPRINTF(("lii_mii_statchg\n"));
655
656 val = AT_READ_4(sc, ATL2_MACC);
657
658 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0)
659 val |= MACC_FDX;
660 else
661 val &= ~MACC_FDX;
662
663 AT_WRITE_4(sc, ATL2_MACC, val);
664 }
665
666 static int
lii_media_change(struct ifnet * ifp)667 lii_media_change(struct ifnet *ifp)
668 {
669 struct lii_softc *sc = ifp->if_softc;
670
671 DPRINTF(("lii_media_change\n"));
672
673 if (ifp->if_flags & IFF_UP)
674 mii_mediachg(&sc->sc_mii);
675 return 0;
676 }
677
678 static void
lii_media_status(struct ifnet * ifp,struct ifmediareq * imr)679 lii_media_status(struct ifnet *ifp, struct ifmediareq *imr)
680 {
681 struct lii_softc *sc = ifp->if_softc;
682
683 DPRINTF(("lii_media_status\n"));
684
685 mii_pollstat(&sc->sc_mii);
686 imr->ifm_status = sc->sc_mii.mii_media_status;
687 imr->ifm_active = sc->sc_mii.mii_media_active;
688 }
689
690 static int
lii_init(struct ifnet * ifp)691 lii_init(struct ifnet *ifp)
692 {
693 struct lii_softc *sc = ifp->if_softc;
694 uint32_t val;
695 int error;
696
697 DPRINTF(("lii_init\n"));
698
699 lii_stop(ifp, 0);
700
701 memset(sc->sc_ring, 0, sc->sc_ringsize);
702
703 /* Disable all interrupts */
704 AT_WRITE_4(sc, ATL2_ISR, 0xffffffff);
705
706 /* XXX endianness */
707 AT_WRITE_4(sc, ATL2_MAC_ADDR_0,
708 sc->sc_eaddr[2] << 24 |
709 sc->sc_eaddr[3] << 16 |
710 sc->sc_eaddr[4] << 8 |
711 sc->sc_eaddr[5]);
712 AT_WRITE_4(sc, ATL2_MAC_ADDR_1,
713 sc->sc_eaddr[0] << 8 |
714 sc->sc_eaddr[1]);
715
716 AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0);
717 /* XXX
718 sc->sc_ringmap->dm_segs[0].ds_addr >> 32);
719 */
720 AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO,
721 (sc->sc_ringmap->dm_segs[0].ds_addr & 0xffffffff)
722 + AT_RXD_PADDING);
723 AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO,
724 sc->sc_txsp & 0xffffffff);
725 AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO,
726 sc->sc_txdp & 0xffffffff);
727
728 AT_WRITE_2(sc, ATL2_TXD_BUFFER_SIZE, AT_TXD_BUFFER_SIZE / 4);
729 AT_WRITE_2(sc, ATL2_TXS_NUM_ENTRIES, AT_TXD_NUM);
730 AT_WRITE_2(sc, ATL2_RXD_NUM_ENTRIES, AT_RXD_NUM);
731
732 /*
733 * Inter Packet Gap Time = 0x60 (IPGT)
734 * Minimum inter-frame gap for RX = 0x50 (MIFG)
735 * 64-bit Carrier-Sense window = 0x40 (IPGR1)
736 * 96-bit IPG window = 0x60 (IPGR2)
737 */
738 AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060);
739
740 /*
741 * Collision window = 0x37 (LCOL)
742 * Maximum # of retrans = 0xf (RETRY)
743 * Maximum binary expansion # = 0xa (ABEBT)
744 * IPG to start jam = 0x7 (JAMIPG)
745 */
746 AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 |
747 MHDC_EXC_DEF_EN);
748
749 /* 100 means 200us */
750 AT_WRITE_2(sc, ATL2_IMTIV, 100);
751 AT_WRITE_2(sc, ATL2_SMC, SMC_ITIMER_EN);
752
753 /* 500000 means 100ms */
754 AT_WRITE_2(sc, ATL2_IALTIV, 50000);
755
756 AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN
757 + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);
758
759 /* unit unknown for TX cur-through threshold */
760 AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177);
761
762 AT_WRITE_2(sc, ATL2_PAUSE_ON_TH, AT_RXD_NUM * 7 / 8);
763 AT_WRITE_2(sc, ATL2_PAUSE_OFF_TH, AT_RXD_NUM / 12);
764
765 sc->sc_rxcur = 0;
766 sc->sc_txs_cur = sc->sc_txs_ack = 0;
767 sc->sc_txd_cur = sc->sc_txd_ack = 0;
768 sc->sc_free_tx_slots = true;
769 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur);
770 AT_WRITE_2(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
771
772 AT_WRITE_1(sc, ATL2_DMAR, DMAR_EN);
773 AT_WRITE_1(sc, ATL2_DMAW, DMAW_EN);
774
775 AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT);
776
777 error = ((AT_READ_4(sc, ATL2_ISR) & ISR_PHY_LINKDOWN) != 0);
778 AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff);
779 AT_WRITE_4(sc, ATL2_ISR, 0);
780 if (error) {
781 aprint_error_dev(sc->sc_dev, "init failed\n");
782 goto out;
783 }
784
785 lii_setmulti(sc);
786
787 val = AT_READ_4(sc, ATL2_MACC) & MACC_FDX;
788
789 val |= MACC_RX_EN | MACC_TX_EN | MACC_MACLP_CLK_PHY |
790 MACC_TX_FLOW_EN | MACC_RX_FLOW_EN |
791 MACC_ADD_CRC | MACC_PAD | MACC_BCAST_EN;
792
793 if (ifp->if_flags & IFF_PROMISC)
794 val |= MACC_PROMISC_EN;
795 else if (ifp->if_flags & IFF_ALLMULTI)
796 val |= MACC_ALLMULTI_EN;
797
798 val |= 7 << MACC_PREAMBLE_LEN_SHIFT;
799 val |= 2 << MACC_HDX_LEFT_BUF_SHIFT;
800
801 AT_WRITE_4(sc, ATL2_MACC, val);
802
803 mii_mediachg(&sc->sc_mii);
804
805 AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK);
806
807 callout_schedule(&sc->sc_tick_ch, hz);
808
809 ifp->if_flags |= IFF_RUNNING;
810 ifp->if_flags &= ~IFF_OACTIVE;
811
812 out:
813 return error;
814 }
815
816 static void
lii_tx_put(struct lii_softc * sc,struct mbuf * m)817 lii_tx_put(struct lii_softc *sc, struct mbuf *m)
818 {
819 int left;
820 struct tx_pkt_header *tph =
821 (struct tx_pkt_header *)(sc->sc_txdbase + sc->sc_txd_cur);
822
823 memset(tph, 0, sizeof *tph);
824 tph->txph_size = m->m_pkthdr.len;
825
826 sc->sc_txd_cur = (sc->sc_txd_cur + 4) % AT_TXD_BUFFER_SIZE;
827
828 /*
829 * We already know we have enough space, so if there is a part of the
830 * space ahead of txd_cur that is active, it doesn't matter because
831 * left will be large enough even without it.
832 */
833 left = AT_TXD_BUFFER_SIZE - sc->sc_txd_cur;
834
835 if (left > m->m_pkthdr.len) {
836 m_copydata(m, 0, m->m_pkthdr.len,
837 sc->sc_txdbase + sc->sc_txd_cur);
838 sc->sc_txd_cur += m->m_pkthdr.len;
839 } else {
840 m_copydata(m, 0, left, sc->sc_txdbase + sc->sc_txd_cur);
841 m_copydata(m, left, m->m_pkthdr.len - left, sc->sc_txdbase);
842 sc->sc_txd_cur = m->m_pkthdr.len - left;
843 }
844
845 /* Round to a 32-bit boundary */
846 sc->sc_txd_cur = ((sc->sc_txd_cur + 3) & ~3) % AT_TXD_BUFFER_SIZE;
847 if (sc->sc_txd_cur == sc->sc_txd_ack)
848 sc->sc_free_tx_slots = false;
849 }
850
851 static int
lii_free_tx_space(struct lii_softc * sc)852 lii_free_tx_space(struct lii_softc *sc)
853 {
854 int space;
855
856 if (sc->sc_txd_cur >= sc->sc_txd_ack)
857 space = (AT_TXD_BUFFER_SIZE - sc->sc_txd_cur) +
858 sc->sc_txd_ack;
859 else
860 space = sc->sc_txd_ack - sc->sc_txd_cur;
861
862 /* Account for the tx_pkt_header */
863 return (space - 4);
864 }
865
866 static void
lii_start(struct ifnet * ifp)867 lii_start(struct ifnet *ifp)
868 {
869 struct lii_softc *sc = ifp->if_softc;
870 struct mbuf *m0;
871
872 DPRINTF(("lii_start\n"));
873
874 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
875 return;
876
877 for (;;) {
878 IFQ_POLL(&ifp->if_snd, m0);
879 if (m0 == NULL)
880 break;
881
882 if (!sc->sc_free_tx_slots ||
883 lii_free_tx_space(sc) < m0->m_pkthdr.len) {
884 ifp->if_flags |= IFF_OACTIVE;
885 break;
886 }
887
888 lii_tx_put(sc, m0);
889
890 DPRINTF(("lii_start: put %d\n", sc->sc_txs_cur));
891
892 sc->sc_txs[sc->sc_txs_cur].txps_update = 0;
893 sc->sc_txs_cur = (sc->sc_txs_cur + 1) % AT_TXD_NUM;
894 if (sc->sc_txs_cur == sc->sc_txs_ack)
895 sc->sc_free_tx_slots = false;
896
897 AT_WRITE_2(sc, ATL2_MB_TXD_WR_IDX, sc->sc_txd_cur/4);
898
899 IFQ_DEQUEUE(&ifp->if_snd, m0);
900
901 bpf_mtap(ifp, m0, BPF_D_OUT);
902 m_freem(m0);
903 }
904 }
905
906 static void
lii_stop(struct ifnet * ifp,int disable)907 lii_stop(struct ifnet *ifp, int disable)
908 {
909 struct lii_softc *sc = ifp->if_softc;
910
911 callout_stop(&sc->sc_tick_ch);
912
913 ifp->if_timer = 0;
914 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
915
916 mii_down(&sc->sc_mii);
917
918 lii_reset(sc);
919
920 AT_WRITE_4(sc, ATL2_IMR, 0);
921 }
922
923 static int
lii_intr(void * v)924 lii_intr(void *v)
925 {
926 struct lii_softc *sc = v;
927 uint32_t status;
928 uint16_t tmp;
929
930 status = AT_READ_4(sc, ATL2_ISR);
931 if (status == 0)
932 return 0;
933
934 DPRINTF(("lii_intr (%x)\n", status));
935
936 /* Clear the interrupt and disable them */
937 AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT);
938
939 if (status & (ISR_PHY | ISR_MANUAL)) {
940 /* Ack PHY interrupt. Magic register */
941 if (status & ISR_PHY)
942 (void)lii_mii_readreg(sc->sc_dev, 1, 19, &tmp);
943 mii_mediachg(&sc->sc_mii);
944 }
945
946 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | ISR_PHY_LINKDOWN)) {
947 lii_init(&sc->sc_ec.ec_if);
948 return 1;
949 }
950
951 if (status & ISR_RX_EVENT) {
952 #ifdef LII_DEBUG
953 if (!(status & ISR_RS_UPDATE))
954 printf("rxintr %08x\n", status);
955 #endif
956 lii_rxintr(sc);
957 }
958
959 if (status & ISR_TX_EVENT)
960 lii_txintr(sc);
961
962 /* Re-enable interrupts */
963 AT_WRITE_4(sc, ATL2_ISR, 0);
964
965 return 1;
966 }
967
968 static void
lii_rxintr(struct lii_softc * sc)969 lii_rxintr(struct lii_softc *sc)
970 {
971 struct ifnet *ifp = &sc->sc_ec.ec_if;
972 struct rx_pkt *rxp;
973 struct mbuf *m;
974 uint16_t size;
975
976 DPRINTF(("lii_rxintr\n"));
977
978 for (;;) {
979 rxp = &sc->sc_rxp[sc->sc_rxcur];
980 if (rxp->rxp_update == 0)
981 break;
982
983 DPRINTF(("lii_rxintr: getting %u (%u) [%x]\n", sc->sc_rxcur,
984 rxp->rxp_size, rxp->rxp_flags));
985 sc->sc_rxcur = (sc->sc_rxcur + 1) % AT_RXD_NUM;
986 rxp->rxp_update = 0;
987 if (!(rxp->rxp_flags & ATL2_RXF_SUCCESS)) {
988 if_statinc(ifp, if_ierrors);
989 continue;
990 }
991
992 MGETHDR(m, M_DONTWAIT, MT_DATA);
993 if (m == NULL) {
994 if_statinc(ifp, if_ierrors);
995 continue;
996 }
997 size = rxp->rxp_size - ETHER_CRC_LEN;
998 if (size > MHLEN) {
999 MCLGET(m, M_DONTWAIT);
1000 if ((m->m_flags & M_EXT) == 0) {
1001 m_freem(m);
1002 if_statinc(ifp, if_ierrors);
1003 continue;
1004 }
1005 }
1006
1007 m_set_rcvif(m, ifp);
1008 /* Copy the packet without the FCS */
1009 m->m_pkthdr.len = m->m_len = size;
1010 memcpy(mtod(m, void *), &rxp->rxp_data[0], size);
1011
1012 if_percpuq_enqueue(ifp->if_percpuq, m);
1013 }
1014
1015 AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
1016 }
1017
1018 static void
lii_txintr(struct lii_softc * sc)1019 lii_txintr(struct lii_softc *sc)
1020 {
1021 struct ifnet *ifp = &sc->sc_ec.ec_if;
1022 struct tx_pkt_status *txs;
1023 struct tx_pkt_header *txph;
1024
1025 DPRINTF(("lii_txintr\n"));
1026
1027 for (;;) {
1028 txs = &sc->sc_txs[sc->sc_txs_ack];
1029 if (txs->txps_update == 0)
1030 break;
1031 DPRINTF(("lii_txintr: ack'd %d\n", sc->sc_txs_ack));
1032 sc->sc_txs_ack = (sc->sc_txs_ack + 1) % AT_TXD_NUM;
1033 sc->sc_free_tx_slots = true;
1034
1035 txs->txps_update = 0;
1036
1037 txph = (struct tx_pkt_header *)
1038 (sc->sc_txdbase + sc->sc_txd_ack);
1039
1040 if (txph->txph_size != txs->txps_size)
1041 aprint_error_dev(sc->sc_dev,
1042 "mismatched status and packet\n");
1043 /*
1044 * Move ack by the packet size, taking the packet header in
1045 * account and round to the next 32-bit boundary
1046 * (7 = sizeof(header) + 3)
1047 */
1048 sc->sc_txd_ack = (sc->sc_txd_ack + txph->txph_size + 7 ) & ~3;
1049 sc->sc_txd_ack %= AT_TXD_BUFFER_SIZE;
1050
1051 if (txs->txps_flags & ATL2_TXF_SUCCESS)
1052 if_statinc(ifp, if_opackets);
1053 else
1054 if_statinc(ifp, if_oerrors);
1055 ifp->if_flags &= ~IFF_OACTIVE;
1056 }
1057
1058 if (sc->sc_free_tx_slots)
1059 if_schedule_deferred_start(ifp);
1060 }
1061
1062 static int
lii_alloc_rings(struct lii_softc * sc)1063 lii_alloc_rings(struct lii_softc *sc)
1064 {
1065 int nsegs;
1066 bus_size_t bs;
1067
1068 /*
1069 * We need a big chunk of DMA-friendly memory because descriptors
1070 * are not separate from data on that crappy hardware, which means
1071 * we'll have to copy data from and to that memory zone to and from
1072 * the mbufs.
1073 *
1074 * How lame is that? Using the default values from the Linux driver,
1075 * we allocate space for receiving up to 64 full-size Ethernet frames,
1076 * and only 8kb for transmitting up to 64 Ethernet frames.
1077 */
1078
1079 sc->sc_ringsize = bs = AT_RXD_PADDING
1080 + AT_RXD_NUM * sizeof(struct rx_pkt)
1081 + AT_TXD_NUM * sizeof(struct tx_pkt_status)
1082 + AT_TXD_BUFFER_SIZE;
1083
1084 if (bus_dmamap_create(sc->sc_dmat, bs, 1, bs, (1<<30),
1085 BUS_DMA_NOWAIT, &sc->sc_ringmap) != 0) {
1086 aprint_error_dev(sc->sc_dev, "bus_dmamap_create failed\n");
1087 return 1;
1088 }
1089
1090 if (bus_dmamem_alloc(sc->sc_dmat, bs, PAGE_SIZE, (1<<30),
1091 &sc->sc_ringseg, 1, &nsegs, BUS_DMA_NOWAIT) != 0) {
1092 aprint_error_dev(sc->sc_dev, "bus_dmamem_alloc failed\n");
1093 goto fail;
1094 }
1095
1096 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_ringseg, nsegs, bs,
1097 (void **)&sc->sc_ring, BUS_DMA_NOWAIT) != 0) {
1098 aprint_error_dev(sc->sc_dev, "bus_dmamem_map failed\n");
1099 goto fail1;
1100 }
1101
1102 if (bus_dmamap_load(sc->sc_dmat, sc->sc_ringmap, sc->sc_ring,
1103 bs, NULL, BUS_DMA_NOWAIT) != 0) {
1104 aprint_error_dev(sc->sc_dev, "bus_dmamap_load failed\n");
1105 goto fail2;
1106 }
1107
1108 sc->sc_rxp = (void *)(sc->sc_ring + AT_RXD_PADDING);
1109 sc->sc_txs = (void *)(sc->sc_ring + AT_RXD_PADDING
1110 + AT_RXD_NUM * sizeof(struct rx_pkt));
1111 sc->sc_txdbase = ((char *)sc->sc_txs)
1112 + AT_TXD_NUM * sizeof(struct tx_pkt_status);
1113 sc->sc_txsp = sc->sc_ringmap->dm_segs[0].ds_addr
1114 + ((char *)sc->sc_txs - (char *)sc->sc_ring);
1115 sc->sc_txdp = sc->sc_ringmap->dm_segs[0].ds_addr
1116 + ((char *)sc->sc_txdbase - (char *)sc->sc_ring);
1117
1118 return 0;
1119
1120 fail2:
1121 bus_dmamem_unmap(sc->sc_dmat, sc->sc_ring, bs);
1122 fail1:
1123 bus_dmamem_free(sc->sc_dmat, &sc->sc_ringseg, nsegs);
1124 fail:
1125 bus_dmamap_destroy(sc->sc_dmat, sc->sc_ringmap);
1126 return 1;
1127 }
1128
1129 static void
lii_watchdog(struct ifnet * ifp)1130 lii_watchdog(struct ifnet *ifp)
1131 {
1132 struct lii_softc *sc = ifp->if_softc;
1133
1134 aprint_error_dev(sc->sc_dev, "watchdog timeout\n");
1135 if_statinc(ifp, if_oerrors);
1136 lii_init(ifp);
1137 }
1138
1139 static int
lii_ioctl(struct ifnet * ifp,u_long cmd,void * data)1140 lii_ioctl(struct ifnet *ifp, u_long cmd, void *data)
1141 {
1142 struct lii_softc *sc = ifp->if_softc;
1143 int s, error;
1144
1145 s = splnet();
1146
1147 switch (cmd) {
1148 default:
1149 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
1150 if (ifp->if_flags & IFF_RUNNING)
1151 lii_setmulti(sc);
1152 error = 0;
1153 }
1154 break;
1155 }
1156
1157 splx(s);
1158
1159 return error;
1160 }
1161
1162 static void
lii_setmulti(struct lii_softc * sc)1163 lii_setmulti(struct lii_softc *sc)
1164 {
1165 struct ethercom *ec = &sc->sc_ec;
1166 struct ifnet *ifp = &ec->ec_if;
1167 uint32_t mht0 = 0, mht1 = 0, crc;
1168 struct ether_multi *enm;
1169 struct ether_multistep step;
1170
1171 /* Clear multicast hash table */
1172 AT_WRITE_4(sc, ATL2_MHT, 0);
1173 AT_WRITE_4(sc, ATL2_MHT + 4, 0);
1174
1175 ifp->if_flags &= ~IFF_ALLMULTI;
1176
1177 ETHER_LOCK(ec);
1178 ETHER_FIRST_MULTI(step, ec, enm);
1179 while (enm != NULL) {
1180 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1181 ifp->if_flags |= IFF_ALLMULTI;
1182 mht0 = mht1 = 0;
1183 ETHER_UNLOCK(ec);
1184 goto alldone;
1185 }
1186
1187 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1188
1189 if (crc & (1U << 31))
1190 mht1 |= (1U << ((crc >> 26) & 0x0000001f));
1191 else
1192 mht0 |= (1U << ((crc >> 26) & 0x0000001f));
1193
1194 ETHER_NEXT_MULTI(step, enm);
1195 }
1196 ETHER_UNLOCK(ec);
1197
1198 alldone:
1199 AT_WRITE_4(sc, ATL2_MHT, mht0);
1200 AT_WRITE_4(sc, ATL2_MHT+4, mht1);
1201 }
1202
1203 static void
lii_tick(void * v)1204 lii_tick(void *v)
1205 {
1206 struct lii_softc *sc = v;
1207 int s;
1208
1209 s = splnet();
1210 mii_tick(&sc->sc_mii);
1211 splx(s);
1212
1213 callout_schedule(&sc->sc_tick_ch, hz);
1214 }
1215