1 /* $NetBSD: mga_dma.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
4 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
5 *
6 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
7 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * All Rights Reserved.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the next
18 * paragraph) shall be included in all copies or substantial portions of the
19 * Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
27 * DEALINGS IN THE SOFTWARE.
28 */
29
30 /**
31 * \file mga_dma.c
32 * DMA support for MGA G200 / G400.
33 *
34 * \author Rickard E. (Rik) Faith <faith@valinux.com>
35 * \author Jeff Hartmann <jhartmann@valinux.com>
36 * \author Keith Whitwell <keith@tungstengraphics.com>
37 * \author Gareth Hughes <gareth@valinux.com>
38 */
39
40 #include <sys/cdefs.h>
41 __KERNEL_RCSID(0, "$NetBSD: mga_dma.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $");
42
43 #include <linux/delay.h>
44
45 #include "mga_drv.h"
46
47 #define MGA_DEFAULT_USEC_TIMEOUT 10000
48 #define MGA_FREELIST_DEBUG 0
49
50 #define MINIMAL_CLEANUP 0
51 #define FULL_CLEANUP 1
52 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
53
54 /* ================================================================
55 * Engine control
56 */
57
mga_do_wait_for_idle(drm_mga_private_t * dev_priv)58 int mga_do_wait_for_idle(drm_mga_private_t *dev_priv)
59 {
60 u32 status = 0;
61 int i;
62 DRM_DEBUG("\n");
63
64 for (i = 0; i < dev_priv->usec_timeout; i++) {
65 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
66 if (status == MGA_ENDPRDMASTS) {
67 MGA_WRITE8(MGA_CRTC_INDEX, 0);
68 return 0;
69 }
70 udelay(1);
71 }
72
73 #if MGA_DMA_DEBUG
74 DRM_ERROR("failed!\n");
75 DRM_INFO(" status=0x%08x\n", status);
76 #endif
77 return -EBUSY;
78 }
79
mga_do_dma_reset(drm_mga_private_t * dev_priv)80 static int mga_do_dma_reset(drm_mga_private_t *dev_priv)
81 {
82 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
83 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
84
85 DRM_DEBUG("\n");
86
87 /* The primary DMA stream should look like new right about now.
88 */
89 primary->tail = 0;
90 primary->space = primary->size;
91 primary->last_flush = 0;
92
93 sarea_priv->last_wrap = 0;
94
95 /* FIXME: Reset counters, buffer ages etc...
96 */
97
98 /* FIXME: What else do we need to reinitialize? WARP stuff?
99 */
100
101 return 0;
102 }
103
104 /* ================================================================
105 * Primary DMA stream
106 */
107
mga_do_dma_flush(drm_mga_private_t * dev_priv)108 void mga_do_dma_flush(drm_mga_private_t *dev_priv)
109 {
110 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
111 u32 head, tail;
112 u32 status = 0;
113 int i;
114 DMA_LOCALS;
115 DRM_DEBUG("\n");
116
117 /* We need to wait so that we can do an safe flush */
118 for (i = 0; i < dev_priv->usec_timeout; i++) {
119 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
120 if (status == MGA_ENDPRDMASTS)
121 break;
122 udelay(1);
123 }
124
125 if (primary->tail == primary->last_flush) {
126 DRM_DEBUG(" bailing out...\n");
127 return;
128 }
129
130 tail = primary->tail + dev_priv->primary->offset;
131
132 /* We need to pad the stream between flushes, as the card
133 * actually (partially?) reads the first of these commands.
134 * See page 4-16 in the G400 manual, middle of the page or so.
135 */
136 BEGIN_DMA(1);
137
138 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
139 MGA_DMAPAD, 0x00000000,
140 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
141
142 ADVANCE_DMA();
143
144 primary->last_flush = primary->tail;
145
146 head = MGA_READ(MGA_PRIMADDRESS);
147
148 if (head <= tail)
149 primary->space = primary->size - primary->tail;
150 else
151 primary->space = head - tail;
152
153 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
154 DRM_DEBUG(" tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset));
155 DRM_DEBUG(" space = 0x%06x\n", primary->space);
156
157 mga_flush_write_combine();
158 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
159
160 DRM_DEBUG("done.\n");
161 }
162
mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)163 void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv)
164 {
165 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
166 u32 head, tail;
167 DMA_LOCALS;
168 DRM_DEBUG("\n");
169
170 BEGIN_DMA_WRAP();
171
172 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
173 MGA_DMAPAD, 0x00000000,
174 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
175
176 ADVANCE_DMA();
177
178 tail = primary->tail + dev_priv->primary->offset;
179
180 primary->tail = 0;
181 primary->last_flush = 0;
182 primary->last_wrap++;
183
184 head = MGA_READ(MGA_PRIMADDRESS);
185
186 if (head == dev_priv->primary->offset)
187 primary->space = primary->size;
188 else
189 primary->space = head - dev_priv->primary->offset;
190
191 DRM_DEBUG(" head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
192 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
193 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
194 DRM_DEBUG(" space = 0x%06x\n", primary->space);
195
196 mga_flush_write_combine();
197 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
198
199 set_bit(0, &primary->wrapped);
200 DRM_DEBUG("done.\n");
201 }
202
mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)203 void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv)
204 {
205 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
206 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
207 u32 head = dev_priv->primary->offset;
208 DRM_DEBUG("\n");
209
210 sarea_priv->last_wrap++;
211 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
212
213 mga_flush_write_combine();
214 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
215
216 clear_bit(0, &primary->wrapped);
217 DRM_DEBUG("done.\n");
218 }
219
220 /* ================================================================
221 * Freelist management
222 */
223
224 #define MGA_BUFFER_USED (~0)
225 #define MGA_BUFFER_FREE 0
226
227 #if MGA_FREELIST_DEBUG
mga_freelist_print(struct drm_device * dev)228 static void mga_freelist_print(struct drm_device *dev)
229 {
230 drm_mga_private_t *dev_priv = dev->dev_private;
231 drm_mga_freelist_t *entry;
232
233 DRM_INFO("\n");
234 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
235 dev_priv->sarea_priv->last_dispatch,
236 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
237 dev_priv->primary->offset));
238 DRM_INFO("current freelist:\n");
239
240 for (entry = dev_priv->head->next; entry; entry = entry->next) {
241 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
242 entry, entry->buf->idx, entry->age.head,
243 (unsigned long)(entry->age.head - dev_priv->primary->offset));
244 }
245 DRM_INFO("\n");
246 }
247 #endif
248
mga_freelist_init(struct drm_device * dev,drm_mga_private_t * dev_priv)249 static int mga_freelist_init(struct drm_device *dev, drm_mga_private_t *dev_priv)
250 {
251 struct drm_device_dma *dma = dev->dma;
252 struct drm_buf *buf;
253 drm_mga_buf_priv_t *buf_priv;
254 drm_mga_freelist_t *entry;
255 int i;
256 DRM_DEBUG("count=%d\n", dma->buf_count);
257
258 dev_priv->head = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
259 if (dev_priv->head == NULL)
260 return -ENOMEM;
261
262 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
263
264 for (i = 0; i < dma->buf_count; i++) {
265 buf = dma->buflist[i];
266 buf_priv = buf->dev_private;
267
268 entry = kzalloc(sizeof(drm_mga_freelist_t), GFP_KERNEL);
269 if (entry == NULL)
270 return -ENOMEM;
271
272 entry->next = dev_priv->head->next;
273 entry->prev = dev_priv->head;
274 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
275 entry->buf = buf;
276
277 if (dev_priv->head->next != NULL)
278 dev_priv->head->next->prev = entry;
279 if (entry->next == NULL)
280 dev_priv->tail = entry;
281
282 buf_priv->list_entry = entry;
283 buf_priv->discard = 0;
284 buf_priv->dispatched = 0;
285
286 dev_priv->head->next = entry;
287 }
288
289 return 0;
290 }
291
mga_freelist_cleanup(struct drm_device * dev)292 static void mga_freelist_cleanup(struct drm_device *dev)
293 {
294 drm_mga_private_t *dev_priv = dev->dev_private;
295 drm_mga_freelist_t *entry;
296 drm_mga_freelist_t *next;
297 DRM_DEBUG("\n");
298
299 entry = dev_priv->head;
300 while (entry) {
301 next = entry->next;
302 kfree(entry);
303 entry = next;
304 }
305
306 dev_priv->head = dev_priv->tail = NULL;
307 }
308
309 #if 0
310 /* FIXME: Still needed?
311 */
312 static void mga_freelist_reset(struct drm_device *dev)
313 {
314 struct drm_device_dma *dma = dev->dma;
315 struct drm_buf *buf;
316 drm_mga_buf_priv_t *buf_priv;
317 int i;
318
319 for (i = 0; i < dma->buf_count; i++) {
320 buf = dma->buflist[i];
321 buf_priv = buf->dev_private;
322 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
323 }
324 }
325 #endif
326
mga_freelist_get(struct drm_device * dev)327 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
328 {
329 drm_mga_private_t *dev_priv = dev->dev_private;
330 drm_mga_freelist_t *next;
331 drm_mga_freelist_t *prev;
332 drm_mga_freelist_t *tail = dev_priv->tail;
333 u32 head, wrap;
334 DRM_DEBUG("\n");
335
336 head = MGA_READ(MGA_PRIMADDRESS);
337 wrap = dev_priv->sarea_priv->last_wrap;
338
339 DRM_DEBUG(" tail=0x%06lx %d\n",
340 tail->age.head ?
341 (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0,
342 tail->age.wrap);
343 DRM_DEBUG(" head=0x%06lx %d\n",
344 (unsigned long)(head - dev_priv->primary->offset), wrap);
345
346 if (TEST_AGE(&tail->age, head, wrap)) {
347 prev = dev_priv->tail->prev;
348 next = dev_priv->tail;
349 prev->next = NULL;
350 next->prev = next->next = NULL;
351 dev_priv->tail = prev;
352 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
353 return next->buf;
354 }
355
356 DRM_DEBUG("returning NULL!\n");
357 return NULL;
358 }
359
mga_freelist_put(struct drm_device * dev,struct drm_buf * buf)360 int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf)
361 {
362 drm_mga_private_t *dev_priv = dev->dev_private;
363 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
364 drm_mga_freelist_t *head, *entry, *prev;
365
366 DRM_DEBUG("age=0x%06lx wrap=%d\n",
367 (unsigned long)(buf_priv->list_entry->age.head -
368 dev_priv->primary->offset),
369 buf_priv->list_entry->age.wrap);
370
371 entry = buf_priv->list_entry;
372 head = dev_priv->head;
373
374 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
375 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
376 prev = dev_priv->tail;
377 prev->next = entry;
378 entry->prev = prev;
379 entry->next = NULL;
380 } else {
381 prev = head->next;
382 head->next = entry;
383 prev->prev = entry;
384 entry->prev = head;
385 entry->next = prev;
386 }
387
388 return 0;
389 }
390
391 /* ================================================================
392 * DMA initialization, cleanup
393 */
394
mga_driver_load(struct drm_device * dev,unsigned long flags)395 int mga_driver_load(struct drm_device *dev, unsigned long flags)
396 {
397 drm_mga_private_t *dev_priv;
398 int ret;
399
400 /* There are PCI versions of the G450. These cards have the
401 * same PCI ID as the AGP G450, but have an additional PCI-to-PCI
402 * bridge chip. We detect these cards, which are not currently
403 * supported by this driver, by looking at the device ID of the
404 * bus the "card" is on. If vendor is 0x3388 (Hint Corp) and the
405 * device is 0x0021 (HB6 Universal PCI-PCI bridge), we reject the
406 * device.
407 */
408 if ((dev->pdev->device == 0x0525) && dev->pdev->bus->self
409 && (dev->pdev->bus->self->vendor == 0x3388)
410 && (dev->pdev->bus->self->device == 0x0021)
411 && dev->agp) {
412 /* FIXME: This should be quirked in the pci core, but oh well
413 * the hw probably stopped existing. */
414 arch_phys_wc_del(dev->agp->agp_mtrr);
415 kfree(dev->agp);
416 dev->agp = NULL;
417 }
418 dev_priv = kzalloc(sizeof(drm_mga_private_t), GFP_KERNEL);
419 if (!dev_priv)
420 return -ENOMEM;
421
422 dev->dev_private = (void *)dev_priv;
423
424 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
425 dev_priv->chipset = flags;
426
427 pci_set_master(dev->pdev);
428
429 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
430 dev_priv->mmio_size = pci_resource_len(dev->pdev, 1);
431
432 ret = drm_vblank_init(dev, 1);
433
434 if (ret) {
435 (void) mga_driver_unload(dev);
436 return ret;
437 }
438
439 return 0;
440 }
441
442 #if IS_ENABLED(CONFIG_AGP)
443 /**
444 * Bootstrap the driver for AGP DMA.
445 *
446 * \todo
447 * Investigate whether there is any benefit to storing the WARP microcode in
448 * AGP memory. If not, the microcode may as well always be put in PCI
449 * memory.
450 *
451 * \todo
452 * This routine needs to set dma_bs->agp_mode to the mode actually configured
453 * in the hardware. Looking just at the Linux AGP driver code, I don't see
454 * an easy way to determine this.
455 *
456 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
457 */
mga_do_agp_dma_bootstrap(struct drm_device * dev,drm_mga_dma_bootstrap_t * dma_bs)458 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
459 drm_mga_dma_bootstrap_t *dma_bs)
460 {
461 drm_mga_private_t *const dev_priv =
462 (drm_mga_private_t *) dev->dev_private;
463 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
464 int err;
465 unsigned offset;
466 const unsigned secondary_size = dma_bs->secondary_bin_count
467 * dma_bs->secondary_bin_size;
468 const unsigned agp_size = (dma_bs->agp_size << 20);
469 struct drm_buf_desc req;
470 struct drm_agp_mode mode;
471 struct drm_agp_info info;
472 struct drm_agp_buffer agp_req;
473 struct drm_agp_binding bind_req;
474
475 /* Acquire AGP. */
476 err = drm_agp_acquire(dev);
477 if (err) {
478 DRM_ERROR("Unable to acquire AGP: %d\n", err);
479 return err;
480 }
481
482 err = drm_agp_info(dev, &info);
483 if (err) {
484 DRM_ERROR("Unable to get AGP info: %d\n", err);
485 return err;
486 }
487
488 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
489 err = drm_agp_enable(dev, mode);
490 if (err) {
491 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
492 return err;
493 }
494
495 /* In addition to the usual AGP mode configuration, the G200 AGP cards
496 * need to have the AGP mode "manually" set.
497 */
498
499 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
500 if (mode.mode & 0x02)
501 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
502 else
503 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
504 }
505
506 /* Allocate and bind AGP memory. */
507 agp_req.size = agp_size;
508 agp_req.type = 0;
509 err = drm_agp_alloc(dev, &agp_req);
510 if (err) {
511 dev_priv->agp_size = 0;
512 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
513 dma_bs->agp_size);
514 return err;
515 }
516
517 dev_priv->agp_size = agp_size;
518 dev_priv->agp_handle = agp_req.handle;
519
520 bind_req.handle = agp_req.handle;
521 bind_req.offset = 0;
522 err = drm_agp_bind(dev, &bind_req);
523 if (err) {
524 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
525 return err;
526 }
527
528 /* Make drm_legacy_addbufs happy by not trying to create a mapping for
529 * less than a page.
530 */
531 if (warp_size < PAGE_SIZE)
532 warp_size = PAGE_SIZE;
533
534 offset = 0;
535 err = drm_legacy_addmap(dev, offset, warp_size,
536 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
537 if (err) {
538 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
539 return err;
540 }
541
542 offset += warp_size;
543 err = drm_legacy_addmap(dev, offset, dma_bs->primary_size,
544 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
545 if (err) {
546 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
547 return err;
548 }
549
550 offset += dma_bs->primary_size;
551 err = drm_legacy_addmap(dev, offset, secondary_size,
552 _DRM_AGP, 0, &dev->agp_buffer_map);
553 if (err) {
554 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
555 return err;
556 }
557
558 (void)memset(&req, 0, sizeof(req));
559 req.count = dma_bs->secondary_bin_count;
560 req.size = dma_bs->secondary_bin_size;
561 req.flags = _DRM_AGP_BUFFER;
562 req.agp_start = offset;
563
564 err = drm_legacy_addbufs_agp(dev, &req);
565 if (err) {
566 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
567 return err;
568 }
569
570 {
571 struct drm_map_list *_entry;
572 unsigned long agp_token = 0;
573
574 list_for_each_entry(_entry, &dev->maplist, head) {
575 if (_entry->map == dev->agp_buffer_map)
576 agp_token = _entry->user_token;
577 }
578 if (!agp_token)
579 return -EFAULT;
580
581 dev->agp_buffer_token = agp_token;
582 }
583
584 offset += secondary_size;
585 err = drm_legacy_addmap(dev, offset, agp_size - offset,
586 _DRM_AGP, 0, &dev_priv->agp_textures);
587 if (err) {
588 DRM_ERROR("Unable to map AGP texture region %d\n", err);
589 return err;
590 }
591
592 drm_legacy_ioremap(dev_priv->warp, dev);
593 drm_legacy_ioremap(dev_priv->primary, dev);
594 drm_legacy_ioremap(dev->agp_buffer_map, dev);
595
596 if (!dev_priv->warp->handle ||
597 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
598 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
599 dev_priv->warp->handle, dev_priv->primary->handle,
600 dev->agp_buffer_map->handle);
601 return -ENOMEM;
602 }
603
604 dev_priv->dma_access = MGA_PAGPXFER;
605 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
606
607 DRM_INFO("Initialized card for AGP DMA.\n");
608 return 0;
609 }
610 #else
mga_do_agp_dma_bootstrap(struct drm_device * dev,drm_mga_dma_bootstrap_t * dma_bs)611 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
612 drm_mga_dma_bootstrap_t *dma_bs)
613 {
614 return -EINVAL;
615 }
616 #endif
617
618 /**
619 * Bootstrap the driver for PCI DMA.
620 *
621 * \todo
622 * The algorithm for decreasing the size of the primary DMA buffer could be
623 * better. The size should be rounded up to the nearest page size, then
624 * decrease the request size by a single page each pass through the loop.
625 *
626 * \todo
627 * Determine whether the maximum address passed to drm_pci_alloc is correct.
628 * The same goes for drm_legacy_addbufs_pci.
629 *
630 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
631 */
mga_do_pci_dma_bootstrap(struct drm_device * dev,drm_mga_dma_bootstrap_t * dma_bs)632 static int mga_do_pci_dma_bootstrap(struct drm_device *dev,
633 drm_mga_dma_bootstrap_t *dma_bs)
634 {
635 drm_mga_private_t *const dev_priv =
636 (drm_mga_private_t *) dev->dev_private;
637 unsigned int warp_size = MGA_WARP_UCODE_SIZE;
638 unsigned int primary_size;
639 unsigned int bin_count;
640 int err;
641 struct drm_buf_desc req;
642
643 if (dev->dma == NULL) {
644 DRM_ERROR("dev->dma is NULL\n");
645 return -EFAULT;
646 }
647
648 /* Make drm_legacy_addbufs happy by not trying to create a mapping for
649 * less than a page.
650 */
651 if (warp_size < PAGE_SIZE)
652 warp_size = PAGE_SIZE;
653
654 /* The proper alignment is 0x100 for this mapping */
655 err = drm_legacy_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
656 _DRM_READ_ONLY, &dev_priv->warp);
657 if (err != 0) {
658 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
659 err);
660 return err;
661 }
662
663 /* Other than the bottom two bits being used to encode other
664 * information, there don't appear to be any restrictions on the
665 * alignment of the primary or secondary DMA buffers.
666 */
667
668 for (primary_size = dma_bs->primary_size; primary_size != 0;
669 primary_size >>= 1) {
670 /* The proper alignment for this mapping is 0x04 */
671 err = drm_legacy_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
672 _DRM_READ_ONLY, &dev_priv->primary);
673 if (!err)
674 break;
675 }
676
677 if (err != 0) {
678 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
679 return -ENOMEM;
680 }
681
682 if (dev_priv->primary->size != dma_bs->primary_size) {
683 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
684 dma_bs->primary_size,
685 (unsigned)dev_priv->primary->size);
686 dma_bs->primary_size = dev_priv->primary->size;
687 }
688
689 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
690 bin_count--) {
691 (void)memset(&req, 0, sizeof(req));
692 req.count = bin_count;
693 req.size = dma_bs->secondary_bin_size;
694
695 err = drm_legacy_addbufs_pci(dev, &req);
696 if (!err)
697 break;
698 }
699
700 if (bin_count == 0) {
701 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
702 return err;
703 }
704
705 if (bin_count != dma_bs->secondary_bin_count) {
706 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
707 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
708
709 dma_bs->secondary_bin_count = bin_count;
710 }
711
712 dev_priv->dma_access = 0;
713 dev_priv->wagp_enable = 0;
714
715 dma_bs->agp_mode = 0;
716
717 DRM_INFO("Initialized card for PCI DMA.\n");
718 return 0;
719 }
720
mga_do_dma_bootstrap(struct drm_device * dev,drm_mga_dma_bootstrap_t * dma_bs)721 static int mga_do_dma_bootstrap(struct drm_device *dev,
722 drm_mga_dma_bootstrap_t *dma_bs)
723 {
724 const int is_agp = (dma_bs->agp_mode != 0) && dev->agp;
725 int err;
726 drm_mga_private_t *const dev_priv =
727 (drm_mga_private_t *) dev->dev_private;
728
729 dev_priv->used_new_dma_init = 1;
730
731 /* The first steps are the same for both PCI and AGP based DMA. Map
732 * the cards MMIO registers and map a status page.
733 */
734 err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
735 _DRM_REGISTERS, _DRM_READ_ONLY,
736 &dev_priv->mmio);
737 if (err) {
738 DRM_ERROR("Unable to map MMIO region: %d\n", err);
739 return err;
740 }
741
742 err = drm_legacy_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
743 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
744 &dev_priv->status);
745 if (err) {
746 DRM_ERROR("Unable to map status region: %d\n", err);
747 return err;
748 }
749
750 /* The DMA initialization procedure is slightly different for PCI and
751 * AGP cards. AGP cards just allocate a large block of AGP memory and
752 * carve off portions of it for internal uses. The remaining memory
753 * is returned to user-mode to be used for AGP textures.
754 */
755 if (is_agp)
756 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
757
758 /* If we attempted to initialize the card for AGP DMA but failed,
759 * clean-up any mess that may have been created.
760 */
761
762 if (err)
763 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
764
765 /* Not only do we want to try and initialized PCI cards for PCI DMA,
766 * but we also try to initialized AGP cards that could not be
767 * initialized for AGP DMA. This covers the case where we have an AGP
768 * card in a system with an unsupported AGP chipset. In that case the
769 * card will be detected as AGP, but we won't be able to allocate any
770 * AGP memory, etc.
771 */
772
773 if (!is_agp || err)
774 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
775
776 return err;
777 }
778
mga_dma_bootstrap(struct drm_device * dev,void * data,struct drm_file * file_priv)779 int mga_dma_bootstrap(struct drm_device *dev, void *data,
780 struct drm_file *file_priv)
781 {
782 drm_mga_dma_bootstrap_t *bootstrap = data;
783 int err;
784 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
785 const drm_mga_private_t *const dev_priv =
786 (drm_mga_private_t *) dev->dev_private;
787
788 err = mga_do_dma_bootstrap(dev, bootstrap);
789 if (err) {
790 mga_do_cleanup_dma(dev, FULL_CLEANUP);
791 return err;
792 }
793
794 if (dev_priv->agp_textures != NULL) {
795 bootstrap->texture_handle = dev_priv->agp_textures->offset;
796 bootstrap->texture_size = dev_priv->agp_textures->size;
797 } else {
798 bootstrap->texture_handle = 0;
799 bootstrap->texture_size = 0;
800 }
801
802 bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
803
804 return err;
805 }
806
mga_do_init_dma(struct drm_device * dev,drm_mga_init_t * init)807 static int mga_do_init_dma(struct drm_device *dev, drm_mga_init_t *init)
808 {
809 drm_mga_private_t *dev_priv;
810 int ret;
811 DRM_DEBUG("\n");
812
813 dev_priv = dev->dev_private;
814
815 if (init->sgram)
816 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
817 else
818 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
819 dev_priv->maccess = init->maccess;
820
821 dev_priv->fb_cpp = init->fb_cpp;
822 dev_priv->front_offset = init->front_offset;
823 dev_priv->front_pitch = init->front_pitch;
824 dev_priv->back_offset = init->back_offset;
825 dev_priv->back_pitch = init->back_pitch;
826
827 dev_priv->depth_cpp = init->depth_cpp;
828 dev_priv->depth_offset = init->depth_offset;
829 dev_priv->depth_pitch = init->depth_pitch;
830
831 /* FIXME: Need to support AGP textures...
832 */
833 dev_priv->texture_offset = init->texture_offset[0];
834 dev_priv->texture_size = init->texture_size[0];
835
836 dev_priv->sarea = drm_legacy_getsarea(dev);
837 if (!dev_priv->sarea) {
838 DRM_ERROR("failed to find sarea!\n");
839 return -EINVAL;
840 }
841
842 if (!dev_priv->used_new_dma_init) {
843
844 dev_priv->dma_access = MGA_PAGPXFER;
845 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
846
847 dev_priv->status = drm_legacy_findmap(dev, init->status_offset);
848 if (!dev_priv->status) {
849 DRM_ERROR("failed to find status page!\n");
850 return -EINVAL;
851 }
852 dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
853 if (!dev_priv->mmio) {
854 DRM_ERROR("failed to find mmio region!\n");
855 return -EINVAL;
856 }
857 dev_priv->warp = drm_legacy_findmap(dev, init->warp_offset);
858 if (!dev_priv->warp) {
859 DRM_ERROR("failed to find warp microcode region!\n");
860 return -EINVAL;
861 }
862 dev_priv->primary = drm_legacy_findmap(dev, init->primary_offset);
863 if (!dev_priv->primary) {
864 DRM_ERROR("failed to find primary dma region!\n");
865 return -EINVAL;
866 }
867 dev->agp_buffer_token = init->buffers_offset;
868 dev->agp_buffer_map =
869 drm_legacy_findmap(dev, init->buffers_offset);
870 if (!dev->agp_buffer_map) {
871 DRM_ERROR("failed to find dma buffer region!\n");
872 return -EINVAL;
873 }
874
875 drm_legacy_ioremap(dev_priv->warp, dev);
876 drm_legacy_ioremap(dev_priv->primary, dev);
877 drm_legacy_ioremap(dev->agp_buffer_map, dev);
878 }
879
880 dev_priv->sarea_priv =
881 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
882 init->sarea_priv_offset);
883
884 if (!dev_priv->warp->handle ||
885 !dev_priv->primary->handle ||
886 ((dev_priv->dma_access != 0) &&
887 ((dev->agp_buffer_map == NULL) ||
888 (dev->agp_buffer_map->handle == NULL)))) {
889 DRM_ERROR("failed to ioremap agp regions!\n");
890 return -ENOMEM;
891 }
892
893 ret = mga_warp_install_microcode(dev_priv);
894 if (ret < 0) {
895 DRM_ERROR("failed to install WARP ucode!: %d\n", ret);
896 return ret;
897 }
898
899 ret = mga_warp_init(dev_priv);
900 if (ret < 0) {
901 DRM_ERROR("failed to init WARP engine!: %d\n", ret);
902 return ret;
903 }
904
905 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
906
907 mga_do_wait_for_idle(dev_priv);
908
909 /* Init the primary DMA registers.
910 */
911 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
912 #if 0
913 MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 | /* Soft trap, SECEND, SETUPEND */
914 MGA_PRIMPTREN1); /* DWGSYNC */
915 #endif
916
917 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
918 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
919 + dev_priv->primary->size);
920 dev_priv->prim.size = dev_priv->primary->size;
921
922 dev_priv->prim.tail = 0;
923 dev_priv->prim.space = dev_priv->prim.size;
924 dev_priv->prim.wrapped = 0;
925
926 dev_priv->prim.last_flush = 0;
927 dev_priv->prim.last_wrap = 0;
928
929 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
930
931 dev_priv->prim.status[0] = dev_priv->primary->offset;
932 dev_priv->prim.status[1] = 0;
933
934 dev_priv->sarea_priv->last_wrap = 0;
935 dev_priv->sarea_priv->last_frame.head = 0;
936 dev_priv->sarea_priv->last_frame.wrap = 0;
937
938 if (mga_freelist_init(dev, dev_priv) < 0) {
939 DRM_ERROR("could not initialize freelist\n");
940 return -ENOMEM;
941 }
942
943 return 0;
944 }
945
mga_do_cleanup_dma(struct drm_device * dev,int full_cleanup)946 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
947 {
948 int err = 0;
949 DRM_DEBUG("\n");
950
951 /* Make sure interrupts are disabled here because the uninstall ioctl
952 * may not have been called from userspace and after dev_private
953 * is freed, it's too late.
954 */
955 if (dev->irq_enabled)
956 drm_irq_uninstall(dev);
957
958 if (dev->dev_private) {
959 drm_mga_private_t *dev_priv = dev->dev_private;
960
961 if ((dev_priv->warp != NULL)
962 && (dev_priv->warp->type != _DRM_CONSISTENT))
963 drm_legacy_ioremapfree(dev_priv->warp, dev);
964
965 if ((dev_priv->primary != NULL)
966 && (dev_priv->primary->type != _DRM_CONSISTENT))
967 drm_legacy_ioremapfree(dev_priv->primary, dev);
968
969 if (dev->agp_buffer_map != NULL)
970 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
971
972 if (dev_priv->used_new_dma_init) {
973 #if IS_ENABLED(CONFIG_AGP)
974 if (dev_priv->agp_handle != 0) {
975 struct drm_agp_binding unbind_req;
976 struct drm_agp_buffer free_req;
977
978 unbind_req.handle = dev_priv->agp_handle;
979 drm_agp_unbind(dev, &unbind_req);
980
981 free_req.handle = dev_priv->agp_handle;
982 drm_agp_free(dev, &free_req);
983
984 dev_priv->agp_textures = NULL;
985 dev_priv->agp_size = 0;
986 dev_priv->agp_handle = 0;
987 }
988
989 if ((dev->agp != NULL) && dev->agp->acquired)
990 err = drm_agp_release(dev);
991 #endif
992 }
993
994 dev_priv->warp = NULL;
995 dev_priv->primary = NULL;
996 dev_priv->sarea = NULL;
997 dev_priv->sarea_priv = NULL;
998 dev->agp_buffer_map = NULL;
999
1000 if (full_cleanup) {
1001 dev_priv->mmio = NULL;
1002 dev_priv->status = NULL;
1003 dev_priv->used_new_dma_init = 0;
1004 }
1005
1006 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
1007 dev_priv->warp_pipe = 0;
1008 memset(dev_priv->warp_pipe_phys, 0,
1009 sizeof(dev_priv->warp_pipe_phys));
1010
1011 if (dev_priv->head != NULL)
1012 mga_freelist_cleanup(dev);
1013 }
1014
1015 return err;
1016 }
1017
mga_dma_init(struct drm_device * dev,void * data,struct drm_file * file_priv)1018 int mga_dma_init(struct drm_device *dev, void *data,
1019 struct drm_file *file_priv)
1020 {
1021 drm_mga_init_t *init = data;
1022 int err;
1023
1024 LOCK_TEST_WITH_RETURN(dev, file_priv);
1025
1026 switch (init->func) {
1027 case MGA_INIT_DMA:
1028 err = mga_do_init_dma(dev, init);
1029 if (err)
1030 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1031 return err;
1032 case MGA_CLEANUP_DMA:
1033 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1034 }
1035
1036 return -EINVAL;
1037 }
1038
1039 /* ================================================================
1040 * Primary DMA stream management
1041 */
1042
mga_dma_flush(struct drm_device * dev,void * data,struct drm_file * file_priv)1043 int mga_dma_flush(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv)
1045 {
1046 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1047 struct drm_lock *lock = data;
1048
1049 LOCK_TEST_WITH_RETURN(dev, file_priv);
1050
1051 DRM_DEBUG("%s%s%s\n",
1052 (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1053 (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1054 (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1055
1056 WRAP_WAIT_WITH_RETURN(dev_priv);
1057
1058 if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL))
1059 mga_do_dma_flush(dev_priv);
1060
1061 if (lock->flags & _DRM_LOCK_QUIESCENT) {
1062 #if MGA_DMA_DEBUG
1063 int ret = mga_do_wait_for_idle(dev_priv);
1064 if (ret < 0)
1065 DRM_INFO("-EBUSY\n");
1066 return ret;
1067 #else
1068 return mga_do_wait_for_idle(dev_priv);
1069 #endif
1070 } else {
1071 return 0;
1072 }
1073 }
1074
mga_dma_reset(struct drm_device * dev,void * data,struct drm_file * file_priv)1075 int mga_dma_reset(struct drm_device *dev, void *data,
1076 struct drm_file *file_priv)
1077 {
1078 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1079
1080 LOCK_TEST_WITH_RETURN(dev, file_priv);
1081
1082 return mga_do_dma_reset(dev_priv);
1083 }
1084
1085 /* ================================================================
1086 * DMA buffer management
1087 */
1088
mga_dma_get_buffers(struct drm_device * dev,struct drm_file * file_priv,struct drm_dma * d)1089 static int mga_dma_get_buffers(struct drm_device *dev,
1090 struct drm_file *file_priv, struct drm_dma *d)
1091 {
1092 struct drm_buf *buf;
1093 int i;
1094
1095 for (i = d->granted_count; i < d->request_count; i++) {
1096 buf = mga_freelist_get(dev);
1097 if (!buf)
1098 return -EAGAIN;
1099
1100 buf->file_priv = file_priv;
1101
1102 if (copy_to_user(&d->request_indices[i],
1103 &buf->idx, sizeof(buf->idx)))
1104 return -EFAULT;
1105 if (copy_to_user(&d->request_sizes[i],
1106 &buf->total, sizeof(buf->total)))
1107 return -EFAULT;
1108
1109 d->granted_count++;
1110 }
1111 return 0;
1112 }
1113
mga_dma_buffers(struct drm_device * dev,void * data,struct drm_file * file_priv)1114 int mga_dma_buffers(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv)
1116 {
1117 struct drm_device_dma *dma = dev->dma;
1118 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1119 struct drm_dma *d = data;
1120 int ret = 0;
1121
1122 LOCK_TEST_WITH_RETURN(dev, file_priv);
1123
1124 /* Please don't send us buffers.
1125 */
1126 if (d->send_count != 0) {
1127 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1128 task_pid_nr(current), d->send_count);
1129 return -EINVAL;
1130 }
1131
1132 /* We'll send you buffers.
1133 */
1134 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1135 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1136 task_pid_nr(current), d->request_count,
1137 dma->buf_count);
1138 return -EINVAL;
1139 }
1140
1141 WRAP_TEST_WITH_RETURN(dev_priv);
1142
1143 d->granted_count = 0;
1144
1145 if (d->request_count)
1146 ret = mga_dma_get_buffers(dev, file_priv, d);
1147
1148 return ret;
1149 }
1150
1151 /**
1152 * Called just before the module is unloaded.
1153 */
mga_driver_unload(struct drm_device * dev)1154 void mga_driver_unload(struct drm_device *dev)
1155 {
1156 kfree(dev->dev_private);
1157 dev->dev_private = NULL;
1158 }
1159
1160 /**
1161 * Called when the last opener of the device is closed.
1162 */
mga_driver_lastclose(struct drm_device * dev)1163 void mga_driver_lastclose(struct drm_device *dev)
1164 {
1165 mga_do_cleanup_dma(dev, FULL_CLEANUP);
1166 }
1167
mga_driver_dma_quiescent(struct drm_device * dev)1168 int mga_driver_dma_quiescent(struct drm_device *dev)
1169 {
1170 drm_mga_private_t *dev_priv = dev->dev_private;
1171 return mga_do_wait_for_idle(dev_priv);
1172 }
1173