1 /* $NetBSD: mga_drv.h,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */
2
3 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
4 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
5 *
6 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
7 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * All rights reserved.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the next
18 * paragraph) shall be included in all copies or substantial portions of the
19 * Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
25 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
26 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
27 * OTHER DEALINGS IN THE SOFTWARE.
28 *
29 * Authors:
30 * Gareth Hughes <gareth@valinux.com>
31 */
32
33 #ifndef __MGA_DRV_H__
34 #define __MGA_DRV_H__
35
36 #include <linux/irqreturn.h>
37 #include <linux/pci.h>
38 #include <linux/slab.h>
39
40 #include <drm/drm_agpsupport.h>
41 #include <drm/drm_device.h>
42 #include <drm/drm_file.h>
43 #include <drm/drm_ioctl.h>
44 #include <drm/drm_irq.h>
45 #include <drm/drm_legacy.h>
46 #include <drm/drm_print.h>
47 #include <drm/drm_sarea.h>
48 #include <drm/drm_vblank.h>
49 #include <drm/mga_drm.h>
50
51 /* General customization:
52 */
53
54 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc."
55
56 #define DRIVER_NAME "mga"
57 #define DRIVER_DESC "Matrox G200/G400"
58 #define DRIVER_DATE "20051102"
59
60 #define DRIVER_MAJOR 3
61 #define DRIVER_MINOR 2
62 #define DRIVER_PATCHLEVEL 1
63
64 typedef struct drm_mga_primary_buffer {
65 u8 *start;
66 u8 *end;
67 int size;
68
69 u32 tail;
70 int space;
71 volatile long wrapped;
72
73 volatile u32 *status;
74
75 u32 last_flush;
76 u32 last_wrap;
77
78 u32 high_mark;
79 } drm_mga_primary_buffer_t;
80
81 typedef struct drm_mga_freelist {
82 struct drm_mga_freelist *next;
83 struct drm_mga_freelist *prev;
84 drm_mga_age_t age;
85 struct drm_buf *buf;
86 } drm_mga_freelist_t;
87
88 typedef struct {
89 drm_mga_freelist_t *list_entry;
90 int discard;
91 int dispatched;
92 } drm_mga_buf_priv_t;
93
94 typedef struct drm_mga_private {
95 drm_mga_primary_buffer_t prim;
96 drm_mga_sarea_t *sarea_priv;
97
98 drm_mga_freelist_t *head;
99 drm_mga_freelist_t *tail;
100
101 unsigned int warp_pipe;
102 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
103
104 int chipset;
105 int usec_timeout;
106
107 /**
108 * If set, the new DMA initialization sequence was used. This is
109 * primarilly used to select how the driver should uninitialized its
110 * internal DMA structures.
111 */
112 int used_new_dma_init;
113
114 /**
115 * If AGP memory is used for DMA buffers, this will be the value
116 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer).
117 */
118 u32 dma_access;
119
120 /**
121 * If AGP memory is used for DMA buffers, this will be the value
122 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI
123 * transfer).
124 */
125 u32 wagp_enable;
126
127 /**
128 * \name MMIO region parameters.
129 *
130 * \sa drm_mga_private_t::mmio
131 */
132 /*@{ */
133 resource_size_t mmio_base; /**< Bus address of base of MMIO. */
134 resource_size_t mmio_size; /**< Size of the MMIO region. */
135 /*@} */
136
137 u32 clear_cmd;
138 u32 maccess;
139
140 atomic_t vbl_received; /**< Number of vblanks received. */
141 wait_queue_head_t fence_queue;
142 atomic_t last_fence_retired;
143 u32 next_fence_to_post;
144
145 unsigned int fb_cpp;
146 unsigned int front_offset;
147 unsigned int front_pitch;
148 unsigned int back_offset;
149 unsigned int back_pitch;
150
151 unsigned int depth_cpp;
152 unsigned int depth_offset;
153 unsigned int depth_pitch;
154
155 unsigned int texture_offset;
156 unsigned int texture_size;
157
158 drm_local_map_t *sarea;
159 drm_local_map_t *mmio;
160 drm_local_map_t *status;
161 drm_local_map_t *warp;
162 drm_local_map_t *primary;
163 drm_local_map_t *agp_textures;
164
165 unsigned long agp_handle;
166 unsigned int agp_size;
167 } drm_mga_private_t;
168
169 extern const struct drm_ioctl_desc mga_ioctls[];
170 extern int mga_max_ioctl;
171
172 /* mga_dma.c */
173 extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
174 struct drm_file *file_priv);
175 extern int mga_dma_init(struct drm_device *dev, void *data,
176 struct drm_file *file_priv);
177 extern int mga_getparam(struct drm_device *dev, void *data,
178 struct drm_file *file_priv);
179 extern int mga_dma_flush(struct drm_device *dev, void *data,
180 struct drm_file *file_priv);
181 extern int mga_dma_reset(struct drm_device *dev, void *data,
182 struct drm_file *file_priv);
183 extern int mga_dma_buffers(struct drm_device *dev, void *data,
184 struct drm_file *file_priv);
185 extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
186 extern void mga_driver_unload(struct drm_device *dev);
187 extern void mga_driver_lastclose(struct drm_device *dev);
188 extern int mga_driver_dma_quiescent(struct drm_device *dev);
189
190 extern int mga_do_wait_for_idle(drm_mga_private_t *dev_priv);
191
192 extern void mga_do_dma_flush(drm_mga_private_t *dev_priv);
193 extern void mga_do_dma_wrap_start(drm_mga_private_t *dev_priv);
194 extern void mga_do_dma_wrap_end(drm_mga_private_t *dev_priv);
195
196 extern int mga_freelist_put(struct drm_device *dev, struct drm_buf *buf);
197
198 /* mga_warp.c */
199 extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv);
200 extern int mga_warp_init(drm_mga_private_t *dev_priv);
201
202 /* mga_irq.c */
203 extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe);
204 extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe);
205 extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
206 extern void mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence);
207 extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
208 extern irqreturn_t mga_driver_irq_handler(int irq, void *arg);
209 extern void mga_driver_irq_preinstall(struct drm_device *dev);
210 extern int mga_driver_irq_postinstall(struct drm_device *dev);
211 extern void mga_driver_irq_uninstall(struct drm_device *dev);
212 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
213 unsigned long arg);
214
215 #define mga_flush_write_combine() wmb()
216
217 #define MGA_READ8(reg) \
218 readb(((void __iomem *)dev_priv->mmio->handle) + (reg))
219 #define MGA_READ(reg) \
220 readl(((void __iomem *)dev_priv->mmio->handle) + (reg))
221 #define MGA_WRITE8(reg, val) \
222 writeb(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
223 #define MGA_WRITE(reg, val) \
224 writel(val, ((void __iomem *)dev_priv->mmio->handle) + (reg))
225
226 #define DWGREG0 0x1c00
227 #define DWGREG0_END 0x1dff
228 #define DWGREG1 0x2c00
229 #define DWGREG1_END 0x2dff
230
231 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
232 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
233 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
234 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
235
236 /* ================================================================
237 * Helper macross...
238 */
239
240 #define MGA_EMIT_STATE(dev_priv, dirty) \
241 do { \
242 if ((dirty) & ~MGA_UPLOAD_CLIPRECTS) { \
243 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) \
244 mga_g400_emit_state(dev_priv); \
245 else \
246 mga_g200_emit_state(dev_priv); \
247 } \
248 } while (0)
249
250 #define WRAP_TEST_WITH_RETURN(dev_priv) \
251 do { \
252 if (test_bit(0, &dev_priv->prim.wrapped)) { \
253 if (mga_is_idle(dev_priv)) { \
254 mga_do_dma_wrap_end(dev_priv); \
255 } else if (dev_priv->prim.space < \
256 dev_priv->prim.high_mark) { \
257 if (MGA_DMA_DEBUG) \
258 DRM_INFO("wrap...\n"); \
259 return -EBUSY; \
260 } \
261 } \
262 } while (0)
263
264 #define WRAP_WAIT_WITH_RETURN(dev_priv) \
265 do { \
266 if (test_bit(0, &dev_priv->prim.wrapped)) { \
267 if (mga_do_wait_for_idle(dev_priv) < 0) { \
268 if (MGA_DMA_DEBUG) \
269 DRM_INFO("wrap...\n"); \
270 return -EBUSY; \
271 } \
272 mga_do_dma_wrap_end(dev_priv); \
273 } \
274 } while (0)
275
276 /* ================================================================
277 * Primary DMA command stream
278 */
279
280 #define MGA_VERBOSE 0
281
282 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
283
284 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
285
286 #define BEGIN_DMA(n) \
287 do { \
288 if (MGA_VERBOSE) { \
289 DRM_INFO("BEGIN_DMA(%d)\n", (n)); \
290 DRM_INFO(" space=0x%x req=0x%zx\n", \
291 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE); \
292 } \
293 prim = dev_priv->prim.start; \
294 write = dev_priv->prim.tail; \
295 } while (0)
296
297 #define BEGIN_DMA_WRAP() \
298 do { \
299 if (MGA_VERBOSE) { \
300 DRM_INFO("BEGIN_DMA()\n"); \
301 DRM_INFO(" space=0x%x\n", dev_priv->prim.space); \
302 } \
303 prim = dev_priv->prim.start; \
304 write = dev_priv->prim.tail; \
305 } while (0)
306
307 #define ADVANCE_DMA() \
308 do { \
309 dev_priv->prim.tail = write; \
310 if (MGA_VERBOSE) \
311 DRM_INFO("ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
312 write, dev_priv->prim.space); \
313 } while (0)
314
315 #define FLUSH_DMA() \
316 do { \
317 if (0) { \
318 DRM_INFO("\n"); \
319 DRM_INFO(" tail=0x%06x head=0x%06lx\n", \
320 dev_priv->prim.tail, \
321 (unsigned long)(MGA_READ(MGA_PRIMADDRESS) - \
322 dev_priv->primary->offset)); \
323 } \
324 if (!test_bit(0, &dev_priv->prim.wrapped)) { \
325 if (dev_priv->prim.space < dev_priv->prim.high_mark) \
326 mga_do_dma_wrap_start(dev_priv); \
327 else \
328 mga_do_dma_flush(dev_priv); \
329 } \
330 } while (0)
331
332 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
333 */
334 #define DMA_WRITE(offset, val) \
335 do { \
336 if (MGA_VERBOSE) \
337 DRM_INFO(" DMA_WRITE( 0x%08x ) at 0x%04zx\n", \
338 (u32)(val), write + (offset) * sizeof(u32)); \
339 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
340 } while (0)
341
342 #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \
343 do { \
344 DMA_WRITE(0, ((DMAREG(reg0) << 0) | \
345 (DMAREG(reg1) << 8) | \
346 (DMAREG(reg2) << 16) | \
347 (DMAREG(reg3) << 24))); \
348 DMA_WRITE(1, val0); \
349 DMA_WRITE(2, val1); \
350 DMA_WRITE(3, val2); \
351 DMA_WRITE(4, val3); \
352 write += DMA_BLOCK_SIZE; \
353 } while (0)
354
355 /* Buffer aging via primary DMA stream head pointer.
356 */
357
358 #define SET_AGE(age, h, w) \
359 do { \
360 (age)->head = h; \
361 (age)->wrap = w; \
362 } while (0)
363
364 #define TEST_AGE(age, h, w) ((age)->wrap < w || \
365 ((age)->wrap == w && \
366 (age)->head < h))
367
368 #define AGE_BUFFER(buf_priv) \
369 do { \
370 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
371 if ((buf_priv)->dispatched) { \
372 entry->age.head = (dev_priv->prim.tail + \
373 dev_priv->primary->offset); \
374 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
375 } else { \
376 entry->age.head = 0; \
377 entry->age.wrap = 0; \
378 } \
379 } while (0)
380
381 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
382 MGA_DWGENGSTS | \
383 MGA_ENDPRDMASTS)
384 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
385 MGA_ENDPRDMASTS)
386
387 #define MGA_DMA_DEBUG 0
388
389 /* A reduced set of the mga registers.
390 */
391 #define MGA_CRTC_INDEX 0x1fd4
392 #define MGA_CRTC_DATA 0x1fd5
393
394 /* CRTC11 */
395 #define MGA_VINTCLR (1 << 4)
396 #define MGA_VINTEN (1 << 5)
397
398 #define MGA_ALPHACTRL 0x2c7c
399 #define MGA_AR0 0x1c60
400 #define MGA_AR1 0x1c64
401 #define MGA_AR2 0x1c68
402 #define MGA_AR3 0x1c6c
403 #define MGA_AR4 0x1c70
404 #define MGA_AR5 0x1c74
405 #define MGA_AR6 0x1c78
406
407 #define MGA_CXBNDRY 0x1c80
408 #define MGA_CXLEFT 0x1ca0
409 #define MGA_CXRIGHT 0x1ca4
410
411 #define MGA_DMAPAD 0x1c54
412 #define MGA_DSTORG 0x2cb8
413 #define MGA_DWGCTL 0x1c00
414 # define MGA_OPCOD_MASK (15 << 0)
415 # define MGA_OPCOD_TRAP (4 << 0)
416 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
417 # define MGA_OPCOD_BITBLT (8 << 0)
418 # define MGA_OPCOD_ILOAD (9 << 0)
419 # define MGA_ATYPE_MASK (7 << 4)
420 # define MGA_ATYPE_RPL (0 << 4)
421 # define MGA_ATYPE_RSTR (1 << 4)
422 # define MGA_ATYPE_ZI (3 << 4)
423 # define MGA_ATYPE_BLK (4 << 4)
424 # define MGA_ATYPE_I (7 << 4)
425 # define MGA_LINEAR (1 << 7)
426 # define MGA_ZMODE_MASK (7 << 8)
427 # define MGA_ZMODE_NOZCMP (0 << 8)
428 # define MGA_ZMODE_ZE (2 << 8)
429 # define MGA_ZMODE_ZNE (3 << 8)
430 # define MGA_ZMODE_ZLT (4 << 8)
431 # define MGA_ZMODE_ZLTE (5 << 8)
432 # define MGA_ZMODE_ZGT (6 << 8)
433 # define MGA_ZMODE_ZGTE (7 << 8)
434 # define MGA_SOLID (1 << 11)
435 # define MGA_ARZERO (1 << 12)
436 # define MGA_SGNZERO (1 << 13)
437 # define MGA_SHIFTZERO (1 << 14)
438 # define MGA_BOP_MASK (15 << 16)
439 # define MGA_BOP_ZERO (0 << 16)
440 # define MGA_BOP_DST (10 << 16)
441 # define MGA_BOP_SRC (12 << 16)
442 # define MGA_BOP_ONE (15 << 16)
443 # define MGA_TRANS_SHIFT 20
444 # define MGA_TRANS_MASK (15 << 20)
445 # define MGA_BLTMOD_MASK (15 << 25)
446 # define MGA_BLTMOD_BMONOLEF (0 << 25)
447 # define MGA_BLTMOD_BMONOWF (4 << 25)
448 # define MGA_BLTMOD_PLAN (1 << 25)
449 # define MGA_BLTMOD_BFCOL (2 << 25)
450 # define MGA_BLTMOD_BU32BGR (3 << 25)
451 # define MGA_BLTMOD_BU32RGB (7 << 25)
452 # define MGA_BLTMOD_BU24BGR (11 << 25)
453 # define MGA_BLTMOD_BU24RGB (15 << 25)
454 # define MGA_PATTERN (1 << 29)
455 # define MGA_TRANSC (1 << 30)
456 # define MGA_CLIPDIS (1 << 31)
457 #define MGA_DWGSYNC 0x2c4c
458
459 #define MGA_FCOL 0x1c24
460 #define MGA_FIFOSTATUS 0x1e10
461 #define MGA_FOGCOL 0x1cf4
462 #define MGA_FXBNDRY 0x1c84
463 #define MGA_FXLEFT 0x1ca8
464 #define MGA_FXRIGHT 0x1cac
465
466 #define MGA_ICLEAR 0x1e18
467 # define MGA_SOFTRAPICLR (1 << 0)
468 # define MGA_VLINEICLR (1 << 5)
469 #define MGA_IEN 0x1e1c
470 # define MGA_SOFTRAPIEN (1 << 0)
471 # define MGA_VLINEIEN (1 << 5)
472
473 #define MGA_LEN 0x1c5c
474
475 #define MGA_MACCESS 0x1c04
476
477 #define MGA_PITCH 0x1c8c
478 #define MGA_PLNWT 0x1c1c
479 #define MGA_PRIMADDRESS 0x1e58
480 # define MGA_DMA_GENERAL (0 << 0)
481 # define MGA_DMA_BLIT (1 << 0)
482 # define MGA_DMA_VECTOR (2 << 0)
483 # define MGA_DMA_VERTEX (3 << 0)
484 #define MGA_PRIMEND 0x1e5c
485 # define MGA_PRIMNOSTART (1 << 0)
486 # define MGA_PAGPXFER (1 << 1)
487 #define MGA_PRIMPTR 0x1e50
488 # define MGA_PRIMPTREN0 (1 << 0)
489 # define MGA_PRIMPTREN1 (1 << 1)
490
491 #define MGA_RST 0x1e40
492 # define MGA_SOFTRESET (1 << 0)
493 # define MGA_SOFTEXTRST (1 << 1)
494
495 #define MGA_SECADDRESS 0x2c40
496 #define MGA_SECEND 0x2c44
497 #define MGA_SETUPADDRESS 0x2cd0
498 #define MGA_SETUPEND 0x2cd4
499 #define MGA_SGN 0x1c58
500 #define MGA_SOFTRAP 0x2c48
501 #define MGA_SRCORG 0x2cb4
502 # define MGA_SRMMAP_MASK (1 << 0)
503 # define MGA_SRCMAP_FB (0 << 0)
504 # define MGA_SRCMAP_SYSMEM (1 << 0)
505 # define MGA_SRCACC_MASK (1 << 1)
506 # define MGA_SRCACC_PCI (0 << 1)
507 # define MGA_SRCACC_AGP (1 << 1)
508 #define MGA_STATUS 0x1e14
509 # define MGA_SOFTRAPEN (1 << 0)
510 # define MGA_VSYNCPEN (1 << 4)
511 # define MGA_VLINEPEN (1 << 5)
512 # define MGA_DWGENGSTS (1 << 16)
513 # define MGA_ENDPRDMASTS (1 << 17)
514 #define MGA_STENCIL 0x2cc8
515 #define MGA_STENCILCTL 0x2ccc
516
517 #define MGA_TDUALSTAGE0 0x2cf8
518 #define MGA_TDUALSTAGE1 0x2cfc
519 #define MGA_TEXBORDERCOL 0x2c5c
520 #define MGA_TEXCTL 0x2c30
521 #define MGA_TEXCTL2 0x2c3c
522 # define MGA_DUALTEX (1 << 7)
523 # define MGA_G400_TC2_MAGIC (1 << 15)
524 # define MGA_MAP1_ENABLE (1 << 31)
525 #define MGA_TEXFILTER 0x2c58
526 #define MGA_TEXHEIGHT 0x2c2c
527 #define MGA_TEXORG 0x2c24
528 # define MGA_TEXORGMAP_MASK (1 << 0)
529 # define MGA_TEXORGMAP_FB (0 << 0)
530 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
531 # define MGA_TEXORGACC_MASK (1 << 1)
532 # define MGA_TEXORGACC_PCI (0 << 1)
533 # define MGA_TEXORGACC_AGP (1 << 1)
534 #define MGA_TEXORG1 0x2ca4
535 #define MGA_TEXORG2 0x2ca8
536 #define MGA_TEXORG3 0x2cac
537 #define MGA_TEXORG4 0x2cb0
538 #define MGA_TEXTRANS 0x2c34
539 #define MGA_TEXTRANSHIGH 0x2c38
540 #define MGA_TEXWIDTH 0x2c28
541
542 #define MGA_WACCEPTSEQ 0x1dd4
543 #define MGA_WCODEADDR 0x1e6c
544 #define MGA_WFLAG 0x1dc4
545 #define MGA_WFLAG1 0x1de0
546 #define MGA_WFLAGNB 0x1e64
547 #define MGA_WFLAGNB1 0x1e08
548 #define MGA_WGETMSB 0x1dc8
549 #define MGA_WIADDR 0x1dc0
550 #define MGA_WIADDR2 0x1dd8
551 # define MGA_WMODE_SUSPEND (0 << 0)
552 # define MGA_WMODE_RESUME (1 << 0)
553 # define MGA_WMODE_JUMP (2 << 0)
554 # define MGA_WMODE_START (3 << 0)
555 # define MGA_WAGP_ENABLE (1 << 2)
556 #define MGA_WMISC 0x1e70
557 # define MGA_WUCODECACHE_ENABLE (1 << 0)
558 # define MGA_WMASTER_ENABLE (1 << 1)
559 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
560 #define MGA_WVRTXSZ 0x1dcc
561
562 #define MGA_YBOT 0x1c9c
563 #define MGA_YDST 0x1c90
564 #define MGA_YDSTLEN 0x1c88
565 #define MGA_YDSTORG 0x1c94
566 #define MGA_YTOP 0x1c98
567
568 #define MGA_ZORG 0x1c0c
569
570 /* This finishes the current batch of commands
571 */
572 #define MGA_EXEC 0x0100
573
574 /* AGP PLL encoding (for G200 only).
575 */
576 #define MGA_AGP_PLL 0x1e4c
577 # define MGA_AGP2XPLL_DISABLE (0 << 0)
578 # define MGA_AGP2XPLL_ENABLE (1 << 0)
579
580 /* Warp registers
581 */
582 #define MGA_WR0 0x2d00
583 #define MGA_WR1 0x2d04
584 #define MGA_WR2 0x2d08
585 #define MGA_WR3 0x2d0c
586 #define MGA_WR4 0x2d10
587 #define MGA_WR5 0x2d14
588 #define MGA_WR6 0x2d18
589 #define MGA_WR7 0x2d1c
590 #define MGA_WR8 0x2d20
591 #define MGA_WR9 0x2d24
592 #define MGA_WR10 0x2d28
593 #define MGA_WR11 0x2d2c
594 #define MGA_WR12 0x2d30
595 #define MGA_WR13 0x2d34
596 #define MGA_WR14 0x2d38
597 #define MGA_WR15 0x2d3c
598 #define MGA_WR16 0x2d40
599 #define MGA_WR17 0x2d44
600 #define MGA_WR18 0x2d48
601 #define MGA_WR19 0x2d4c
602 #define MGA_WR20 0x2d50
603 #define MGA_WR21 0x2d54
604 #define MGA_WR22 0x2d58
605 #define MGA_WR23 0x2d5c
606 #define MGA_WR24 0x2d60
607 #define MGA_WR25 0x2d64
608 #define MGA_WR26 0x2d68
609 #define MGA_WR27 0x2d6c
610 #define MGA_WR28 0x2d70
611 #define MGA_WR29 0x2d74
612 #define MGA_WR30 0x2d78
613 #define MGA_WR31 0x2d7c
614 #define MGA_WR32 0x2d80
615 #define MGA_WR33 0x2d84
616 #define MGA_WR34 0x2d88
617 #define MGA_WR35 0x2d8c
618 #define MGA_WR36 0x2d90
619 #define MGA_WR37 0x2d94
620 #define MGA_WR38 0x2d98
621 #define MGA_WR39 0x2d9c
622 #define MGA_WR40 0x2da0
623 #define MGA_WR41 0x2da4
624 #define MGA_WR42 0x2da8
625 #define MGA_WR43 0x2dac
626 #define MGA_WR44 0x2db0
627 #define MGA_WR45 0x2db4
628 #define MGA_WR46 0x2db8
629 #define MGA_WR47 0x2dbc
630 #define MGA_WR48 0x2dc0
631 #define MGA_WR49 0x2dc4
632 #define MGA_WR50 0x2dc8
633 #define MGA_WR51 0x2dcc
634 #define MGA_WR52 0x2dd0
635 #define MGA_WR53 0x2dd4
636 #define MGA_WR54 0x2dd8
637 #define MGA_WR55 0x2ddc
638 #define MGA_WR56 0x2de0
639 #define MGA_WR57 0x2de4
640 #define MGA_WR58 0x2de8
641 #define MGA_WR59 0x2dec
642 #define MGA_WR60 0x2df0
643 #define MGA_WR61 0x2df4
644 #define MGA_WR62 0x2df8
645 #define MGA_WR63 0x2dfc
646 # define MGA_G400_WR_MAGIC (1 << 6)
647 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
648
649 #define MGA_ILOAD_ALIGN 64
650 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
651
652 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
653 MGA_ATYPE_I | \
654 MGA_ZMODE_NOZCMP | \
655 MGA_ARZERO | \
656 MGA_SGNZERO | \
657 MGA_BOP_SRC | \
658 (15 << MGA_TRANS_SHIFT))
659
660 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
661 MGA_ZMODE_NOZCMP | \
662 MGA_SOLID | \
663 MGA_ARZERO | \
664 MGA_SGNZERO | \
665 MGA_SHIFTZERO | \
666 MGA_BOP_SRC | \
667 (0 << MGA_TRANS_SHIFT) | \
668 MGA_BLTMOD_BMONOLEF | \
669 MGA_TRANSC | \
670 MGA_CLIPDIS)
671
672 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
673 MGA_ATYPE_RPL | \
674 MGA_SGNZERO | \
675 MGA_SHIFTZERO | \
676 MGA_BOP_SRC | \
677 (0 << MGA_TRANS_SHIFT) | \
678 MGA_BLTMOD_BFCOL | \
679 MGA_CLIPDIS)
680
681 /* Simple idle test.
682 */
mga_is_idle(drm_mga_private_t * dev_priv)683 static __inline__ int mga_is_idle(drm_mga_private_t *dev_priv)
684 {
685 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
686 return (status == MGA_ENDPRDMASTS);
687 }
688
689 #endif
690