1 /* $NetBSD: r128_cce.c,v 1.3 2021/12/18 23:45:42 riastradh Exp $ */
2
3 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
4 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
5 */
6 /*
7 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
8 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
9 * All Rights Reserved.
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
20 * Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 *
30 * Authors:
31 * Gareth Hughes <gareth@valinux.com>
32 */
33
34 #include <sys/cdefs.h>
35 __KERNEL_RCSID(0, "$NetBSD: r128_cce.c,v 1.3 2021/12/18 23:45:42 riastradh Exp $");
36
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/firmware.h>
40 #include <linux/module.h>
41 #include <linux/platform_device.h>
42 #include <linux/slab.h>
43 #include <linux/uaccess.h>
44
45 #include <drm/drm_agpsupport.h>
46 #include <drm/drm_device.h>
47 #include <drm/drm_file.h>
48 #include <drm/drm_irq.h>
49 #include <drm/drm_print.h>
50 #include <drm/r128_drm.h>
51
52 #include "r128_drv.h"
53
54 #define R128_FIFO_DEBUG 0
55
56 #define FIRMWARE_NAME "r128/r128_cce.bin"
57
58 MODULE_FIRMWARE(FIRMWARE_NAME);
59
R128_READ_PLL(struct drm_device * dev,int addr)60 static int R128_READ_PLL(struct drm_device *dev, int addr)
61 {
62 drm_r128_private_t *dev_priv = dev->dev_private;
63
64 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
65 return R128_READ(R128_CLOCK_CNTL_DATA);
66 }
67
68 #if R128_FIFO_DEBUG
r128_status(drm_r128_private_t * dev_priv)69 static void r128_status(drm_r128_private_t *dev_priv)
70 {
71 printk("GUI_STAT = 0x%08x\n",
72 (unsigned int)R128_READ(R128_GUI_STAT));
73 printk("PM4_STAT = 0x%08x\n",
74 (unsigned int)R128_READ(R128_PM4_STAT));
75 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
76 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
77 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
78 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
79 printk("PM4_MICRO_CNTL = 0x%08x\n",
80 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
81 printk("PM4_BUFFER_CNTL = 0x%08x\n",
82 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
83 }
84 #endif
85
86 /* ================================================================
87 * Engine, FIFO control
88 */
89
r128_do_pixcache_flush(drm_r128_private_t * dev_priv)90 static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv)
91 {
92 u32 tmp;
93 int i;
94
95 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
96 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
97
98 for (i = 0; i < dev_priv->usec_timeout; i++) {
99 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
100 return 0;
101 udelay(1);
102 }
103
104 #if R128_FIFO_DEBUG
105 DRM_ERROR("failed!\n");
106 #endif
107 return -EBUSY;
108 }
109
r128_do_wait_for_fifo(drm_r128_private_t * dev_priv,int entries)110 static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries)
111 {
112 int i;
113
114 for (i = 0; i < dev_priv->usec_timeout; i++) {
115 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
116 if (slots >= entries)
117 return 0;
118 udelay(1);
119 }
120
121 #if R128_FIFO_DEBUG
122 DRM_ERROR("failed!\n");
123 #endif
124 return -EBUSY;
125 }
126
r128_do_wait_for_idle(drm_r128_private_t * dev_priv)127 static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv)
128 {
129 int i, ret;
130
131 ret = r128_do_wait_for_fifo(dev_priv, 64);
132 if (ret)
133 return ret;
134
135 for (i = 0; i < dev_priv->usec_timeout; i++) {
136 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
137 r128_do_pixcache_flush(dev_priv);
138 return 0;
139 }
140 udelay(1);
141 }
142
143 #if R128_FIFO_DEBUG
144 DRM_ERROR("failed!\n");
145 #endif
146 return -EBUSY;
147 }
148
149 /* ================================================================
150 * CCE control, initialization
151 */
152
153 /* Load the microcode for the CCE */
r128_cce_load_microcode(drm_r128_private_t * dev_priv)154 static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
155 {
156 struct platform_device *pdev;
157 const struct firmware *fw;
158 const __be32 *fw_data;
159 int rc, i;
160
161 DRM_DEBUG("\n");
162
163 pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
164 if (IS_ERR(pdev)) {
165 pr_err("r128_cce: Failed to register firmware\n");
166 return PTR_ERR(pdev);
167 }
168 rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
169 platform_device_unregister(pdev);
170 if (rc) {
171 pr_err("r128_cce: Failed to load firmware \"%s\"\n",
172 FIRMWARE_NAME);
173 return rc;
174 }
175
176 if (fw->size != 256 * 8) {
177 pr_err("r128_cce: Bogus length %zu in firmware \"%s\"\n",
178 fw->size, FIRMWARE_NAME);
179 rc = -EINVAL;
180 goto out_release;
181 }
182
183 r128_do_wait_for_idle(dev_priv);
184
185 fw_data = (const __be32 *)fw->data;
186 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
187 for (i = 0; i < 256; i++) {
188 R128_WRITE(R128_PM4_MICROCODE_DATAH,
189 be32_to_cpup(&fw_data[i * 2]));
190 R128_WRITE(R128_PM4_MICROCODE_DATAL,
191 be32_to_cpup(&fw_data[i * 2 + 1]));
192 }
193
194 out_release:
195 release_firmware(fw);
196 return rc;
197 }
198
199 /* Flush any pending commands to the CCE. This should only be used just
200 * prior to a wait for idle, as it informs the engine that the command
201 * stream is ending.
202 */
r128_do_cce_flush(drm_r128_private_t * dev_priv)203 static void r128_do_cce_flush(drm_r128_private_t *dev_priv)
204 {
205 u32 tmp;
206
207 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
208 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
209 }
210
211 /* Wait for the CCE to go idle.
212 */
r128_do_cce_idle(drm_r128_private_t * dev_priv)213 int r128_do_cce_idle(drm_r128_private_t *dev_priv)
214 {
215 int i;
216
217 for (i = 0; i < dev_priv->usec_timeout; i++) {
218 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
219 int pm4stat = R128_READ(R128_PM4_STAT);
220 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
221 dev_priv->cce_fifo_size) &&
222 !(pm4stat & (R128_PM4_BUSY |
223 R128_PM4_GUI_ACTIVE))) {
224 return r128_do_pixcache_flush(dev_priv);
225 }
226 }
227 udelay(1);
228 }
229
230 #if R128_FIFO_DEBUG
231 DRM_ERROR("failed!\n");
232 r128_status(dev_priv);
233 #endif
234 return -EBUSY;
235 }
236
237 /* Start the Concurrent Command Engine.
238 */
r128_do_cce_start(drm_r128_private_t * dev_priv)239 static void r128_do_cce_start(drm_r128_private_t *dev_priv)
240 {
241 r128_do_wait_for_idle(dev_priv);
242
243 R128_WRITE(R128_PM4_BUFFER_CNTL,
244 dev_priv->cce_mode | dev_priv->ring.size_l2qw
245 | R128_PM4_BUFFER_CNTL_NOUPDATE);
246 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
247 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
248
249 dev_priv->cce_running = 1;
250 }
251
252 /* Reset the Concurrent Command Engine. This will not flush any pending
253 * commands, so you must wait for the CCE command stream to complete
254 * before calling this routine.
255 */
r128_do_cce_reset(drm_r128_private_t * dev_priv)256 static void r128_do_cce_reset(drm_r128_private_t *dev_priv)
257 {
258 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
259 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
260 dev_priv->ring.tail = 0;
261 }
262
263 /* Stop the Concurrent Command Engine. This will not flush any pending
264 * commands, so you must flush the command stream and wait for the CCE
265 * to go idle before calling this routine.
266 */
r128_do_cce_stop(drm_r128_private_t * dev_priv)267 static void r128_do_cce_stop(drm_r128_private_t *dev_priv)
268 {
269 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
270 R128_WRITE(R128_PM4_BUFFER_CNTL,
271 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
272
273 dev_priv->cce_running = 0;
274 }
275
276 /* Reset the engine. This will stop the CCE if it is running.
277 */
r128_do_engine_reset(struct drm_device * dev)278 static int r128_do_engine_reset(struct drm_device *dev)
279 {
280 drm_r128_private_t *dev_priv = dev->dev_private;
281 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
282
283 r128_do_pixcache_flush(dev_priv);
284
285 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
286 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
287
288 R128_WRITE_PLL(R128_MCLK_CNTL,
289 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
290
291 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
292
293 /* Taken from the sample code - do not change */
294 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
295 R128_READ(R128_GEN_RESET_CNTL);
296 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
297 R128_READ(R128_GEN_RESET_CNTL);
298
299 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
300 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
301 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
302
303 /* Reset the CCE ring */
304 r128_do_cce_reset(dev_priv);
305
306 /* The CCE is no longer running after an engine reset */
307 dev_priv->cce_running = 0;
308
309 /* Reset any pending vertex, indirect buffers */
310 r128_freelist_reset(dev);
311
312 return 0;
313 }
314
r128_cce_init_ring_buffer(struct drm_device * dev,drm_r128_private_t * dev_priv)315 static void r128_cce_init_ring_buffer(struct drm_device *dev,
316 drm_r128_private_t *dev_priv)
317 {
318 u32 ring_start;
319 u32 tmp;
320
321 DRM_DEBUG("\n");
322
323 /* The manual (p. 2) says this address is in "VM space". This
324 * means it's an offset from the start of AGP space.
325 */
326 #if IS_ENABLED(CONFIG_AGP)
327 if (!dev_priv->is_pci)
328 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
329 else
330 #endif
331 ring_start = dev_priv->cce_ring->offset -
332 (unsigned long)dev->sg->virtual;
333
334 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
335
336 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
337 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
338
339 /* Set watermark control */
340 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
341 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
342 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
343 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
344 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
345
346 /* Force read. Why? Because it's in the examples... */
347 R128_READ(R128_PM4_BUFFER_ADDR);
348
349 /* Turn on bus mastering */
350 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
351 R128_WRITE(R128_BUS_CNTL, tmp);
352 }
353
r128_do_init_cce(struct drm_device * dev,drm_r128_init_t * init)354 static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init)
355 {
356 drm_r128_private_t *dev_priv;
357 int rc;
358
359 DRM_DEBUG("\n");
360
361 if (dev->dev_private) {
362 DRM_DEBUG("called when already initialized\n");
363 return -EINVAL;
364 }
365
366 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
367 if (dev_priv == NULL)
368 return -ENOMEM;
369
370 dev_priv->is_pci = init->is_pci;
371
372 if (dev_priv->is_pci && !dev->sg) {
373 DRM_ERROR("PCI GART memory not allocated!\n");
374 dev->dev_private = (void *)dev_priv;
375 r128_do_cleanup_cce(dev);
376 return -EINVAL;
377 }
378
379 dev_priv->usec_timeout = init->usec_timeout;
380 if (dev_priv->usec_timeout < 1 ||
381 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
382 DRM_DEBUG("TIMEOUT problem!\n");
383 dev->dev_private = (void *)dev_priv;
384 r128_do_cleanup_cce(dev);
385 return -EINVAL;
386 }
387
388 dev_priv->cce_mode = init->cce_mode;
389
390 /* GH: Simple idle check.
391 */
392 atomic_set(&dev_priv->idle_count, 0);
393
394 /* We don't support anything other than bus-mastering ring mode,
395 * but the ring can be in either AGP or PCI space for the ring
396 * read pointer.
397 */
398 if ((init->cce_mode != R128_PM4_192BM) &&
399 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
400 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
401 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
402 DRM_DEBUG("Bad cce_mode!\n");
403 dev->dev_private = (void *)dev_priv;
404 r128_do_cleanup_cce(dev);
405 return -EINVAL;
406 }
407
408 switch (init->cce_mode) {
409 case R128_PM4_NONPM4:
410 dev_priv->cce_fifo_size = 0;
411 break;
412 case R128_PM4_192PIO:
413 case R128_PM4_192BM:
414 dev_priv->cce_fifo_size = 192;
415 break;
416 case R128_PM4_128PIO_64INDBM:
417 case R128_PM4_128BM_64INDBM:
418 dev_priv->cce_fifo_size = 128;
419 break;
420 case R128_PM4_64PIO_128INDBM:
421 case R128_PM4_64BM_128INDBM:
422 case R128_PM4_64PIO_64VCBM_64INDBM:
423 case R128_PM4_64BM_64VCBM_64INDBM:
424 case R128_PM4_64PIO_64VCPIO_64INDPIO:
425 dev_priv->cce_fifo_size = 64;
426 break;
427 }
428
429 switch (init->fb_bpp) {
430 case 16:
431 dev_priv->color_fmt = R128_DATATYPE_RGB565;
432 break;
433 case 32:
434 default:
435 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
436 break;
437 }
438 dev_priv->front_offset = init->front_offset;
439 dev_priv->front_pitch = init->front_pitch;
440 dev_priv->back_offset = init->back_offset;
441 dev_priv->back_pitch = init->back_pitch;
442
443 switch (init->depth_bpp) {
444 case 16:
445 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
446 break;
447 case 24:
448 case 32:
449 default:
450 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
451 break;
452 }
453 dev_priv->depth_offset = init->depth_offset;
454 dev_priv->depth_pitch = init->depth_pitch;
455 dev_priv->span_offset = init->span_offset;
456
457 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
458 (dev_priv->front_offset >> 5));
459 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
460 (dev_priv->back_offset >> 5));
461 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
462 (dev_priv->depth_offset >> 5) |
463 R128_DST_TILE);
464 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
465 (dev_priv->span_offset >> 5));
466
467 dev_priv->sarea = drm_legacy_getsarea(dev);
468 if (!dev_priv->sarea) {
469 DRM_ERROR("could not find sarea!\n");
470 dev->dev_private = (void *)dev_priv;
471 r128_do_cleanup_cce(dev);
472 return -EINVAL;
473 }
474
475 dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
476 if (!dev_priv->mmio) {
477 DRM_ERROR("could not find mmio region!\n");
478 dev->dev_private = (void *)dev_priv;
479 r128_do_cleanup_cce(dev);
480 return -EINVAL;
481 }
482 dev_priv->cce_ring = drm_legacy_findmap(dev, init->ring_offset);
483 if (!dev_priv->cce_ring) {
484 DRM_ERROR("could not find cce ring region!\n");
485 dev->dev_private = (void *)dev_priv;
486 r128_do_cleanup_cce(dev);
487 return -EINVAL;
488 }
489 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
490 if (!dev_priv->ring_rptr) {
491 DRM_ERROR("could not find ring read pointer!\n");
492 dev->dev_private = (void *)dev_priv;
493 r128_do_cleanup_cce(dev);
494 return -EINVAL;
495 }
496 dev->agp_buffer_token = init->buffers_offset;
497 dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
498 if (!dev->agp_buffer_map) {
499 DRM_ERROR("could not find dma buffer region!\n");
500 dev->dev_private = (void *)dev_priv;
501 r128_do_cleanup_cce(dev);
502 return -EINVAL;
503 }
504
505 if (!dev_priv->is_pci) {
506 dev_priv->agp_textures =
507 drm_legacy_findmap(dev, init->agp_textures_offset);
508 if (!dev_priv->agp_textures) {
509 DRM_ERROR("could not find agp texture region!\n");
510 dev->dev_private = (void *)dev_priv;
511 r128_do_cleanup_cce(dev);
512 return -EINVAL;
513 }
514 }
515
516 dev_priv->sarea_priv =
517 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
518 init->sarea_priv_offset);
519
520 #if IS_ENABLED(CONFIG_AGP)
521 if (!dev_priv->is_pci) {
522 drm_legacy_ioremap_wc(dev_priv->cce_ring, dev);
523 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
524 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
525 if (!dev_priv->cce_ring->handle ||
526 !dev_priv->ring_rptr->handle ||
527 !dev->agp_buffer_map->handle) {
528 DRM_ERROR("Could not ioremap agp regions!\n");
529 dev->dev_private = (void *)dev_priv;
530 r128_do_cleanup_cce(dev);
531 return -ENOMEM;
532 }
533 } else
534 #endif
535 {
536 dev_priv->cce_ring->handle =
537 (void *)(unsigned long)dev_priv->cce_ring->offset;
538 dev_priv->ring_rptr->handle =
539 (void *)(unsigned long)dev_priv->ring_rptr->offset;
540 dev->agp_buffer_map->handle =
541 (void *)(unsigned long)dev->agp_buffer_map->offset;
542 }
543
544 #if IS_ENABLED(CONFIG_AGP)
545 if (!dev_priv->is_pci)
546 dev_priv->cce_buffers_offset = dev->agp->base;
547 else
548 #endif
549 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
550
551 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
552 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
553 + init->ring_size / sizeof(u32));
554 dev_priv->ring.size = init->ring_size;
555 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
556
557 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
558
559 dev_priv->ring.high_mark = 128;
560
561 dev_priv->sarea_priv->last_frame = 0;
562 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
563
564 dev_priv->sarea_priv->last_dispatch = 0;
565 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
566
567 #if IS_ENABLED(CONFIG_AGP)
568 if (dev_priv->is_pci) {
569 #endif
570 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
571 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
572 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
573 dev_priv->gart_info.addr = NULL;
574 dev_priv->gart_info.bus_addr = 0;
575 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
576 rc = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
577 if (rc) {
578 DRM_ERROR("failed to init PCI GART!\n");
579 dev->dev_private = (void *)dev_priv;
580 r128_do_cleanup_cce(dev);
581 return rc;
582 }
583 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
584 #if IS_ENABLED(CONFIG_AGP)
585 }
586 #endif
587
588 r128_cce_init_ring_buffer(dev, dev_priv);
589 rc = r128_cce_load_microcode(dev_priv);
590
591 dev->dev_private = (void *)dev_priv;
592
593 r128_do_engine_reset(dev);
594
595 if (rc) {
596 DRM_ERROR("Failed to load firmware!\n");
597 r128_do_cleanup_cce(dev);
598 }
599
600 return rc;
601 }
602
r128_do_cleanup_cce(struct drm_device * dev)603 int r128_do_cleanup_cce(struct drm_device *dev)
604 {
605
606 /* Make sure interrupts are disabled here because the uninstall ioctl
607 * may not have been called from userspace and after dev_private
608 * is freed, it's too late.
609 */
610 if (dev->irq_enabled)
611 drm_irq_uninstall(dev);
612
613 if (dev->dev_private) {
614 drm_r128_private_t *dev_priv = dev->dev_private;
615
616 #if IS_ENABLED(CONFIG_AGP)
617 if (!dev_priv->is_pci) {
618 if (dev_priv->cce_ring != NULL)
619 drm_legacy_ioremapfree(dev_priv->cce_ring, dev);
620 if (dev_priv->ring_rptr != NULL)
621 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
622 if (dev->agp_buffer_map != NULL) {
623 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
624 dev->agp_buffer_map = NULL;
625 }
626 } else
627 #endif
628 {
629 if (dev_priv->gart_info.bus_addr)
630 if (!drm_ati_pcigart_cleanup(dev,
631 &dev_priv->gart_info))
632 DRM_ERROR
633 ("failed to cleanup PCI GART!\n");
634 }
635
636 kfree(dev->dev_private);
637 dev->dev_private = NULL;
638 }
639
640 return 0;
641 }
642
r128_cce_init(struct drm_device * dev,void * data,struct drm_file * file_priv)643 int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
644 {
645 drm_r128_init_t *init = data;
646
647 DRM_DEBUG("\n");
648
649 LOCK_TEST_WITH_RETURN(dev, file_priv);
650
651 switch (init->func) {
652 case R128_INIT_CCE:
653 return r128_do_init_cce(dev, init);
654 case R128_CLEANUP_CCE:
655 return r128_do_cleanup_cce(dev);
656 }
657
658 return -EINVAL;
659 }
660
r128_cce_start(struct drm_device * dev,void * data,struct drm_file * file_priv)661 int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
662 {
663 drm_r128_private_t *dev_priv = dev->dev_private;
664 DRM_DEBUG("\n");
665
666 LOCK_TEST_WITH_RETURN(dev, file_priv);
667
668 DEV_INIT_TEST_WITH_RETURN(dev_priv);
669
670 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
671 DRM_DEBUG("while CCE running\n");
672 return 0;
673 }
674
675 r128_do_cce_start(dev_priv);
676
677 return 0;
678 }
679
680 /* Stop the CCE. The engine must have been idled before calling this
681 * routine.
682 */
r128_cce_stop(struct drm_device * dev,void * data,struct drm_file * file_priv)683 int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
684 {
685 drm_r128_private_t *dev_priv = dev->dev_private;
686 drm_r128_cce_stop_t *stop = data;
687 int ret;
688 DRM_DEBUG("\n");
689
690 LOCK_TEST_WITH_RETURN(dev, file_priv);
691
692 DEV_INIT_TEST_WITH_RETURN(dev_priv);
693
694 /* Flush any pending CCE commands. This ensures any outstanding
695 * commands are exectuted by the engine before we turn it off.
696 */
697 if (stop->flush)
698 r128_do_cce_flush(dev_priv);
699
700 /* If we fail to make the engine go idle, we return an error
701 * code so that the DRM ioctl wrapper can try again.
702 */
703 if (stop->idle) {
704 ret = r128_do_cce_idle(dev_priv);
705 if (ret)
706 return ret;
707 }
708
709 /* Finally, we can turn off the CCE. If the engine isn't idle,
710 * we will get some dropped triangles as they won't be fully
711 * rendered before the CCE is shut down.
712 */
713 r128_do_cce_stop(dev_priv);
714
715 /* Reset the engine */
716 r128_do_engine_reset(dev);
717
718 return 0;
719 }
720
721 /* Just reset the CCE ring. Called as part of an X Server engine reset.
722 */
r128_cce_reset(struct drm_device * dev,void * data,struct drm_file * file_priv)723 int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
724 {
725 drm_r128_private_t *dev_priv = dev->dev_private;
726 DRM_DEBUG("\n");
727
728 LOCK_TEST_WITH_RETURN(dev, file_priv);
729
730 DEV_INIT_TEST_WITH_RETURN(dev_priv);
731
732 r128_do_cce_reset(dev_priv);
733
734 /* The CCE is no longer running after an engine reset */
735 dev_priv->cce_running = 0;
736
737 return 0;
738 }
739
r128_cce_idle(struct drm_device * dev,void * data,struct drm_file * file_priv)740 int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
741 {
742 drm_r128_private_t *dev_priv = dev->dev_private;
743 DRM_DEBUG("\n");
744
745 LOCK_TEST_WITH_RETURN(dev, file_priv);
746
747 DEV_INIT_TEST_WITH_RETURN(dev_priv);
748
749 if (dev_priv->cce_running)
750 r128_do_cce_flush(dev_priv);
751
752 return r128_do_cce_idle(dev_priv);
753 }
754
r128_engine_reset(struct drm_device * dev,void * data,struct drm_file * file_priv)755 int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
756 {
757 DRM_DEBUG("\n");
758
759 LOCK_TEST_WITH_RETURN(dev, file_priv);
760
761 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
762
763 return r128_do_engine_reset(dev);
764 }
765
r128_fullscreen(struct drm_device * dev,void * data,struct drm_file * file_priv)766 int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
767 {
768 return -EINVAL;
769 }
770
771 /* ================================================================
772 * Freelist management
773 */
774 #define R128_BUFFER_USED 0xffffffff
775 #define R128_BUFFER_FREE 0
776
777 #if 0
778 static int r128_freelist_init(struct drm_device *dev)
779 {
780 struct drm_device_dma *dma = dev->dma;
781 drm_r128_private_t *dev_priv = dev->dev_private;
782 struct drm_buf *buf;
783 drm_r128_buf_priv_t *buf_priv;
784 drm_r128_freelist_t *entry;
785 int i;
786
787 dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
788 if (dev_priv->head == NULL)
789 return -ENOMEM;
790
791 dev_priv->head->age = R128_BUFFER_USED;
792
793 for (i = 0; i < dma->buf_count; i++) {
794 buf = dma->buflist[i];
795 buf_priv = buf->dev_private;
796
797 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
798 if (!entry)
799 return -ENOMEM;
800
801 entry->age = R128_BUFFER_FREE;
802 entry->buf = buf;
803 entry->prev = dev_priv->head;
804 entry->next = dev_priv->head->next;
805 if (!entry->next)
806 dev_priv->tail = entry;
807
808 buf_priv->discard = 0;
809 buf_priv->dispatched = 0;
810 buf_priv->list_entry = entry;
811
812 dev_priv->head->next = entry;
813
814 if (dev_priv->head->next)
815 dev_priv->head->next->prev = entry;
816 }
817
818 return 0;
819
820 }
821 #endif
822
r128_freelist_get(struct drm_device * dev)823 static struct drm_buf *r128_freelist_get(struct drm_device * dev)
824 {
825 struct drm_device_dma *dma = dev->dma;
826 drm_r128_private_t *dev_priv = dev->dev_private;
827 drm_r128_buf_priv_t *buf_priv;
828 struct drm_buf *buf;
829 int i, t;
830
831 /* FIXME: Optimize -- use freelist code */
832
833 for (i = 0; i < dma->buf_count; i++) {
834 buf = dma->buflist[i];
835 buf_priv = buf->dev_private;
836 if (!buf->file_priv)
837 return buf;
838 }
839
840 for (t = 0; t < dev_priv->usec_timeout; t++) {
841 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
842
843 for (i = 0; i < dma->buf_count; i++) {
844 buf = dma->buflist[i];
845 buf_priv = buf->dev_private;
846 if (buf->pending && buf_priv->age <= done_age) {
847 /* The buffer has been processed, so it
848 * can now be used.
849 */
850 buf->pending = 0;
851 return buf;
852 }
853 }
854 udelay(1);
855 }
856
857 DRM_DEBUG("returning NULL!\n");
858 return NULL;
859 }
860
r128_freelist_reset(struct drm_device * dev)861 void r128_freelist_reset(struct drm_device *dev)
862 {
863 struct drm_device_dma *dma = dev->dma;
864 int i;
865
866 for (i = 0; i < dma->buf_count; i++) {
867 struct drm_buf *buf = dma->buflist[i];
868 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
869 buf_priv->age = 0;
870 }
871 }
872
873 /* ================================================================
874 * CCE command submission
875 */
876
r128_wait_ring(drm_r128_private_t * dev_priv,int n)877 int r128_wait_ring(drm_r128_private_t *dev_priv, int n)
878 {
879 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
880 int i;
881
882 for (i = 0; i < dev_priv->usec_timeout; i++) {
883 r128_update_ring_snapshot(dev_priv);
884 if (ring->space >= n)
885 return 0;
886 udelay(1);
887 }
888
889 /* FIXME: This is being ignored... */
890 DRM_ERROR("failed!\n");
891 return -EBUSY;
892 }
893
r128_cce_get_buffers(struct drm_device * dev,struct drm_file * file_priv,struct drm_dma * d)894 static int r128_cce_get_buffers(struct drm_device *dev,
895 struct drm_file *file_priv,
896 struct drm_dma *d)
897 {
898 int i;
899 struct drm_buf *buf;
900
901 for (i = d->granted_count; i < d->request_count; i++) {
902 buf = r128_freelist_get(dev);
903 if (!buf)
904 return -EAGAIN;
905
906 buf->file_priv = file_priv;
907
908 if (copy_to_user(&d->request_indices[i], &buf->idx,
909 sizeof(buf->idx)))
910 return -EFAULT;
911 if (copy_to_user(&d->request_sizes[i], &buf->total,
912 sizeof(buf->total)))
913 return -EFAULT;
914
915 d->granted_count++;
916 }
917 return 0;
918 }
919
r128_cce_buffers(struct drm_device * dev,void * data,struct drm_file * file_priv)920 int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
921 {
922 struct drm_device_dma *dma = dev->dma;
923 int ret = 0;
924 struct drm_dma *d = data;
925
926 LOCK_TEST_WITH_RETURN(dev, file_priv);
927
928 /* Please don't send us buffers.
929 */
930 if (d->send_count != 0) {
931 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
932 task_pid_nr(current), d->send_count);
933 return -EINVAL;
934 }
935
936 /* We'll send you buffers.
937 */
938 if (d->request_count < 0 || d->request_count > dma->buf_count) {
939 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
940 task_pid_nr(current), d->request_count, dma->buf_count);
941 return -EINVAL;
942 }
943
944 d->granted_count = 0;
945
946 if (d->request_count)
947 ret = r128_cce_get_buffers(dev, file_priv, d);
948
949 return ret;
950 }
951