[Midnightbsd-cvs] src [9884] trunk/sys/boot/fdt: add fdt
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Thu May 24 07:32:26 EDT 2018
Revision: 9884
http://svnweb.midnightbsd.org/src/?rev=9884
Author: laffer1
Date: 2018-05-24 07:32:26 -0400 (Thu, 24 May 2018)
Log Message:
-----------
add fdt
Added Paths:
-----------
trunk/sys/boot/fdt/
trunk/sys/boot/fdt/Makefile
trunk/sys/boot/fdt/dts/
trunk/sys/boot/fdt/dts/bindings-gpio.txt
trunk/sys/boot/fdt/dts/bindings-mpp.txt
trunk/sys/boot/fdt/dts/db78100.dts
trunk/sys/boot/fdt/dts/db88f5182.dts
trunk/sys/boot/fdt/dts/db88f5281.dts
trunk/sys/boot/fdt/dts/db88f6281.dts
trunk/sys/boot/fdt/dts/dockstar.dts
trunk/sys/boot/fdt/dts/mpc8555cds.dts
trunk/sys/boot/fdt/dts/mpc8572ds.dts
trunk/sys/boot/fdt/dts/sheevaplug.dts
trunk/sys/boot/fdt/dts/ts7800.dts
trunk/sys/boot/fdt/fdt_loader_cmd.c
Added: trunk/sys/boot/fdt/Makefile
===================================================================
--- trunk/sys/boot/fdt/Makefile (rev 0)
+++ trunk/sys/boot/fdt/Makefile 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,30 @@
+# $MidnightBSD$
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../../contrib/libfdt/
+
+LIB= fdt
+INTERNALLIB=
+
+# Vendor sources of libfdt.
+SRCS+= fdt.c fdt_ro.c fdt_wip.c fdt_sw.c fdt_rw.c fdt_strerror.c
+
+# Loader's fdt commands extension sources.
+SRCS+= fdt_loader_cmd.c
+
+CFLAGS+= -I${.CURDIR}/../../contrib/libfdt/ -I${.CURDIR}/../common/ \
+ -I${.CURDIR}/../uboot/lib
+
+CFLAGS+= -ffreestanding
+
+.if ${MACHINE_CPUARCH} == "powerpc" || ${MACHINE_CPUARCH} == "arm"
+CFLAGS+= -msoft-float
+.endif
+
+.if ${MACHINE_ARCH} == "powerpc64"
+CFLAGS+= -m32
+.endif
+
+CFLAGS+= -Wformat -Wall
+
+.include <bsd.lib.mk>
Property changes on: trunk/sys/boot/fdt/Makefile
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+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/boot/fdt/dts/bindings-gpio.txt
===================================================================
--- trunk/sys/boot/fdt/dts/bindings-gpio.txt (rev 0)
+++ trunk/sys/boot/fdt/dts/bindings-gpio.txt 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,101 @@
+$MidnightBSD$
+
+GPIO configuration.
+===================
+
+1. Properties for GPIO Controllers
+
+1.1 #gpio-cells
+
+Property: #gpio-cells
+
+Value type: <u32>
+
+Description: The #gpio-cells property defines the number of cells required
+ to encode a gpio specifier.
+
+
+1.2 gpio-controller
+
+Property: gpio-controller
+
+Value type: <empty>
+
+Description: The presence of a gpio-controller property defines a node as a
+ GPIO controller node.
+
+
+1.3 pin-count
+
+Property: pin-count
+
+Value type: <u32>
+
+Description: The pin-count property defines the number of GPIO pins.
+
+
+1.4 Example
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <6 7 8 9>;
+ interrupt-parent = <&PIC>;
+ pin-count = <50>
+ };
+
+2. Properties for GPIO consumer nodes.
+
+2.1 gpios
+
+Property: gpios
+
+Value type: <prop-encoded-array> encoded as arbitrary number of GPIO
+ specifiers.
+
+Description: The gpios property of a device node defines the GPIO or GPIOs
+ that are used by the device. The value of the gpios property
+ consists of an arbitrary number of GPIO specifiers.
+
+ The first cell of the GPIO specifier is phandle of the node's
+ parent GPIO controller and remaining cells are defined by the
+ binding describing the GPIO parent, typically include
+ information like pin number, direction and various flags.
+
+Example:
+ gpios = <&GPIO 0 1 0 /* GPIO[0]: IN, NONE */
+ &GPIO 1 2 0>; /* GPIO[1]: OUT, NONE */
+
+
+3. "mrvl,gpio" controller GPIO specifier
+
+ <phandle pin dir flags>
+
+
+pin: 0-MAX GPIO pin number.
+
+dir:
+ 1 IN Input direction.
+ 2 OUT Output direction.
+
+flags:
+ 0x0000---- IN_NONE
+ 0x0001---- IN_POL_LOW Polarity low (inverted input value.
+ 0x0002---- IN_IRQ_EDGE Interrupt, edge triggered.
+ 0x0004---- IN_IRQ_LEVEL Interrupt, level triggered.
+
+ 0x----0000 OUT_NONE
+ 0x----0001 OUT_BLINK Blink on the pin.
+ 0x----0002 OUT_OPEN_DRAIN Open drain output line.
+ 0x----0004 OUT_OPEN_SRC Open source output line.
+
+
+Example:
+ gpios = <&GPIO 0 1 0x00000000 /* GPIO[0]: IN */
+ &GPIO 1 2 0x00000000 /* GPIO[1]: OUT */
+ &GPIO 2 1 0x00020000 /* GPIO[2]: IN, IRQ (edge) */
+ &GPIO 3 1 0x00040000 /* GPIO[3]: IN, IRQ (level) */
+ ...
+ &GPIO 10 2 0x00000001>; /* GPIO[10]: OUT, blink */
Property changes on: trunk/sys/boot/fdt/dts/bindings-gpio.txt
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/boot/fdt/dts/bindings-mpp.txt
===================================================================
--- trunk/sys/boot/fdt/dts/bindings-mpp.txt (rev 0)
+++ trunk/sys/boot/fdt/dts/bindings-mpp.txt 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,50 @@
+$FreeBSD$
+
+* Multi purpose pin (MPP) configuration.
+
+Required properties:
+
+- pin-map : array of pin configurations. Each pin is defined by 2 cells,
+ respectively: <pin> <function>. Pins not specified in the pin-map property
+ are assumed to have default value of <function> = 0, which means GPIO.
+
+ - pin : pin number.
+
+ - function : function ID of the pin according to the assignment tables in
+ User Manual. Each pin can have many possible functions depending on the
+ MPP unit incarnation.
+
+- pin-count: number of the physical MPP connections on the SOC (depending on
+ the model it can be 24-50, or possibly else in future devices).
+
+Example:
+
+ mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count= <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 7 2 /* MPP[7]: SPI_SCn */
+ 8 1 /* MPP[8]: TW_SDA */
+ 9 1 /* MPP[9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 5 /* MPP[20]: SATA1_AC */
+ 21 5 >; /* MPP[21]: SATA0_AC */
+ };
Property changes on: trunk/sys/boot/fdt/dts/bindings-mpp.txt
___________________________________________________________________
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+bindings-gpio.txt
\ No newline at end of property
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+native
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+text/plain
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Added: trunk/sys/boot/fdt/dts/db78100.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db78100.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/db78100.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-78100 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-78100";
+ compatible = "DB-78100-BP", "DB-78100-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR571";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+ win-count = <14>;
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000
+ 0x3 0x1b 0xfc100000 0x00000400>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x3 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ soc78100 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <8>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 2 /* MPP[0]: GE1_TXCLK */
+ 1 2 /* MPP[1]: GE1_TXCTL */
+ 2 2 /* MPP[2]: GE1_RXCTL */
+ 3 2 /* MPP[3]: GE1_RXCLK */
+ 4 2 /* MPP[4]: GE1_TXD[0] */
+ 5 2 /* MPP[5]: GE1_TXD[1] */
+ 6 2 /* MPP[6]: GE1_TXD[2] */
+ 7 2 /* MPP[7]: GE1_TXD[3] */
+ 8 2 /* MPP[8]: GE1_RXD[0] */
+ 9 2 /* MPP[9]: GE1_RXD[1] */
+ 10 2 /* MPP[10]: GE1_RXD[2] */
+ 11 2 /* MPP[11]: GE1_RXD[3] */
+ 13 3 /* MPP[13]: SYSRST_OUTn */
+ 14 3 /* MPP[14]: SATA1_ACTn */
+ 15 3 /* MPP[15]: SATA0_ACTn */
+ 16 4 /* MPP[16]: UA2_TXD */
+ 17 4 /* MPP[17]: UA2_RXD */
+ 18 3 /* MPP[18]: <UNKNOWN> */
+ 19 3 /* MPP[19]: <UNKNOWN> */
+ 20 3 /* MPP[20]: <UNKNOWN> */
+ 21 3 /* MPP[21]: <UNKNOWN> */
+ 22 4 /* MPP[22]: UA3_TXD */
+ 23 4 >; /* MPP[21]: UA3_RXD */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <56 57 58 59>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <2>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11100 0x20>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <41 42 43 40 70>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ phy1: ethernet-phy at 1 {
+ reg = <0x9>;
+ };
+ };
+ };
+
+ enet1: ethernet at 76000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x76000 0x2000>;
+ ranges = <0x0 0x76000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <45 46 47 44 70>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy1>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <12>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <13>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <72 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 51000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x51000 0x1000>;
+ interrupts = <72 17>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 52000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x52000 0x1000>;
+ interrupts = <72 18>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <22 23>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 90000 {
+ compatible = "mrvl,cesa";
+ reg = <0x90000 0x10000>;
+ interrupts = <19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at a0000 {
+ compatible = "mrvl,sata";
+ reg = <0xa0000 0x6000>;
+ interrupts = <26>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ pci0: pcie at f1040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0xf2000000 0xf2000000 0x0 0x04000000
+ 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&PIC>;
+ interrupts = <68>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0x0800 0x0 0x0 0x1 &PIC 0x20
+ 0x0800 0x0 0x0 0x2 &PIC 0x21
+ 0x0800 0x0 0x0 0x3 &PIC 0x22
+ 0x0800 0x0 0x0 0x4 &PIC 0x23
+ >;
+ };
+
+ sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/db78100.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
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+native
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Added: trunk/sys/boot/fdt/dts/db88f5182.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f5182.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/db88f5182.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F5182 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F5182";
+ compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ soc88f5182 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 0 3 /* MPP[0]: GPIO[0] */
+ 2 2 /* MPP[2]: PCI_REQn[3] */
+ 3 2 /* MPP[3]: PCI_GNTn[3] */
+ 4 2 /* MPP[4]: PCI_REQn[4] */
+ 5 2 /* MPP[5]: PCI_GNTn[4] */
+ 6 5 /* MPP[6]: SATA0_ACT */
+ 7 5 /* MPP[7]: SATA1_ACT */
+ 12 5 /* MPP[12]: SATA0_PRESENT */
+ 13 5 /* MPP[13]: SATA1_PRESENT */
+ 14 4 /* MPP[14]: NAND Flash REn[2] */
+ 15 4 /* MPP[15]: NAND Flash WEn[2] */
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 18 0 /* MPP[18]: UA1_CTS */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <6 7 8 9>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <17 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ idma at 60000 {
+ compatible = "mrvl,idma";
+ reg = <0x60000 0x1000>;
+ interrupts = <24 25 26 27 23>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <29>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/db88f5182.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/db88f5281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f5281.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/db88f5281.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F5281 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F5281";
+ compatible = "DB-88F5281-BP", "DB-88F5281-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ soc88f5281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 0 3 /* MPP[0]: GPIO[0] */
+ 2 2 /* MPP[2]: PCI_REQn[3] */
+ 3 2 /* MPP[3]: PCI_GNTn[3] */
+ 4 2 /* MPP[4]: PCI_REQn[4] */
+ 5 2 /* MPP[5]: PCI_GNTn[4] */
+ 6 3 /* MPP[6]: <UNKNOWN> */
+ 7 3 /* MPP[7]: <UNKNOWN> */
+ 8 3 /* MPP[8]: <UNKNOWN> */
+ 9 3 /* MPP[9]: <UNKNOWN> */
+ 14 4 /* MPP[14]: NAND Flash REn[2] */
+ 15 4 /* MPP[15]: NAND Flash WEn[2] */
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 18 0 /* MPP[18]: UA1_CTS */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <6 7 8 9>;
+ interrupt-parent = <&PIC>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <17 16>;
+ interrupt-parent = <&PIC>;
+ };
+
+ idma at 60000 {
+ compatible = "mrvl,idma";
+ reg = <0x60000 0x1000>;
+ interrupts = <24 25 26 27 23>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/db88f5281.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/db88f6281.dts
===================================================================
--- trunk/sys/boot/fdt/dts/db88f6281.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/db88f6281.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell DB-88F6281 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,DB-88F6281";
+ compatible = "DB-88F6281-BP", "DB-88F6281-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ pci0 = &pci0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000
+ 0x3 0x1b 0xfc100000 0x00000400>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x3 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 7 2 /* MPP[7]: SPI_SCn */
+ 8 1 /* MPP[8]: TW_SDA */
+ 9 1 /* MPP[9]: TW_SCK */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 20 5 /* MPP[20]: SATA1_AC */
+ 21 5 >; /* MPP[21]: SATA0_AC */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x8>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+
+ sata at 80000 {
+ compatible = "mrvl,sata";
+ reg = <0x80000 0x6000>;
+ interrupts = <21>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ pci0: pcie at f1040000 {
+ compatible = "mrvl,pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xf1040000 0x2000>;
+ bus-range = <0 255>;
+ ranges = <0x02000000 0x0 0xf1300000 0xf1300000 0x0 0x04000000
+ 0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&PIC>;
+ interrupts = <44>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x1 */
+ 0x0800 0x0 0x0 0x1 &PIC 0x9
+ 0x0800 0x0 0x0 0x2 &PIC 0x9
+ 0x0800 0x0 0x0 0x3 &PIC 0x9
+ 0x0800 0x0 0x0 0x4 &PIC 0x9
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0xf1300000
+ 0x02000000 0x0 0xf1300000
+ 0x0 0x04000000
+
+ 0x01000000 0x0 0x0
+ 0x01000000 0x0 0x0
+ 0x0 0x00100000>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/db88f6281.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/dockstar.dts
===================================================================
--- trunk/sys/boot/fdt/dts/dockstar.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/dockstar.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Seagate DockStar (Marvell SheevaPlug based) Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "seagate,DockStar";
+ compatible = "DockStar";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x8000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000
+ 0x3 0x1b 0xfc100000 0x00000400>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x3 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 8 2 /* MPP[8]: UA0_RTS */
+ 9 2 /* MPP[9]: UA0_CTS */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 29 1 >; /* MPP[29]: TSMP[9] */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/dockstar.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/mpc8555cds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mpc8555cds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mpc8555cds.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,443 @@
+/*
+ * MPC8555 CDS Device Tree Source
+ *
+ * Copyright 2006, 2008 Freescale Semiconductor Inc. All rights reserved
+ *
+ * Neither the name of Freescale Semiconductor, Inc nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Freescale hereby publishes it under the following licenses:
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * GNU General Public License, version 2
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ * You may select the license of your choice.
+ *------------------------------------------------------------------
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "MPC8555CDS";
+ compatible = "MPC8555CDS", "MPC85xxCDS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8555 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>; // 33 MHz, from uboot
+ bus-frequency = <0>; // 166 MHz
+ clock-frequency = <0>; // 825 MHz, from uboot
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>; // 256M at 0x0
+ };
+
+ localbus at e0005000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,lbc", "fsl,elbc";
+ reg = <0xe0005000 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0xff800000 0x00800000
+ 0x1 0x0 0xff000000 0x00800000
+ 0x2 0x0 0xf8000000 0x00008000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00800000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nor at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x1 0x0 0x00800000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ rtc at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "dallas,ds1553";
+ reg = <0x2 0x0 0x00008000>;
+ bank-width = <1>;
+ device-width = <1>;
+ };
+ };
+
+ soc8555 at e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x0 0xe0000000 0x100000>;
+ bus-frequency = <0>;
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <8>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,mpc8555-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,8555-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,8555-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x40000>; // L2, 256K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8555-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x0>;
+ device_type = "ethernet-phy";
+ };
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <5 1>;
+ reg = <0x1>;
+ device_type = "ethernet-phy";
+ };
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x7e>;
+ fsl,descriptor-types-mask = <0x01010ebf>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ cpm at 80000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
+ reg = <0x80000 0x20000>;
+ interrupts = <46 2>;
+ interrupt-parent = <&mpic>;
+ };
+ };
+
+ pci0: pci at e0008000 {
+ interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x10 */
+ 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x11 */
+ 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
+ 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
+ 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
+ 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
+ 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ bus-range = <0 0>;
+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xfee00000 0x0 0x00010000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe0008000 0x1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+
+ i8259 at 19000 {
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <0x19000 0x0 0x0 0x0 0x1>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <1>;
+ interrupt-parent = <&pci0>;
+ };
+ };
+
+ pci1: pci at e0009000 {
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
+ 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ bus-range = <0 0>;
+ ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x0 0xfee10000 0x0 0x00010000>;
+ clock-frequency = <66666666>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0xe0009000 0x1000>;
+ compatible = "fsl,mpc8540-pci";
+ device_type = "pci";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mpc8555cds.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/mpc8572ds.dts
===================================================================
--- trunk/sys/boot/fdt/dts/mpc8572ds.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/mpc8572ds.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,895 @@
+/*
+ * MPC8572 DS Device Tree Source
+ *
+ * Copyright 2007-2009 Freescale Semiconductor Inc. All rights reserved
+ *
+ * Neither the name of Freescale Semiconductor, Inc nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * Freescale hereby publishes it under the following licenses:
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+ * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * GNU General Public License, version 2
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ *
+ * You may select the license of your choice.
+ *------------------------------------------------------------------
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,MPC8572DS";
+ compatible = "fsl,MPC8572DS";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ pci2 = &pci2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,8572 at 0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,8572 at 1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus at ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ ranges = <0x0 0x0 0x0 0xe8000000 0x08000000>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition at 0 {
+ reg = <0x0 0x03000000>;
+ label = "ramdisk-nor";
+ read-only;
+ };
+
+ partition at 3000000 {
+ reg = <0x03000000 0x00e00000>;
+ label = "diagnostic-nor";
+ read-only;
+ };
+
+ partition at 3e00000 {
+ reg = <0x03e00000 0x00200000>;
+ label = "dink-nor";
+ read-only;
+ };
+
+ partition at 4000000 {
+ reg = <0x04000000 0x00400000>;
+ label = "kernel-nor";
+ read-only;
+ };
+
+ partition at 4400000 {
+ reg = <0x04400000 0x03b00000>;
+ label = "jffs2-nor";
+ };
+
+ partition at 7f00000 {
+ reg = <0x07f00000 0x00080000>;
+ label = "dtb-nor";
+ read-only;
+ };
+
+ partition at 7f80000 {
+ reg = <0x07f80000 0x00080000>;
+ label = "u-boot-nor";
+ read-only;
+ };
+ };
+
+ nand at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x2 0x0 0x40000>;
+
+ partition at 0 {
+ reg = <0x0 0x02000000>;
+ label = "u-boot-nand";
+ read-only;
+ };
+
+ partition at 2000000 {
+ reg = <0x02000000 0x10000000>;
+ label = "jffs2-nand";
+ };
+
+ partition at 12000000 {
+ reg = <0x12000000 0x08000000>;
+ label = "ramdisk-nand";
+ read-only;
+ };
+
+ partition at 1a000000 {
+ reg = <0x1a000000 0x04000000>;
+ label = "kernel-nand";
+ };
+
+ partition at 1e000000 {
+ reg = <0x1e000000 0x01000000>;
+ label = "dtb-nand";
+ read-only;
+ };
+
+ partition at 1f000000 {
+ reg = <0x1f000000 0x21000000>;
+ label = "reserved-nand";
+ };
+ };
+
+ nand at 4,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x4 0x0 0x40000>;
+ };
+
+ nand at 5,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x5 0x0 0x40000>;
+ };
+
+ nand at 6,0 {
+ compatible = "fsl,mpc8572-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x6 0x0 0x40000>;
+ };
+ };
+
+ soc8572 at ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x0 0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law at 0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm at 1000 {
+ compatible = "fsl,mpc8572-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller at 2000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ memory-controller at 6000 {
+ compatible = "fsl,mpc8572-memory-controller";
+ reg = <0x6000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ L2: l2-cache-controller at 20000 {
+ compatible = "fsl,mpc8572-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x100000>; // L2, 1M
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ i2c at 3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ i2c at 3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ dma at c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ dma at 21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel at 0 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel at 80 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel at 100 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel at 180 {
+ compatible = "fsl,mpc8572-dma-channel",
+ "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ ptp_timer: ptimer at 24e00 {
+ compatible = "fsl,gianfar-ptp-timer";
+ reg = <0x24e00 0xb0>;
+ };
+
+ enet0: ethernet at 24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy at 0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy at 1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x1>;
+ };
+ phy2: ethernet-phy at 2 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x2>;
+ };
+ phy3: ethernet-phy at 3 {
+ interrupt-parent = <&mpic>;
+ interrupts = <10 1>;
+ reg = <0x3>;
+ };
+
+ tbi0: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet1: ethernet at 25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi1: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet at 26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi2>;
+ phy-handle = <&phy2>;
+ ptimer-handle = < &ptp_timer >;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi2: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet3: ethernet at 27000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <3>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x27000 0x1000>;
+ ranges = <0x0 0x27000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <37 2 38 2 39 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi3>;
+ phy-handle = <&phy3>;
+ phy-connection-type = "rgmii-id";
+
+ mdio at 520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi3: tbi-phy at 11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ serial0: serial at 4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial at 4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities at e0000 { //global utilities block
+ compatible = "fsl,mpc8572-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+
+ power at e0070{
+ compatible = "fsl,mpc8548-pmc";
+ reg = <0xe0070 0x14>;
+ };
+
+ timer at 41100 {
+ compatible = "fsl,mpic-global-timer";
+ reg = <0x41100 0x204>;
+ interrupts = <0xf7 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ msi at 41600 {
+ compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ crypto at 30000 {
+ compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
+ "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0x9fe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ /* PME (pattern-matcher) */
+ pme at 10000 {
+ device_type = "pme";
+ compatible = "pme8572";
+ reg = <0x10000 0x5000>;
+ interrupts = <0x39 0x2 0x40 0x2 0x41 0x2 0x42 0x2 0x43 0x2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ mpic: pic at 40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+ };
+
+ pci0: pcie at ffe08000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe08000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee20000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <24 2>;
+ interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x11 func 0 - PCI slot 1 */
+ 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 1 - PCI slot 1 */
+ 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 2 - PCI slot 1 */
+ 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 3 - PCI slot 1 */
+ 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 4 - PCI slot 1 */
+ 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 5 - PCI slot 1 */
+ 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 6 - PCI slot 1 */
+ 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x11 func 7 - PCI slot 1 */
+ 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
+ 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
+ 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
+ 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
+
+ /* IDSEL 0x12 func 0 - PCI slot 2 */
+ 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 1 - PCI slot 2 */
+ 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 2 - PCI slot 2 */
+ 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 3 - PCI slot 2 */
+ 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 4 - PCI slot 2 */
+ 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 5 - PCI slot 2 */
+ 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 6 - PCI slot 2 */
+ 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ /* IDSEL 0x12 func 7 - PCI slot 2 */
+ 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
+ 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
+ 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
+ 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
+
+ // IDSEL 0x1c USB
+ 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
+ 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
+ 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
+ 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
+
+ // IDSEL 0x1d Audio
+ 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
+
+ // IDSEL 0x1e Legacy
+ 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
+ 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
+
+ // IDSEL 0x1f IDE/SATA
+ 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
+ 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
+
+ >;
+
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ uli1575 at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ isa at 1e {
+ device_type = "isa";
+ #interrupt-cells = <2>;
+ #size-cells = <1>;
+ #address-cells = <2>;
+ reg = <0xf000 0x0 0x0 0x0 0x0>;
+ ranges = <0x1 0x0 0x1000000 0x0 0x0
+ 0x1000>;
+ interrupt-parent = <&i8259>;
+
+ i8259: interrupt-controller at 20 {
+ reg = <0x1 0x20 0x2
+ 0x1 0xa0 0x2
+ 0x1 0x4d0 0x2>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ compatible = "chrp,iic";
+ interrupts = <9 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ i8042 at 60 {
+ #size-cells = <0>;
+ #address-cells = <1>;
+ reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
+ interrupts = <1 3 12 3>;
+ interrupt-parent =
+ <&i8259>;
+
+ keyboard at 0 {
+ reg = <0x0>;
+ compatible = "pnpPNP,303";
+ };
+
+ mouse at 1 {
+ reg = <0x1>;
+ compatible = "pnpPNP,f03";
+ };
+ };
+
+ rtc at 70 {
+ compatible = "pnpPNP,b00";
+ reg = <0x1 0x70 0x2>;
+ };
+
+ gpio at 400 {
+ reg = <0x1 0x400 0x80>;
+ };
+ };
+ };
+ };
+
+ };
+
+ pci1: pcie at ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee10000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x4 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x5 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x6 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x7 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x90000000
+ 0x2000000 0x0 0x90000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci2: pcie at ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
+ 0x1000000 0x0 0x00000000 0 0xfee00000 0x0 0x00010000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+ interrupt-map = <
+ /* IDSEL 0x0 */
+ 0000 0x0 0x0 0x1 &mpic 0x0 0x1
+ 0000 0x0 0x0 0x2 &mpic 0x1 0x1
+ 0000 0x0 0x0 0x3 &mpic 0x2 0x1
+ 0000 0x0 0x0 0x4 &mpic 0x3 0x1
+ >;
+ pcie at 0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x10000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/mpc8572ds.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/sheevaplug.dts
===================================================================
--- trunk/sys/boot/fdt/dts/sheevaplug.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/sheevaplug.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Marvell SheevaPlug Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,SheevaPlug";
+ compatible = "SheevaPlug";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &enet0;
+ mpp = &MPP;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ soc = &SOC;
+ sram = &SRAM;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR131";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x4000>; // L1, 16K
+ i-cache-size = <0x4000>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x20000000>; // 512M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000
+ 0x3 0x1b 0xfc100000 0x00000400>;
+
+ nor at 0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ led at 1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "led";
+ reg = <0x1 0x0 0x00100000>;
+ };
+
+ nor at 2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x2 0x0 0x02000000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+
+ nand at 3,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x3 0x0 0x00100000>;
+ bank-width = <2>;
+ device-width = <1>;
+ };
+ };
+
+ SOC: soc88f6281 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <1>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x34>;
+ pin-count = <50>;
+ pin-map = <
+ 0 1 /* MPP[0]: NF_IO[2] */
+ 1 1 /* MPP[1]: NF_IO[3] */
+ 2 1 /* MPP[2]: NF_IO[4] */
+ 3 1 /* MPP[3]: NF_IO[5] */
+ 4 1 /* MPP[4]: NF_IO[6] */
+ 5 1 /* MPP[5]: NF_IO[7] */
+ 6 1 /* MPP[6]: SYSRST_OUTn */
+ 8 2 /* MPP[8]: UA0_RTS */
+ 9 2 /* MPP[9]: UA0_CTS */
+ 10 3 /* MPP[10]: UA0_TXD */
+ 11 3 /* MPP[11]: UA0_RXD */
+ 12 1 /* MPP[12]: SD_CLK */
+ 13 1 /* MPP[13]: SD_CMD */
+ 14 1 /* MPP[14]: SD_D[0] */
+ 15 1 /* MPP[15]: SD_D[1] */
+ 16 1 /* MPP[16]: SD_D[2] */
+ 17 1 /* MPP[17]: SD_D[3] */
+ 18 1 /* MPP[18]: NF_IO[0] */
+ 19 1 /* MPP[19]: NF_IO[1] */
+ 29 1 >; /* MPP[29]: TSMP[9] */
+ };
+
+ GPIO: gpio at 10100 {
+ #gpio-cells = <3>;
+ compatible = "mrvl,gpio";
+ reg = <0x10100 0x20>;
+ gpio-controller;
+ interrupts = <35 36 37 38 39 40 41>;
+ interrupt-parent = <&PIC>;
+ };
+
+ rtc at 10300 {
+ compatible = "mrvl,rtc";
+ reg = <0x10300 0x08>;
+ };
+
+ twsi at 11000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,twsi";
+ reg = <0x11000 0x20>;
+ interrupts = <43>;
+ interrupt-parent = <&PIC>;
+ };
+
+ enet0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V2";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <12 13 14 11 46>;
+ interrupt-parent = <&PIC>;
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <33>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <34>;
+ interrupt-parent = <&PIC>;
+ };
+
+ crypto at 30000 {
+ compatible = "mrvl,cesa";
+ reg = <0x30000 0x10000>;
+ interrupts = <22>;
+ interrupt-parent = <&PIC>;
+
+ sram-handle = <&SRAM>;
+ };
+
+ usb at 50000 {
+ compatible = "mrvl,usb-ehci", "usb-ehci";
+ reg = <0x50000 0x1000>;
+ interrupts = <48 19>;
+ interrupt-parent = <&PIC>;
+ };
+
+ xor at 60000 {
+ compatible = "mrvl,xor";
+ reg = <0x60000 0x1000>;
+ interrupts = <5 6 7 8>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ SRAM: sram at fd000000 {
+ compatible = "mrvl,cesa-sram";
+ reg = <0xfd000000 0x00100000>;
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/sheevaplug.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/dts/ts7800.dts
===================================================================
--- trunk/sys/boot/fdt/dts/ts7800.dts (rev 0)
+++ trunk/sys/boot/fdt/dts/ts7800.dts 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Technologic Systems TS-7800 Device Tree Source.
+ *
+ * $FreeBSD$
+ */
+
+/dts-v1/;
+
+/ {
+ model = "mrvl,TS-7800";
+ compatible = "DB-88F5182-BP", "DB-88F5182-BP-A";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &mge0;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ mpp = &MPP;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu at 0 {
+ device_type = "cpu";
+ compatible = "ARM,88FR531";
+ reg = <0x0>;
+ d-cache-line-size = <32>; // 32 bytes
+ i-cache-line-size = <32>; // 32 bytes
+ d-cache-size = <0x8000>; // L1, 32K
+ i-cache-size = <0x8000>; // L1, 32K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>; // 128M at 0x0
+ };
+
+ localbus at f1000000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "mrvl,lbc";
+
+ /* This reflects CPU decode windows setup. */
+ ranges = <0x0 0x0f 0xf9300000 0x00100000
+ 0x1 0x1e 0xfa000000 0x00100000
+ 0x2 0x1d 0xfa100000 0x02000000>;
+ };
+
+ soc88f5182 at f1000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0xf1000000 0x00100000>;
+ bus-frequency = <0>;
+
+ PIC: pic at 20200 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x20200 0x3c>;
+ compatible = "mrvl,pic";
+ };
+
+ timer at 20300 {
+ compatible = "mrvl,timer";
+ reg = <0x20300 0x30>;
+ interrupts = <0>;
+ interrupt-parent = <&PIC>;
+ mrvl,has-wdt;
+ };
+
+ MPP: mpp at 10000 {
+ #pin-cells = <2>;
+ compatible = "mrvl,mpp";
+ reg = <0x10000 0x54>;
+ pin-count = <20>;
+ pin-map = <
+ 16 0 /* MPP[16]: UA1_RXD */
+ 17 0 /* MPP[17]: UA1_TXD */
+ 19 0 >; /* MPP[19]: UA1_RTS */
+ };
+
+ mge0: ethernet at 72000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "V1";
+ compatible = "mrvl,ge";
+ reg = <0x72000 0x2000>;
+ ranges = <0x0 0x72000 0x2000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <18 19 20 21 22>;
+ interrupt-parent = <&PIC>;
+
+ phy-handle = <&phy0>;
+
+ mdio at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mrvl,mdio";
+
+ phy0: ethernet-phy at 0 {
+ reg = <0x0>;
+ };
+ };
+ };
+
+ serial0: serial at 12000 {
+ compatible = "ns16550";
+ reg = <0x12000 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <3>;
+ interrupt-parent = <&PIC>;
+ };
+
+ serial1: serial at 12100 {
+ compatible = "ns16550";
+ reg = <0x12100 0x20>;
+ reg-shift = <2>;
+ clock-frequency = <0>;
+ interrupts = <4>;
+ interrupt-parent = <&PIC>;
+ };
+ };
+
+ chosen {
+ stdin = "serial0";
+ stdout = "serial0";
+ };
+};
Property changes on: trunk/sys/boot/fdt/dts/ts7800.dts
___________________________________________________________________
Added: mnbsd:nokeywords
## -0,0 +1 ##
+bindings-gpio.txt
\ No newline at end of property
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/fdt/fdt_loader_cmd.c
===================================================================
--- trunk/sys/boot/fdt/fdt_loader_cmd.c (rev 0)
+++ trunk/sys/boot/fdt/fdt_loader_cmd.c 2018-05-24 11:32:26 UTC (rev 9884)
@@ -0,0 +1,1427 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2009-2010 The FreeBSD Foundation
+ * All rights reserved.
+ *
+ * This software was developed by Semihalf under sponsorship from
+ * the FreeBSD Foundation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <stand.h>
+#include <fdt.h>
+#include <libfdt.h>
+#include <sys/param.h>
+#include <sys/linker.h>
+#include <machine/elf.h>
+
+#include "bootstrap.h"
+#include "glue.h"
+
+#define DEBUG
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
+ printf(fmt,##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+#define FDT_CWD_LEN 256
+#define FDT_MAX_DEPTH 6
+
+#define FDT_PROP_SEP " = "
+
+#define STR(number) #number
+#define STRINGIFY(number) STR(number)
+
+#define COPYOUT(s,d,l) archsw.arch_copyout((vm_offset_t)(s), d, l)
+
+#define FDT_STATIC_DTB_SYMBOL "fdt_static_dtb"
+
+static struct fdt_header *fdtp = NULL;
+
+static int fdt_cmd_nyi(int argc, char *argv[]);
+
+static int fdt_cmd_mkprop(int argc, char *argv[]);
+static int fdt_cmd_cd(int argc, char *argv[]);
+static int fdt_cmd_hdr(int argc, char *argv[]);
+static int fdt_cmd_ls(int argc, char *argv[]);
+static int fdt_cmd_prop(int argc, char *argv[]);
+static int fdt_cmd_pwd(int argc, char *argv[]);
+static int fdt_cmd_rm(int argc, char *argv[]);
+static int fdt_cmd_mknode(int argc, char *argv[]);
+
+typedef int cmdf_t(int, char *[]);
+
+struct cmdtab {
+ char *name;
+ cmdf_t *handler;
+};
+
+static const struct cmdtab commands[] = {
+ { "alias", &fdt_cmd_nyi },
+ { "cd", &fdt_cmd_cd },
+ { "header", &fdt_cmd_hdr },
+ { "ls", &fdt_cmd_ls },
+ { "mknode", &fdt_cmd_mknode },
+ { "mkprop", &fdt_cmd_mkprop },
+ { "mres", &fdt_cmd_nyi },
+ { "prop", &fdt_cmd_prop },
+ { "pwd", &fdt_cmd_pwd },
+ { "rm", &fdt_cmd_rm },
+ { NULL, NULL }
+};
+
+static char cwd[FDT_CWD_LEN] = "/";
+
+static vm_offset_t
+fdt_find_static_dtb(void)
+{
+ Elf_Sym sym;
+ vm_offset_t dyntab, esym;
+ uint64_t offs;
+ struct preloaded_file *kfp;
+ struct file_metadata *md;
+ Elf_Sym *symtab;
+ Elf_Dyn *dyn;
+ char *strtab, *strp;
+ int i, sym_count;
+
+ symtab = NULL;
+ dyntab = esym = 0;
+ strtab = strp = NULL;
+
+ offs = __elfN(relocation_offset);
+
+ kfp = file_findfile(NULL, NULL);
+ if (kfp == NULL)
+ return (0);
+
+ md = file_findmetadata(kfp, MODINFOMD_ESYM);
+ if (md == NULL)
+ return (0);
+ COPYOUT(md->md_data, &esym, sizeof(esym));
+
+ md = file_findmetadata(kfp, MODINFOMD_DYNAMIC);
+ if (md == NULL)
+ return (0);
+ COPYOUT(md->md_data, &dyntab, sizeof(dyntab));
+
+ dyntab += offs;
+
+ /* Locate STRTAB and DYNTAB */
+ for (dyn = (Elf_Dyn *)dyntab; dyn->d_tag != DT_NULL; dyn++) {
+ if (dyn->d_tag == DT_STRTAB) {
+ strtab = (char *)(uintptr_t)(dyn->d_un.d_ptr + offs);
+ continue;
+ } else if (dyn->d_tag == DT_SYMTAB) {
+ symtab = (Elf_Sym *)(uintptr_t)
+ (dyn->d_un.d_ptr + offs);
+ continue;
+ }
+ }
+
+ if (symtab == NULL || strtab == NULL) {
+ /*
+ * No symtab? No strtab? That should not happen here,
+ * and should have been verified during __elfN(loadimage).
+ * This must be some kind of a bug.
+ */
+ return (0);
+ }
+
+ sym_count = (int)((Elf_Sym *)esym - symtab) / sizeof(Elf_Sym);
+
+ /*
+ * The most efficent way to find a symbol would be to calculate a
+ * hash, find proper bucket and chain, and thus find a symbol.
+ * However, that would involve code duplication (e.g. for hash
+ * function). So we're using simpler and a bit slower way: we're
+ * iterating through symbols, searching for the one which name is
+ * 'equal' to 'fdt_static_dtb'. To speed up the process a little bit,
+ * we are eliminating symbols type of which is not STT_NOTYPE, or(and)
+ * those which binding attribute is not STB_GLOBAL.
+ */
+ for (i = 0; i < sym_count; i++) {
+ COPYOUT(symtab + i, &sym, sizeof(sym));
+ if (ELF_ST_BIND(sym.st_info) != STB_GLOBAL ||
+ ELF_ST_TYPE(sym.st_info) != STT_NOTYPE)
+ continue;
+
+ strp = strdupout((vm_offset_t)(strtab + sym.st_name));
+ if (strcmp(strp, FDT_STATIC_DTB_SYMBOL) == 0) {
+ /* Found a match ! */
+ free(strp);
+ return ((vm_offset_t)(sym.st_value + offs));
+ }
+ free(strp);
+ }
+ return (0);
+}
+
+static int
+fdt_setup_fdtp()
+{
+ struct preloaded_file *bfp;
+ int err;
+
+ /*
+ * Find the device tree blob.
+ */
+ bfp = file_findfile(NULL, "dtb");
+ if (bfp == NULL) {
+ if ((fdtp = (struct fdt_header *)fdt_find_static_dtb()) == 0) {
+ command_errmsg = "no device tree blob found!";
+ return (CMD_ERROR);
+ }
+ } else {
+ /* Dynamic blob has precedence over static. */
+ fdtp = (struct fdt_header *)bfp->f_addr;
+ }
+
+ /*
+ * Validate the blob.
+ */
+ err = fdt_check_header(fdtp);
+ if (err < 0) {
+ if (err == -FDT_ERR_BADVERSION)
+ sprintf(command_errbuf,
+ "incompatible blob version: %d, should be: %d",
+ fdt_version(fdtp), FDT_LAST_SUPPORTED_VERSION);
+
+ else
+ sprintf(command_errbuf, "error validating blob: %s",
+ fdt_strerror(err));
+ return (CMD_ERROR);
+ }
+ return (CMD_OK);
+}
+
+#define fdt_strtovect(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \
+ (cellbuf), (lim), (cellsize), 0);
+
+/* Force using base 16 */
+#define fdt_strtovectx(str, cellbuf, lim, cellsize) _fdt_strtovect((str), \
+ (cellbuf), (lim), (cellsize), 16);
+
+static int
+_fdt_strtovect(char *str, void *cellbuf, int lim, unsigned char cellsize,
+ uint8_t base)
+{
+ char *buf = str;
+ char *end = str + strlen(str) - 2;
+ uint32_t *u32buf = NULL;
+ uint8_t *u8buf = NULL;
+ int cnt = 0;
+
+ if (cellsize == sizeof(uint32_t))
+ u32buf = (uint32_t *)cellbuf;
+ else
+ u8buf = (uint8_t *)cellbuf;
+
+ if (lim == 0)
+ return (0);
+
+ while (buf < end) {
+
+ /* Skip white whitespace(s)/separators */
+ while (!isxdigit(*buf) && buf < end)
+ buf++;
+
+ if (u32buf != NULL)
+ u32buf[cnt] =
+ cpu_to_fdt32((uint32_t)strtol(buf, NULL, base));
+
+ else
+ u8buf[cnt] = (uint8_t)strtol(buf, NULL, base);
+
+ if (cnt + 1 <= lim - 1)
+ cnt++;
+ else
+ break;
+ buf++;
+ /* Find another number */
+ while ((isxdigit(*buf) || *buf == 'x') && buf < end)
+ buf++;
+ }
+ return (cnt);
+}
+
+#define TMP_MAX_ETH 8
+
+void
+fixup_ethernet(const char *env, char *ethstr, int *eth_no, int len)
+{
+ char *end, *str;
+ uint8_t tmp_addr[6];
+ int i, n;
+
+ /* Extract interface number */
+ i = strtol(env + 3, &end, 10);
+ if (end == (env + 3))
+ /* 'ethaddr' means interface 0 address */
+ n = 0;
+ else
+ n = i;
+
+ if (n > TMP_MAX_ETH)
+ return;
+
+ str = ub_env_get(env);
+
+ /* Convert macaddr string into a vector of uints */
+ fdt_strtovectx(str, &tmp_addr, 6, sizeof(uint8_t));
+ if (n != 0) {
+ i = strlen(env) - 7;
+ strncpy(ethstr + 8, env + 3, i);
+ }
+ /* Set actual property to a value from vect */
+ fdt_setprop(fdtp, fdt_path_offset(fdtp, ethstr),
+ "local-mac-address", &tmp_addr, 6 * sizeof(uint8_t));
+
+ /* Clear ethernet..XXXX.. string */
+ bzero(ethstr + 8, len - 8);
+
+ if (n + 1 > *eth_no)
+ *eth_no = n + 1;
+}
+
+void
+fixup_cpubusfreqs(unsigned long cpufreq, unsigned long busfreq)
+{
+ int lo, o = 0, o2, maxo = 0, depth;
+ const uint32_t zero = 0;
+
+ /* We want to modify every subnode of /cpus */
+ o = fdt_path_offset(fdtp, "/cpus");
+
+ /* maxo should contain offset of node next to /cpus */
+ depth = 0;
+ maxo = o;
+ while (depth != -1)
+ maxo = fdt_next_node(fdtp, maxo, &depth);
+
+ /* Find CPU frequency properties */
+ o = fdt_node_offset_by_prop_value(fdtp, o, "clock-frequency",
+ &zero, sizeof(uint32_t));
+
+ o2 = fdt_node_offset_by_prop_value(fdtp, o, "bus-frequency", &zero,
+ sizeof(uint32_t));
+
+ lo = MIN(o, o2);
+
+ while (o != -FDT_ERR_NOTFOUND && o2 != -FDT_ERR_NOTFOUND) {
+
+ o = fdt_node_offset_by_prop_value(fdtp, lo,
+ "clock-frequency", &zero, sizeof(uint32_t));
+
+ o2 = fdt_node_offset_by_prop_value(fdtp, lo, "bus-frequency",
+ &zero, sizeof(uint32_t));
+
+ /* We're only interested in /cpus subnode(s) */
+ if (lo > maxo)
+ break;
+
+ fdt_setprop_inplace_cell(fdtp, lo, "clock-frequency",
+ (uint32_t)cpufreq);
+
+ fdt_setprop_inplace_cell(fdtp, lo, "bus-frequency",
+ (uint32_t)busfreq);
+
+ lo = MIN(o, o2);
+ }
+}
+
+int
+fdt_reg_valid(uint32_t *reg, int len, int addr_cells, int size_cells)
+{
+ int cells_in_tuple, i, tuples, tuple_size;
+ uint32_t cur_start, cur_size;
+
+ cells_in_tuple = (addr_cells + size_cells);
+ tuple_size = cells_in_tuple * sizeof(uint32_t);
+ tuples = len / tuple_size;
+ if (tuples == 0)
+ return (EINVAL);
+
+ for (i = 0; i < tuples; i++) {
+ if (addr_cells == 2)
+ cur_start = fdt64_to_cpu(reg[i * cells_in_tuple]);
+ else
+ cur_start = fdt32_to_cpu(reg[i * cells_in_tuple]);
+
+ if (size_cells == 2)
+ cur_size = fdt64_to_cpu(reg[i * cells_in_tuple + 2]);
+ else
+ cur_size = fdt32_to_cpu(reg[i * cells_in_tuple + 1]);
+
+ if (cur_size == 0)
+ return (EINVAL);
+
+ debugf(" reg#%d (start: 0x%0x size: 0x%0x) valid!\n",
+ i, cur_start, cur_size);
+ }
+ return (0);
+}
+
+void
+fixup_memory(struct sys_info *si)
+{
+ struct mem_region *curmr;
+ uint32_t addr_cells, size_cells;
+ uint32_t *addr_cellsp, *reg, *size_cellsp;
+ int err, i, len, memory, realmrno, root;
+ uint8_t *buf, *sb;
+
+ root = fdt_path_offset(fdtp, "/");
+ if (root < 0) {
+ sprintf(command_errbuf, "Could not find root node !");
+ return;
+ }
+
+ memory = fdt_path_offset(fdtp, "/memory");
+ if (memory <= 0) {
+ /* Create proper '/memory' node. */
+ memory = fdt_add_subnode(fdtp, root, "memory");
+ if (memory <= 0) {
+ sprintf(command_errbuf, "Could not fixup '/memory' "
+ "node, error code : %d!\n", memory);
+ return;
+ }
+
+ err = fdt_setprop(fdtp, memory, "device_type", "memory",
+ sizeof("memory"));
+
+ if (err < 0)
+ return;
+ }
+
+ addr_cellsp = (uint32_t *)fdt_getprop(fdtp, root, "#address-cells",
+ NULL);
+ size_cellsp = (uint32_t *)fdt_getprop(fdtp, root, "#size-cells", NULL);
+
+ if (addr_cellsp == NULL || size_cellsp == NULL) {
+ sprintf(command_errbuf, "Could not fixup '/memory' node : "
+ "%s %s property not found in root node!\n",
+ (!addr_cellsp) ? "#address-cells" : "",
+ (!size_cellsp) ? "#size-cells" : "");
+ return;
+ }
+
+ addr_cells = fdt32_to_cpu(*addr_cellsp);
+ size_cells = fdt32_to_cpu(*size_cellsp);
+
+ /* Count valid memory regions entries in sysinfo. */
+ realmrno = si->mr_no;
+ for (i = 0; i < si->mr_no; i++)
+ if (si->mr[i].start == 0 && si->mr[i].size == 0)
+ realmrno--;
+
+ if (realmrno == 0) {
+ sprintf(command_errbuf, "Could not fixup '/memory' node : "
+ "sysinfo doesn't contain valid memory regions info!\n");
+ return;
+ }
+
+ if ((reg = (uint32_t *)fdt_getprop(fdtp, memory, "reg",
+ &len)) != NULL) {
+
+ if (fdt_reg_valid(reg, len, addr_cells, size_cells) == 0)
+ /*
+ * Do not apply fixup if existing 'reg' property
+ * seems to be valid.
+ */
+ return;
+ }
+
+ len = (addr_cells + size_cells) * realmrno * sizeof(uint32_t);
+ sb = buf = (uint8_t *)malloc(len);
+ if (!buf)
+ return;
+
+ bzero(buf, len);
+
+ for (i = 0; i < si->mr_no; i++) {
+ curmr = &si->mr[i];
+ if (curmr->size != 0) {
+ /* Ensure endianess, and put cells into a buffer */
+ if (addr_cells == 2)
+ *(uint64_t *)buf =
+ cpu_to_fdt64(curmr->start);
+ else
+ *(uint32_t *)buf =
+ cpu_to_fdt32(curmr->start);
+
+ buf += sizeof(uint32_t) * addr_cells;
+ if (size_cells == 2)
+ *(uint64_t *)buf =
+ cpu_to_fdt64(curmr->size);
+ else
+ *(uint32_t *)buf =
+ cpu_to_fdt32(curmr->size);
+
+ buf += sizeof(uint32_t) * size_cells;
+ }
+ }
+
+ /* Set property */
+ if ((err = fdt_setprop(fdtp, memory, "reg", sb, len)) < 0)
+ sprintf(command_errbuf, "Could not fixup '/memory' node.\n");
+}
+
+void
+fixup_stdout(const char *env)
+{
+ const char *str;
+ char *ptr;
+ int serialno;
+ int len, no, sero;
+ const struct fdt_property *prop;
+ char *tmp[10];
+
+ str = ub_env_get(env);
+ ptr = (char *)str + strlen(str) - 1;
+ while (ptr > str && isdigit(*(str - 1)))
+ str--;
+
+ if (ptr == str)
+ return;
+
+ serialno = (int)strtol(ptr, NULL, 0);
+ no = fdt_path_offset(fdtp, "/chosen");
+ if (no < 0)
+ return;
+
+ prop = fdt_get_property(fdtp, no, "stdout", &len);
+
+ /* If /chosen/stdout does not extist, create it */
+ if (prop == NULL || (prop != NULL && len == 0)) {
+
+ bzero(tmp, 10 * sizeof(char));
+ strcpy((char *)&tmp, "serial");
+ if (strlen(ptr) > 3)
+ /* Serial number too long */
+ return;
+
+ strncpy((char *)tmp + 6, ptr, 3);
+ sero = fdt_path_offset(fdtp, (const char *)tmp);
+ if (sero < 0)
+ /*
+ * If serial device we're trying to assign
+ * stdout to doesn't exist in DT -- return.
+ */
+ return;
+
+ fdt_setprop(fdtp, no, "stdout", &tmp,
+ strlen((char *)&tmp) + 1);
+ fdt_setprop(fdtp, no, "stdin", &tmp,
+ strlen((char *)&tmp) + 1);
+ }
+}
+
+/*
+ * Locate the blob, fix it up and return its location.
+ */
+void *
+fdt_fixup(void)
+{
+ const char *env;
+ char *ethstr;
+ int chosen, err, eth_no, len;
+ struct sys_info *si;
+
+ env = NULL;
+ eth_no = 0;
+ ethstr = NULL;
+ len = 0;
+
+ err = fdt_setup_fdtp();
+ if (err) {
+ sprintf(command_errbuf, "No valid device tree blob found!");
+ return (NULL);
+ }
+
+ /* Create /chosen node (if not exists) */
+ if ((chosen = fdt_subnode_offset(fdtp, 0, "chosen")) ==
+ -FDT_ERR_NOTFOUND)
+ chosen = fdt_add_subnode(fdtp, 0, "chosen");
+
+ /* Value assigned to fixup-applied does not matter. */
+ if (fdt_getprop(fdtp, chosen, "fixup-applied", NULL))
+ goto success;
+
+ /* Acquire sys_info */
+ si = ub_get_sys_info();
+
+ while ((env = ub_env_enum(env)) != NULL) {
+ if (strncmp(env, "eth", 3) == 0 &&
+ strncmp(env + (strlen(env) - 4), "addr", 4) == 0) {
+ /*
+ * Handle Ethernet addrs: parse uboot env eth%daddr
+ */
+
+ if (!eth_no) {
+ /*
+ * Check how many chars we will need to store
+ * maximal eth iface number.
+ */
+ len = strlen(STRINGIFY(TMP_MAX_ETH)) +
+ strlen("ethernet");
+
+ /*
+ * Reserve mem for string "ethernet" and len
+ * chars for iface no.
+ */
+ ethstr = (char *)malloc(len * sizeof(char));
+ bzero(ethstr, len * sizeof(char));
+ strcpy(ethstr, "ethernet0");
+ }
+
+ /* Modify blob */
+ fixup_ethernet(env, ethstr, ð_no, len);
+
+ } else if (strcmp(env, "consoledev") == 0)
+ fixup_stdout(env);
+ }
+
+ /* Modify cpu(s) and bus clock frequenties in /cpus node [Hz] */
+ fixup_cpubusfreqs(si->clk_cpu, si->clk_bus);
+
+ /* Fixup memory regions */
+ fixup_memory(si);
+
+ fdt_setprop(fdtp, chosen, "fixup-applied", NULL, 0);
+
+success:
+ return (fdtp);
+}
+
+int
+command_fdt_internal(int argc, char *argv[])
+{
+ cmdf_t *cmdh;
+ char *cmd;
+ int i, err;
+
+ if (argc < 2) {
+ command_errmsg = "usage is 'fdt <command> [<args>]";
+ return (CMD_ERROR);
+ }
+
+ /*
+ * Check if uboot env vars were parsed already. If not, do it now.
+ */
+ if (fdt_fixup() == NULL)
+ return (CMD_ERROR);
+
+ /*
+ * Validate fdt <command>.
+ */
+ cmd = strdup(argv[1]);
+ i = 0;
+ cmdh = NULL;
+ while (!(commands[i].name == NULL)) {
+ if (strcmp(cmd, commands[i].name) == 0) {
+ /* found it */
+ cmdh = commands[i].handler;
+ break;
+ }
+ i++;
+ }
+ if (cmdh == NULL) {
+ command_errmsg = "unknown command";
+ return (CMD_ERROR);
+ }
+
+ /*
+ * Call command handler.
+ */
+ err = (*cmdh)(argc, argv);
+
+ return (err);
+}
+
+static int
+fdt_cmd_cd(int argc, char *argv[])
+{
+ char *path;
+ char tmp[FDT_CWD_LEN];
+ int len, o;
+
+ path = (argc > 2) ? argv[2] : "/";
+
+ if (path[0] == '/') {
+ len = strlen(path);
+ if (len >= FDT_CWD_LEN)
+ goto fail;
+ } else {
+ /* Handle path specification relative to cwd */
+ len = strlen(cwd) + strlen(path) + 1;
+ if (len >= FDT_CWD_LEN)
+ goto fail;
+
+ strcpy(tmp, cwd);
+ strcat(tmp, "/");
+ strcat(tmp, path);
+ path = tmp;
+ }
+
+ o = fdt_path_offset(fdtp, path);
+ if (o < 0) {
+ sprintf(command_errbuf, "could not find node: '%s'", path);
+ return (CMD_ERROR);
+ }
+
+ strcpy(cwd, path);
+ return (CMD_OK);
+
+fail:
+ sprintf(command_errbuf, "path too long: %d, max allowed: %d",
+ len, FDT_CWD_LEN - 1);
+ return (CMD_ERROR);
+}
+
+static int
+fdt_cmd_hdr(int argc __unused, char *argv[] __unused)
+{
+ char line[80];
+ int ver;
+
+ if (fdtp == NULL) {
+ command_errmsg = "no device tree blob pointer?!";
+ return (CMD_ERROR);
+ }
+
+ ver = fdt_version(fdtp);
+ pager_open();
+ sprintf(line, "\nFlattened device tree header (%p):\n", fdtp);
+ pager_output(line);
+ sprintf(line, " magic = 0x%08x\n", fdt_magic(fdtp));
+ pager_output(line);
+ sprintf(line, " size = %d\n", fdt_totalsize(fdtp));
+ pager_output(line);
+ sprintf(line, " off_dt_struct = 0x%08x\n",
+ fdt_off_dt_struct(fdtp));
+ pager_output(line);
+ sprintf(line, " off_dt_strings = 0x%08x\n",
+ fdt_off_dt_strings(fdtp));
+ pager_output(line);
+ sprintf(line, " off_mem_rsvmap = 0x%08x\n",
+ fdt_off_mem_rsvmap(fdtp));
+ pager_output(line);
+ sprintf(line, " version = %d\n", ver);
+ pager_output(line);
+ sprintf(line, " last compatible version = %d\n",
+ fdt_last_comp_version(fdtp));
+ pager_output(line);
+ if (ver >= 2) {
+ sprintf(line, " boot_cpuid = %d\n",
+ fdt_boot_cpuid_phys(fdtp));
+ pager_output(line);
+ }
+ if (ver >= 3) {
+ sprintf(line, " size_dt_strings = %d\n",
+ fdt_size_dt_strings(fdtp));
+ pager_output(line);
+ }
+ if (ver >= 17) {
+ sprintf(line, " size_dt_struct = %d\n",
+ fdt_size_dt_struct(fdtp));
+ pager_output(line);
+ }
+ pager_close();
+
+ return (CMD_OK);
+}
+
+static int
+fdt_cmd_ls(int argc, char *argv[])
+{
+ const char *prevname[FDT_MAX_DEPTH] = { NULL };
+ const char *name;
+ char *path;
+ int i, o, depth, len;
+
+ path = (argc > 2) ? argv[2] : NULL;
+ if (path == NULL)
+ path = cwd;
+
+ o = fdt_path_offset(fdtp, path);
+ if (o < 0) {
+ sprintf(command_errbuf, "could not find node: '%s'", path);
+ return (CMD_ERROR);
+ }
+
+ for (depth = 0;
+ (o >= 0) && (depth >= 0);
+ o = fdt_next_node(fdtp, o, &depth)) {
+
+ name = fdt_get_name(fdtp, o, &len);
+
+ if (depth > FDT_MAX_DEPTH) {
+ printf("max depth exceeded: %d\n", depth);
+ continue;
+ }
+
+ prevname[depth] = name;
+
+ /* Skip root (i = 1) when printing devices */
+ for (i = 1; i <= depth; i++) {
+ if (prevname[i] == NULL)
+ break;
+
+ if (strcmp(cwd, "/") == 0)
+ printf("/");
+ printf("%s", prevname[i]);
+ }
+ printf("\n");
+ }
+
+ return (CMD_OK);
+}
+
+static __inline int
+isprint(int c)
+{
+
+ return (c >= ' ' && c <= 0x7e);
+}
+
+static int
+fdt_isprint(const void *data, int len, int *count)
+{
+ const char *d;
+ char ch;
+ int yesno, i;
+
+ if (len == 0)
+ return (0);
+
+ d = (const char *)data;
+ if (d[len - 1] != '\0')
+ return (0);
+
+ *count = 0;
+ yesno = 1;
+ for (i = 0; i < len; i++) {
+ ch = *(d + i);
+ if (isprint(ch) || (ch == '\0' && i > 0)) {
+ /* Count strings */
+ if (ch == '\0')
+ (*count)++;
+ continue;
+ }
+
+ yesno = 0;
+ break;
+ }
+
+ return (yesno);
+}
+
+static int
+fdt_data_str(const void *data, int len, int count, char **buf)
+{
+ char *b, *tmp;
+ const char *d;
+ int buf_len, i, l;
+
+ /*
+ * Calculate the length for the string and allocate memory.
+ *
+ * Note that 'len' already includes at least one terminator.
+ */
+ buf_len = len;
+ if (count > 1) {
+ /*
+ * Each token had already a terminator buried in 'len', but we
+ * only need one eventually, don't count space for these.
+ */
+ buf_len -= count - 1;
+
+ /* Each consecutive token requires a ", " separator. */
+ buf_len += count * 2;
+ }
+
+ /* Add some space for surrounding double quotes. */
+ buf_len += count * 2;
+
+ /* Note that string being put in 'tmp' may be as big as 'buf_len'. */
+ b = (char *)malloc(buf_len);
+ tmp = (char *)malloc(buf_len);
+ if (b == NULL)
+ goto error;
+
+ if (tmp == NULL) {
+ free(b);
+ goto error;
+ }
+
+ b[0] = '\0';
+
+ /*
+ * Now that we have space, format the string.
+ */
+ i = 0;
+ do {
+ d = (const char *)data + i;
+ l = strlen(d) + 1;
+
+ sprintf(tmp, "\"%s\"%s", d,
+ (i + l) < len ? ", " : "");
+ strcat(b, tmp);
+
+ i += l;
+
+ } while (i < len);
+ *buf = b;
+
+ free(tmp);
+
+ return (0);
+error:
+ return (1);
+}
+
+static int
+fdt_data_cell(const void *data, int len, char **buf)
+{
+ char *b, *tmp;
+ const uint32_t *c;
+ int count, i, l;
+
+ /* Number of cells */
+ count = len / 4;
+
+ /*
+ * Calculate the length for the string and allocate memory.
+ */
+
+ /* Each byte translates to 2 output characters */
+ l = len * 2;
+ if (count > 1) {
+ /* Each consecutive cell requires a " " separator. */
+ l += (count - 1) * 1;
+ }
+ /* Each cell will have a "0x" prefix */
+ l += count * 2;
+ /* Space for surrounding <> and terminator */
+ l += 3;
+
+ b = (char *)malloc(l);
+ tmp = (char *)malloc(l);
+ if (b == NULL)
+ goto error;
+
+ if (tmp == NULL) {
+ free(b);
+ goto error;
+ }
+
+ b[0] = '\0';
+ strcat(b, "<");
+
+ for (i = 0; i < len; i += 4) {
+ c = (const uint32_t *)((const uint8_t *)data + i);
+ sprintf(tmp, "0x%08x%s", fdt32_to_cpu(*c),
+ i < (len - 4) ? " " : "");
+ strcat(b, tmp);
+ }
+ strcat(b, ">");
+ *buf = b;
+
+ free(tmp);
+
+ return (0);
+error:
+ return (1);
+}
+
+static int
+fdt_data_bytes(const void *data, int len, char **buf)
+{
+ char *b, *tmp;
+ const char *d;
+ int i, l;
+
+ /*
+ * Calculate the length for the string and allocate memory.
+ */
+
+ /* Each byte translates to 2 output characters */
+ l = len * 2;
+ if (len > 1)
+ /* Each consecutive byte requires a " " separator. */
+ l += (len - 1) * 1;
+ /* Each byte will have a "0x" prefix */
+ l += len * 2;
+ /* Space for surrounding [] and terminator. */
+ l += 3;
+
+ b = (char *)malloc(l);
+ tmp = (char *)malloc(l);
+ if (b == NULL)
+ goto error;
+
+ if (tmp == NULL) {
+ free(b);
+ goto error;
+ }
+
+ b[0] = '\0';
+ strcat(b, "[");
+
+ for (i = 0, d = data; i < len; i++) {
+ sprintf(tmp, "0x%02x%s", d[i], i < len - 1 ? " " : "");
+ strcat(b, tmp);
+ }
+ strcat(b, "]");
+ *buf = b;
+
+ free(tmp);
+
+ return (0);
+error:
+ return (1);
+}
+
+static int
+fdt_data_fmt(const void *data, int len, char **buf)
+{
+ int count;
+
+ if (len == 0) {
+ *buf = NULL;
+ return (1);
+ }
+
+ if (fdt_isprint(data, len, &count))
+ return (fdt_data_str(data, len, count, buf));
+
+ else if ((len % 4) == 0)
+ return (fdt_data_cell(data, len, buf));
+
+ else
+ return (fdt_data_bytes(data, len, buf));
+}
+
+static int
+fdt_prop(int offset)
+{
+ char *line, *buf;
+ const struct fdt_property *prop;
+ const char *name;
+ const void *data;
+ int len, rv;
+
+ line = NULL;
+ prop = fdt_offset_ptr(fdtp, offset, sizeof(*prop));
+ if (prop == NULL)
+ return (1);
+
+ name = fdt_string(fdtp, fdt32_to_cpu(prop->nameoff));
+ len = fdt32_to_cpu(prop->len);
+
+ rv = 0;
+ buf = NULL;
+ if (len == 0) {
+ /* Property without value */
+ line = (char *)malloc(strlen(name) + 2);
+ if (line == NULL) {
+ rv = 2;
+ goto out2;
+ }
+ sprintf(line, "%s\n", name);
+ goto out1;
+ }
+
+ /*
+ * Process property with value
+ */
+ data = prop->data;
+
+ if (fdt_data_fmt(data, len, &buf) != 0) {
+ rv = 3;
+ goto out2;
+ }
+
+ line = (char *)malloc(strlen(name) + strlen(FDT_PROP_SEP) +
+ strlen(buf) + 2);
+ if (line == NULL) {
+ sprintf(command_errbuf, "could not allocate space for string");
+ rv = 4;
+ goto out2;
+ }
+
+ sprintf(line, "%s" FDT_PROP_SEP "%s\n", name, buf);
+
+out1:
+ pager_open();
+ pager_output(line);
+ pager_close();
+
+out2:
+ if (buf)
+ free(buf);
+
+ if (line)
+ free(line);
+
+ return (rv);
+}
+
+static int
+fdt_modprop(int nodeoff, char *propname, void *value, char mode)
+{
+ uint32_t cells[100];
+ char *buf;
+ int len, rv;
+ const struct fdt_property *p;
+
+ p = fdt_get_property(fdtp, nodeoff, propname, NULL);
+
+ if (p != NULL) {
+ if (mode == 1) {
+ /* Adding inexistant value in mode 1 is forbidden */
+ sprintf(command_errbuf, "property already exists!");
+ return (CMD_ERROR);
+ }
+ } else if (mode == 0) {
+ sprintf(command_errbuf, "property does not exist!");
+ return (CMD_ERROR);
+ }
+ len = strlen(value);
+ rv = 0;
+ buf = (char *)value;
+
+ switch (*buf) {
+ case '&':
+ /* phandles */
+ break;
+ case '<':
+ /* Data cells */
+ len = fdt_strtovect(buf, (void *)&cells, 100,
+ sizeof(uint32_t));
+
+ rv = fdt_setprop(fdtp, nodeoff, propname, &cells,
+ len * sizeof(uint32_t));
+ break;
+ case '[':
+ /* Data bytes */
+ len = fdt_strtovect(buf, (void *)&cells, 100,
+ sizeof(uint8_t));
+
+ rv = fdt_setprop(fdtp, nodeoff, propname, &cells,
+ len * sizeof(uint8_t));
+ break;
+ case '"':
+ default:
+ /* Default -- string */
+ rv = fdt_setprop_string(fdtp, nodeoff, propname, value);
+ break;
+ }
+
+ if (rv != 0) {
+ if (rv == -FDT_ERR_NOSPACE)
+ sprintf(command_errbuf,
+ "Device tree blob is too small!\n");
+ else
+ sprintf(command_errbuf,
+ "Could not add/modify property!\n");
+ }
+ return (rv);
+}
+
+/* Merge strings from argv into a single string */
+static int
+fdt_merge_strings(int argc, char *argv[], int start, char **buffer)
+{
+ char *buf;
+ int i, idx, sz;
+
+ *buffer = NULL;
+ sz = 0;
+
+ for (i = start; i < argc; i++)
+ sz += strlen(argv[i]);
+
+ /* Additional bytes for whitespaces between args */
+ sz += argc - start;
+
+ buf = (char *)malloc(sizeof(char) * sz);
+ bzero(buf, sizeof(char) * sz);
+
+ if (buf == NULL) {
+ sprintf(command_errbuf, "could not allocate space "
+ "for string");
+ return (1);
+ }
+
+ idx = 0;
+ for (i = start, idx = 0; i < argc; i++) {
+ strcpy(buf + idx, argv[i]);
+ idx += strlen(argv[i]);
+ buf[idx] = ' ';
+ idx++;
+ }
+ buf[sz - 1] = '\0';
+ *buffer = buf;
+ return (0);
+}
+
+/* Extract offset and name of node/property from a given path */
+static int
+fdt_extract_nameloc(char **pathp, char **namep, int *nodeoff)
+{
+ int o;
+ char *path = *pathp, *name = NULL, *subpath = NULL;
+
+ subpath = strrchr(path, '/');
+ if (subpath == NULL) {
+ o = fdt_path_offset(fdtp, cwd);
+ name = path;
+ path = (char *)&cwd;
+ } else {
+ *subpath = '\0';
+ if (strlen(path) == 0)
+ path = cwd;
+
+ name = subpath + 1;
+ o = fdt_path_offset(fdtp, path);
+ }
+
+ if (strlen(name) == 0) {
+ sprintf(command_errbuf, "name not specified");
+ return (1);
+ }
+ if (o < 0) {
+ sprintf(command_errbuf, "could not find node: '%s'", path);
+ return (1);
+ }
+ *namep = name;
+ *nodeoff = o;
+ *pathp = path;
+ return (0);
+}
+
+static int
+fdt_cmd_prop(int argc, char *argv[])
+{
+ char *path, *propname, *value;
+ int o, next, depth, rv;
+ uint32_t tag;
+
+ path = (argc > 2) ? argv[2] : NULL;
+
+ value = NULL;
+
+ if (argc > 3) {
+ /* Merge property value strings into one */
+ if (fdt_merge_strings(argc, argv, 3, &value) != 0)
+ return (CMD_ERROR);
+ } else
+ value = NULL;
+
+ if (path == NULL)
+ path = cwd;
+
+ rv = CMD_OK;
+
+ if (value) {
+ /* If value is specified -- try to modify prop. */
+ if (fdt_extract_nameloc(&path, &propname, &o) != 0)
+ return (CMD_ERROR);
+
+ rv = fdt_modprop(o, propname, value, 0);
+ if (rv)
+ return (CMD_ERROR);
+ return (CMD_OK);
+
+ }
+ /* User wants to display properties */
+ o = fdt_path_offset(fdtp, path);
+
+ if (o < 0) {
+ sprintf(command_errbuf, "could not find node: '%s'", path);
+ rv = CMD_ERROR;
+ goto out;
+ }
+
+ depth = 0;
+ while (depth >= 0) {
+ tag = fdt_next_tag(fdtp, o, &next);
+ switch (tag) {
+ case FDT_NOP:
+ break;
+ case FDT_PROP:
+ if (depth > 1)
+ /* Don't process properties of nested nodes */
+ break;
+
+ if (fdt_prop(o) != 0) {
+ sprintf(command_errbuf, "could not process "
+ "property");
+ rv = CMD_ERROR;
+ goto out;
+ }
+ break;
+ case FDT_BEGIN_NODE:
+ depth++;
+ if (depth > FDT_MAX_DEPTH) {
+ printf("warning: nesting too deep: %d\n",
+ depth);
+ goto out;
+ }
+ break;
+ case FDT_END_NODE:
+ depth--;
+ if (depth == 0)
+ /*
+ * This is the end of our starting node, force
+ * the loop finish.
+ */
+ depth--;
+ break;
+ }
+ o = next;
+ }
+out:
+ return (rv);
+}
+
+static int
+fdt_cmd_mkprop(int argc, char *argv[])
+{
+ int o;
+ char *path, *propname, *value;
+
+ path = (argc > 2) ? argv[2] : NULL;
+
+ value = NULL;
+
+ if (argc > 3) {
+ /* Merge property value strings into one */
+ if (fdt_merge_strings(argc, argv, 3, &value) != 0)
+ return (CMD_ERROR);
+ } else
+ value = NULL;
+
+ if (fdt_extract_nameloc(&path, &propname, &o) != 0)
+ return (CMD_ERROR);
+
+ if (fdt_modprop(o, propname, value, 1))
+ return (CMD_ERROR);
+
+ return (CMD_OK);
+}
+
+static int
+fdt_cmd_rm(int argc, char *argv[])
+{
+ int o, rv;
+ char *path = NULL, *propname;
+
+ if (argc > 2)
+ path = argv[2];
+ else {
+ sprintf(command_errbuf, "no node/property name specified");
+ return (CMD_ERROR);
+ }
+
+ o = fdt_path_offset(fdtp, path);
+ if (o < 0) {
+ /* If node not found -- try to find & delete property */
+ if (fdt_extract_nameloc(&path, &propname, &o) != 0)
+ return (CMD_ERROR);
+
+ if ((rv = fdt_delprop(fdtp, o, propname)) != 0) {
+ sprintf(command_errbuf, "could not delete"
+ "%s\n", (rv == -FDT_ERR_NOTFOUND) ?
+ "(property/node does not exist)" : "");
+ return (CMD_ERROR);
+
+ } else
+ return (CMD_OK);
+ }
+ /* If node exists -- remove node */
+ rv = fdt_del_node(fdtp, o);
+ if (rv) {
+ sprintf(command_errbuf, "could not delete node");
+ return (CMD_ERROR);
+ }
+ return (CMD_OK);
+}
+
+static int
+fdt_cmd_mknode(int argc, char *argv[])
+{
+ int o, rv;
+ char *path = NULL, *nodename = NULL;
+
+ if (argc > 2)
+ path = argv[2];
+ else {
+ sprintf(command_errbuf, "no node name specified");
+ return (CMD_ERROR);
+ }
+
+ if (fdt_extract_nameloc(&path, &nodename, &o) != 0)
+ return (CMD_ERROR);
+
+ rv = fdt_add_subnode(fdtp, o, nodename);
+
+ if (rv < 0) {
+ if (rv == -FDT_ERR_NOSPACE)
+ sprintf(command_errbuf,
+ "Device tree blob is too small!\n");
+ else
+ sprintf(command_errbuf,
+ "Could not add node!\n");
+ return (CMD_ERROR);
+ }
+ return (CMD_OK);
+}
+
+static int
+fdt_cmd_pwd(int argc, char *argv[])
+{
+ char line[FDT_CWD_LEN];
+
+ pager_open();
+ sprintf(line, "%s\n", cwd);
+ pager_output(line);
+ pager_close();
+ return (CMD_OK);
+}
+
+static int
+fdt_cmd_nyi(int argc, char *argv[])
+{
+
+ printf("command not yet implemented\n");
+ return (CMD_ERROR);
+}
Property changes on: trunk/sys/boot/fdt/fdt_loader_cmd.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
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