[Midnightbsd-cvs] src [9885] trunk/sys/boot/arm: arm
laffer1 at midnightbsd.org
laffer1 at midnightbsd.org
Thu May 24 07:40:02 EDT 2018
Revision: 9885
http://svnweb.midnightbsd.org/src/?rev=9885
Author: laffer1
Date: 2018-05-24 07:40:01 -0400 (Thu, 24 May 2018)
Log Message:
-----------
arm
Added Paths:
-----------
trunk/sys/boot/arm/
trunk/sys/boot/arm/Makefile
trunk/sys/boot/arm/Makefile.inc
trunk/sys/boot/arm/at91/
trunk/sys/boot/arm/at91/Makefile
trunk/sys/boot/arm/at91/Makefile.inc
trunk/sys/boot/arm/at91/boot0/
trunk/sys/boot/arm/at91/boot0/Makefile
trunk/sys/boot/arm/at91/boot0/README
trunk/sys/boot/arm/at91/boot0/linker.cfg
trunk/sys/boot/arm/at91/boot0/main.c
trunk/sys/boot/arm/at91/boot0iic/
trunk/sys/boot/arm/at91/boot0iic/Makefile
trunk/sys/boot/arm/at91/boot0iic/main.c
trunk/sys/boot/arm/at91/boot0spi/
trunk/sys/boot/arm/at91/boot0spi/Makefile
trunk/sys/boot/arm/at91/boot0spi/main.c
trunk/sys/boot/arm/at91/boot2/
trunk/sys/boot/arm/at91/boot2/Makefile
trunk/sys/boot/arm/at91/boot2/board.h
trunk/sys/boot/arm/at91/boot2/boot2.c
trunk/sys/boot/arm/at91/boot2/bwct_board.c
trunk/sys/boot/arm/at91/boot2/centipad_board.c
trunk/sys/boot/arm/at91/boot2/kb920x_board.c
trunk/sys/boot/arm/at91/bootiic/
trunk/sys/boot/arm/at91/bootiic/Makefile
trunk/sys/boot/arm/at91/bootiic/README
trunk/sys/boot/arm/at91/bootiic/env_vars.c
trunk/sys/boot/arm/at91/bootiic/env_vars.h
trunk/sys/boot/arm/at91/bootiic/loader_prompt.c
trunk/sys/boot/arm/at91/bootiic/loader_prompt.h
trunk/sys/boot/arm/at91/bootiic/main.c
trunk/sys/boot/arm/at91/bootspi/
trunk/sys/boot/arm/at91/bootspi/Makefile
trunk/sys/boot/arm/at91/bootspi/README
trunk/sys/boot/arm/at91/bootspi/ee.c
trunk/sys/boot/arm/at91/bootspi/ee.h
trunk/sys/boot/arm/at91/bootspi/env_vars.c
trunk/sys/boot/arm/at91/bootspi/env_vars.h
trunk/sys/boot/arm/at91/bootspi/loader_prompt.c
trunk/sys/boot/arm/at91/bootspi/loader_prompt.h
trunk/sys/boot/arm/at91/bootspi/main.c
trunk/sys/boot/arm/at91/libat91/
trunk/sys/boot/arm/at91/libat91/Makefile
trunk/sys/boot/arm/at91/libat91/arm_init.S
trunk/sys/boot/arm/at91/libat91/at91rm9200.h
trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c
trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.h
trunk/sys/boot/arm/at91/libat91/delay.c
trunk/sys/boot/arm/at91/libat91/eeprom.c
trunk/sys/boot/arm/at91/libat91/emac.c
trunk/sys/boot/arm/at91/libat91/emac.h
trunk/sys/boot/arm/at91/libat91/emac_init.c
trunk/sys/boot/arm/at91/libat91/getc.c
trunk/sys/boot/arm/at91/libat91/lib.h
trunk/sys/boot/arm/at91/libat91/lib_AT91RM9200.h
trunk/sys/boot/arm/at91/libat91/mci_device.h
trunk/sys/boot/arm/at91/libat91/memcmp.c
trunk/sys/boot/arm/at91/libat91/memcpy.c
trunk/sys/boot/arm/at91/libat91/memset.c
trunk/sys/boot/arm/at91/libat91/p_string.c
trunk/sys/boot/arm/at91/libat91/printf.c
trunk/sys/boot/arm/at91/libat91/putchar.c
trunk/sys/boot/arm/at91/libat91/reset.c
trunk/sys/boot/arm/at91/libat91/sd-card.c
trunk/sys/boot/arm/at91/libat91/sd-card.h
trunk/sys/boot/arm/at91/libat91/spi_flash.c
trunk/sys/boot/arm/at91/libat91/spi_flash.h
trunk/sys/boot/arm/at91/libat91/strcmp.c
trunk/sys/boot/arm/at91/libat91/strcpy.c
trunk/sys/boot/arm/at91/libat91/strcvt.c
trunk/sys/boot/arm/at91/libat91/strlen.c
trunk/sys/boot/arm/at91/libat91/tag_list.c
trunk/sys/boot/arm/at91/libat91/tag_list.h
trunk/sys/boot/arm/at91/libat91/xmodem.c
trunk/sys/boot/arm/at91/linker.cfg
trunk/sys/boot/arm/ixp425/
trunk/sys/boot/arm/ixp425/Makefile.inc
trunk/sys/boot/arm/ixp425/boot2/
trunk/sys/boot/arm/ixp425/boot2/Makefile
trunk/sys/boot/arm/ixp425/boot2/arm_init.S
trunk/sys/boot/arm/ixp425/boot2/boot2.c
trunk/sys/boot/arm/ixp425/boot2/cf_ata.h
trunk/sys/boot/arm/ixp425/boot2/ixp425_board.c
trunk/sys/boot/arm/ixp425/boot2/lib.h
trunk/sys/boot/arm/uboot/
trunk/sys/boot/arm/uboot/Makefile
trunk/sys/boot/arm/uboot/conf.c
trunk/sys/boot/arm/uboot/help.uboot
trunk/sys/boot/arm/uboot/ldscript.arm
trunk/sys/boot/arm/uboot/start.S
trunk/sys/boot/arm/uboot/version
Added: trunk/sys/boot/arm/Makefile
===================================================================
--- trunk/sys/boot/arm/Makefile (rev 0)
+++ trunk/sys/boot/arm/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,5 @@
+# $MidnightBSD$
+
+SUBDIR= uboot
+
+.include <bsd.subdir.mk>
Property changes on: trunk/sys/boot/arm/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/Makefile.inc
===================================================================
--- trunk/sys/boot/arm/Makefile.inc (rev 0)
+++ trunk/sys/boot/arm/Makefile.inc 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,3 @@
+# $MidnightBSD$ */
+
+.include "../Makefile.inc"
Property changes on: trunk/sys/boot/arm/Makefile.inc
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,5 @@
+# $MidnightBSD$
+
+SUBDIR= libat91 boot0 boot0iic boot0spi boot2 bootiic bootspi
+
+.include <bsd.subdir.mk>
Property changes on: trunk/sys/boot/arm/at91/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/Makefile.inc
===================================================================
--- trunk/sys/boot/arm/at91/Makefile.inc (rev 0)
+++ trunk/sys/boot/arm/at91/Makefile.inc 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,57 @@
+# $MidnightBSD$
+
+.if !target(__at91_boot_Makefile.inc__)
+.PATH: ${.CURDIR}/../../../../libkern ${.CURDIR}/../../../../libkern/arm
+
+__at91_boot_Makefile.inc__:
+
+# tsc, bwct, kb920x, centipad are the supported flavors
+BOOT_FLAVOR?=kb920x
+
+CFLAGS=-Os -mcpu=arm9 -ffreestanding \
+ -I${.CURDIR}/../libat91 \
+ -I${.CURDIR}/../../../.. \
+ -I${.CURDIR}/../../../../arm \
+ -D_KERNEL \
+ -Wall -Waggregate-return \
+ -Wnested-externs \
+ -Wpointer-arith -Wshadow -Wwrite-strings \
+ -Werror \
+ -Wmissing-prototypes \
+ -Wmissing-declarations
+# -Wstrict-prototypes
+
+CFLAGS+=-DBOOT_${BOOT_FLAVOR:U}
+
+LIBAT91=${.OBJDIR}/../libat91/libat91.a
+
+LD ?= ld
+OBJCOPY ?= objcopy
+
+.if defined(P)
+${P}: ${P}.out
+ ${OBJCOPY} -S -O binary ${P}.out ${.TARGET}
+ @set -- `ls -l ${.TARGET}`; x=$$((12288-$$5)); \
+ echo "$$x bytes available"; test $$x -ge 0
+
+${P}.out: ${OBJS}
+ ${LD} ${LDFLAGS} -o ${.TARGET} ${OBJS} ${LIBAT91}
+
+CLEANFILES+= ${P} ${P}.out
+.endif
+
+.if defined(WITH_TAG_LIST)
+MK_TAG_LIST:=yes
+.else
+MK_TAG_LIST:=no
+.endif
+
+.if defined(WITH_FPGA)
+MK_FPGA:=yes
+.else
+MK_FPGA:=no
+.endif
+
+.endif
+
+.include "../Makefile.inc"
Property changes on: trunk/sys/boot/arm/at91/Makefile.inc
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/boot0/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/boot0/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,14 @@
+# $MidnightBSD$
+
+.PATH: ${.CURDIR}/../libat91
+
+P=boot0
+FILES=${P}
+SRCS=arm_init.S main.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+CFLAGS+=-DBOOT_BOOT0
Property changes on: trunk/sys/boot/arm/at91/boot0/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0/README
===================================================================
--- trunk/sys/boot/arm/at91/boot0/README (rev 0)
+++ trunk/sys/boot/arm/at91/boot0/README 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,7 @@
+This is a bootstrap bootloader. It is intended to be used when the
+AT91RM9200 is running xmodem over DBGU. It will download the next stage
+of the booting process (or the recovery program) and jump to it. It loads
+the program at a 1MB offset into SDRAM. Programs are expected to be
+smaller than this and copy themselves to the right location.
+
+$MidnightBSD$
Property changes on: trunk/sys/boot/arm/at91/boot0/README
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0/linker.cfg
===================================================================
--- trunk/sys/boot/arm/at91/boot0/linker.cfg (rev 0)
+++ trunk/sys/boot/arm/at91/boot0/linker.cfg 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,84 @@
+/*******************************************************************************
+ *
+ * Filename: linker.cfg
+ *
+ * linker config file used for internal RAM or eeprom images at address 0.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin move data to SDRAM
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $MidnightBSD$
+ ******************************************************************************/
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(start)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = 0;
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ *(.stub)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ }
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .data :
+ {
+ __data_start = . ;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ __bss_start__ = .;
+ .sbss :
+ {
+ PROVIDE (__sbss_start = .);
+ PROVIDE (___sbss_start = .);
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ PROVIDE (__sbss_end = .);
+ PROVIDE (___sbss_end = .);
+ }
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ }
+ . = ALIGN(32 / 8);
+ _end = .;
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+ PROVIDE (end = .);
+}
Property changes on: trunk/sys/boot/arm/at91/boot0/linker.cfg
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0/main.c
===================================================================
--- trunk/sys/boot/arm/at91/boot0/main.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot0/main.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,44 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "lib.h"
+#include "at91rm9200_lowlevel.h"
+
+typedef void fn_t(void);
+
+int
+main(void)
+{
+ char *addr = (char *)SDRAM_BASE + (1 << 20); /* Load to base + 1MB */
+ fn_t *fn = (fn_t *)(SDRAM_BASE + (1 << 20)); /* Load to base + 1MB */
+
+ while (xmodem_rx(addr) == -1)
+ continue;
+ fn();
+ return (0);
+}
Property changes on: trunk/sys/boot/arm/at91/boot0/main.c
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0iic/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/boot0iic/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/boot0iic/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,14 @@
+# $MidnightBSD$
+
+.PATH: ${.CURDIR}/../libat91
+
+P=boot0iic
+FILES=${P}
+SRCS=arm_init.S main.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/../linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+CFLAGS+=-DBOOT_BOOT0
Property changes on: trunk/sys/boot/arm/at91/boot0iic/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0iic/main.c
===================================================================
--- trunk/sys/boot/arm/at91/boot0iic/main.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot0iic/main.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,50 @@
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $MidnightBSD$
+ */
+
+#include "at91rm9200.h"
+#include "lib.h"
+#include "at91rm9200_lowlevel.h"
+
+int
+main(void)
+{
+ char *addr = (char *)SDRAM_BASE + (1 << 20); /* Load to base + 1MB */
+ int len, sec;
+
+ printf("\nSend data to be written into EEPROM\n");
+ while ((len = xmodem_rx(addr)) == -1)
+ continue;
+ sec = GetSeconds() + 1;
+ while (sec >= GetSeconds())
+ continue;
+ printf("\nWriting EEPROM from 0x%x to addr 0, 0x%x bytes\n", addr,
+ len);
+ InitEEPROM();
+ printf("init done\n");
+ WriteEEPROM(0, addr, len);
+ printf("\nWrote %d bytes. Press reset\n", len);
+ return (1);
+}
Property changes on: trunk/sys/boot/arm/at91/boot0iic/main.c
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0spi/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/boot0spi/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/boot0spi/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,14 @@
+# $MidnightBSD$
+
+.PATH: ${.CURDIR}/../libat91
+
+P=boot0spi
+FILES=${P}
+SRCS=arm_init.S main.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/../linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+CFLAGS+=-DBOOT_BOOT0
Property changes on: trunk/sys/boot/arm/at91/boot0spi/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot0spi/main.c
===================================================================
--- trunk/sys/boot/arm/at91/boot0spi/main.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot0spi/main.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,68 @@
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $MidnightBSD$
+ */
+
+#include "at91rm9200.h"
+#include "lib.h"
+#include "at91rm9200_lowlevel.h"
+#include "spi_flash.h"
+
+#define LOADER_OFFSET 0
+#define FPGA_OFFSET (15 * FLASH_PAGE_SIZE)
+#define OFFSET FPGA_OFFSET
+
+int
+main(void)
+{
+ int len, i, j, off, sec;
+ char *addr = (char *)SDRAM_BASE + (1 << 20); /* download at + 1MB */
+ char *addr2 = (char *)SDRAM_BASE + (2 << 20); /* readback to + 2MB */
+ char *addr3 = (char *)SDRAM_BASE + (3 << 20); /* extra copy at + 3MB */
+
+ SPI_InitFlash();
+ printf("Waiting for data\n");
+ while ((len = xmodem_rx(addr)) == -1)
+ continue;
+ // Need extra copy at addr3
+ memcpy(addr3, addr, (len + FLASH_PAGE_SIZE - 1) / FLASH_PAGE_SIZE * FLASH_PAGE_SIZE);
+ printf("Writing %u bytes to flash at %u\n", len, OFFSET);
+ for (i = 0; i < len; i+= FLASH_PAGE_SIZE) {
+ for (j = 0; j < 10; j++) {
+ off = i + OFFSET;
+ SPI_WriteFlash(off, addr + i, FLASH_PAGE_SIZE);
+ SPI_ReadFlash(off, addr2 + i, FLASH_PAGE_SIZE);
+ if (p_memcmp(addr3 + i, addr2 + i, FLASH_PAGE_SIZE) == 0)
+ break;
+ }
+ if (j >= 10)
+ printf("Bad Readback at %u\n", i);
+ }
+ sec = GetSeconds() + 2;
+ while (sec <= GetSeconds())
+ continue;
+ printf("Done\n");
+ reset();
+ return (1);
+}
Property changes on: trunk/sys/boot/arm/at91/boot0spi/main.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/boot2/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,23 @@
+# $MidnightBSD$
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../libat91 ${.CURDIR}/../bootspi
+
+P=boot2
+FILES=${P}
+SRCS=arm_init.S boot2.c ${BOOT_FLAVOR:L}_board.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/../linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+.if ${BOOT_FLAVOR} == "kb920x"
+CFLAGS+=-DBOOT_IIC
+.endif
+CFLAGS+= \
+ -I${.CURDIR}/../bootspi \
+ -I${.CURDIR}/../../../common \
+ -I${.CURDIR}/../../../.. \
+ -D_KERNEL \
+ -DUFS1_ONLY
Property changes on: trunk/sys/boot/arm/at91/boot2/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/board.h
===================================================================
--- trunk/sys/boot/arm/at91/boot2/board.h (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/board.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,30 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+void Update(void);
+void board_init(void);
+int drvread(void *, unsigned, unsigned);
Property changes on: trunk/sys/boot/arm/at91/boot2/board.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/boot2.c
===================================================================
--- trunk/sys/boot/arm/at91/boot2/boot2.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/boot2.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,396 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 John Hay
+ * Copyright (c) 2006 Warner Losh
+ * Copyright (c) 1998 Robert Nordier
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/disklabel.h>
+#include <sys/diskmbr.h>
+#include <sys/dirent.h>
+#include <sys/reboot.h>
+
+#include <machine/elf.h>
+
+#include <stdarg.h>
+
+#include "lib.h"
+#include "board.h"
+
+#define RBX_ASKNAME 0x0 /* -a */
+#define RBX_SINGLE 0x1 /* -s */
+/* 0x2 is reserved for log2(RB_NOSYNC). */
+/* 0x3 is reserved for log2(RB_HALT). */
+/* 0x4 is reserved for log2(RB_INITNAME). */
+#define RBX_DFLTROOT 0x5 /* -r */
+/* #define RBX_KDB 0x6 -d */
+/* 0x7 is reserved for log2(RB_RDONLY). */
+/* 0x8 is reserved for log2(RB_DUMP). */
+/* 0x9 is reserved for log2(RB_MINIROOT). */
+#define RBX_CONFIG 0xa /* -c */
+#define RBX_VERBOSE 0xb /* -v */
+/* #define RBX_SERIAL 0xc -h */
+/* #define RBX_CDROM 0xd -C */
+/* 0xe is reserved for log2(RB_POWEROFF). */
+#define RBX_GDB 0xf /* -g */
+/* #define RBX_MUTE 0x10 -m */
+/* 0x11 is reserved for log2(RB_SELFTEST). */
+/* 0x12 is reserved for boot programs. */
+/* 0x13 is reserved for boot programs. */
+/* #define RBX_PAUSE 0x14 -p */
+/* #define RBX_QUIET 0x15 -q */
+#define RBX_NOINTR 0x1c /* -n */
+/* 0x1d is reserved for log2(RB_MULTIPLE) and is just misnamed here. */
+/* #define RBX_DUAL 0x1d -D */
+/* 0x1f is reserved for log2(RB_BOOTINFO). */
+
+/* pass: -a, -s, -r, -v, -g */
+#define RBX_MASK (OPT_SET(RBX_ASKNAME) | OPT_SET(RBX_SINGLE) | \
+ OPT_SET(RBX_DFLTROOT) | \
+ OPT_SET(RBX_VERBOSE) | \
+ OPT_SET(RBX_GDB))
+
+#define PATH_DOTCONFIG "/boot.config"
+#define PATH_CONFIG "/boot/config"
+//#define PATH_KERNEL "/boot/kernel/kernel"
+#define PATH_KERNEL "/boot/kernel/kernel.gz.tramp"
+
+extern uint32_t _end;
+
+#define NOPT 6
+
+#define OPT_SET(opt) (1 << (opt))
+#define OPT_CHECK(opt) ((opts) & OPT_SET(opt))
+
+static const char optstr[NOPT] = "agnrsv";
+static const unsigned char flags[NOPT] = {
+ RBX_ASKNAME,
+ RBX_GDB,
+ RBX_NOINTR,
+ RBX_DFLTROOT,
+ RBX_SINGLE,
+ RBX_VERBOSE
+};
+
+unsigned dsk_start;
+static char cmd[512];
+static char kname[1024];
+static uint32_t opts;
+static int dsk_meta;
+
+static void load(void);
+static int parse(void);
+static int xfsread(ino_t, void *, size_t);
+static int dskread(void *, unsigned, unsigned);
+#ifdef FIXUP_BOOT_DRV
+static void fixup_boot_drv(caddr_t, int, int, int);
+#endif
+
+#define UFS_SMALL_CGBASE
+#include "ufsread.c"
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) printf(fmt, __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+static inline int
+xfsread(ino_t inode, void *buf, size_t nbyte)
+{
+ if ((size_t)fsread(inode, buf, nbyte) != nbyte)
+ return -1;
+ return 0;
+}
+
+static inline void
+getstr(int c)
+{
+ char *s;
+
+ s = cmd;
+ if (c == 0)
+ c = getc(10000);
+ for (;;) {
+ switch (c) {
+ case 0:
+ break;
+ case '\177':
+ case '\b':
+ if (s > cmd) {
+ s--;
+ printf("\b \b");
+ }
+ break;
+ case '\n':
+ case '\r':
+ *s = 0;
+ return;
+ default:
+ if (s - cmd < sizeof(cmd) - 1)
+ *s++ = c;
+ xputchar(c);
+ }
+ c = getc(10000);
+ }
+}
+
+int
+main(void)
+{
+ int autoboot, c = 0;
+ ino_t ino;
+
+ dmadat = (void *)(0x20000000 + (16 << 20));
+ board_init();
+
+ autoboot = 1;
+
+ /* Process configuration file */
+ if ((ino = lookup(PATH_CONFIG)) ||
+ (ino = lookup(PATH_DOTCONFIG)))
+ fsread(ino, cmd, sizeof(cmd));
+
+ if (*cmd) {
+ if (parse())
+ autoboot = 0;
+ printf("%s: %s\n", PATH_CONFIG, cmd);
+ /* Do not process this command twice */
+ *cmd = 0;
+ }
+
+ if (*kname == '\0')
+ strcpy(kname, PATH_KERNEL);
+
+ /* Present the user with the boot2 prompt. */
+ for (;;) {
+ printf("\nDefault: %s\nboot: ", kname);
+ if (!autoboot ||
+ (OPT_CHECK(RBX_NOINTR) == 0 && (c = getc(2)) != 0))
+ getstr(c);
+ xputchar('\n');
+ autoboot = 0;
+ c = 0;
+ if (parse())
+ xputchar('\a');
+ else
+ load();
+ }
+}
+
+static void
+load(void)
+{
+ Elf32_Ehdr eh;
+ static Elf32_Phdr ep[2];
+ caddr_t p;
+ ino_t ino;
+ uint32_t addr;
+ int i, j;
+#ifdef FIXUP_BOOT_DRV
+ caddr_t staddr;
+ int klen;
+
+ staddr = (caddr_t)0xffffffff;
+ klen = 0;
+#endif
+ if (!(ino = lookup(kname))) {
+ if (!ls)
+ printf("No %s\n", kname);
+ return;
+ }
+ if (xfsread(ino, &eh, sizeof(eh)))
+ return;
+ if (!IS_ELF(eh)) {
+ printf("Invalid %s\n", "format");
+ return;
+ }
+ fs_off = eh.e_phoff;
+ for (j = i = 0; i < eh.e_phnum && j < 2; i++) {
+ if (xfsread(ino, ep + j, sizeof(ep[0])))
+ return;
+ if (ep[j].p_type == PT_LOAD)
+ j++;
+ }
+ for (i = 0; i < 2; i++) {
+ p = (caddr_t)ep[i].p_paddr;
+ fs_off = ep[i].p_offset;
+#ifdef FIXUP_BOOT_DRV
+ if (staddr == (caddr_t)0xffffffff)
+ staddr = p;
+ klen += ep[i].p_filesz;
+#endif
+ if (xfsread(ino, p, ep[i].p_filesz))
+ return;
+ }
+ addr = eh.e_entry;
+#ifdef FIXUP_BOOT_DRV
+ fixup_boot_drv(staddr, klen, bootslice, bootpart);
+#endif
+ ((void(*)(int))addr)(opts & RBX_MASK);
+}
+
+static int
+parse()
+{
+ char *arg = cmd;
+ char *ep, *p;
+ int c, i;
+
+ while ((c = *arg++)) {
+ if (c == ' ' || c == '\t' || c == '\n')
+ continue;
+ for (p = arg; *p && *p != '\n' && *p != ' ' && *p != '\t'; p++);
+ ep = p;
+ if (*p)
+ *p++ = 0;
+ if (c == '-') {
+ while ((c = *arg++)) {
+ for (i = 0; c != optstr[i]; i++)
+ if (i == NOPT - 1)
+ return -1;
+ opts ^= OPT_SET(flags[i]);
+ }
+ } else {
+ arg--;
+ if ((i = ep - arg)) {
+ if ((size_t)i >= sizeof(kname))
+ return -1;
+ memcpy(kname, arg, i + 1);
+ }
+ }
+ arg = p;
+ }
+ return 0;
+}
+
+static int
+dskread(void *buf, unsigned lba, unsigned nblk)
+{
+ struct dos_partition *dp;
+ struct disklabel *d;
+ char *sec;
+ int i;
+
+ if (!dsk_meta) {
+ sec = dmadat->secbuf;
+ dsk_start = 0;
+ if (drvread(sec, DOSBBSECTOR, 1))
+ return -1;
+ dp = (void *)(sec + DOSPARTOFF);
+ for (i = 0; i < NDOSPART; i++) {
+ if (dp[i].dp_typ == DOSPTYP_386BSD)
+ break;
+ }
+ if (i == NDOSPART)
+ return -1;
+ /*
+ * Although dp_start is aligned within the disk
+ * partition structure, DOSPARTOFF is 446, which is
+ * only word (2) aligned, not longword (4) aligned.
+ * Cope by using memcpy to fetch the start of this
+ * partition.
+ */
+ memcpy(&dsk_start, &dp[1].dp_start, 4);
+ if (drvread(sec, dsk_start + LABELSECTOR, 1))
+ return -1;
+ d = (void *)(sec + LABELOFFSET);
+ if (d->d_magic != DISKMAGIC || d->d_magic2 != DISKMAGIC) {
+ printf("Invalid %s\n", "label");
+ return -1;
+ }
+ if (!d->d_partitions[0].p_size) {
+ printf("Invalid %s\n", "partition");
+ return -1;
+ }
+ dsk_start += d->d_partitions[0].p_offset;
+ dsk_start -= d->d_partitions[RAW_PART].p_offset;
+ dsk_meta++;
+ }
+ return drvread(buf, dsk_start + lba, nblk);
+}
+
+#ifdef FIXUP_BOOT_DRV
+/*
+ * fixup_boot_drv() will try to find the ROOTDEVNAME spec in the kernel
+ * and change it to what was specified on the comandline or /boot.conf
+ * file or to what was encountered on the disk. It will try to handle 3
+ * different disk layouts, raw (dangerously dedicated), slice only and
+ * slice + partition. It will look for the following strings in the
+ * kernel, but if it is one of the first three, the string in the kernel
+ * must use the correct form to match the actual disk layout:
+ * - ufs:ad0a
+ * - ufs:ad0s1
+ * - ufs:ad0s1a
+ * - ufs:ROOTDEVNAME
+ * In the case of the first three strings, only the "a" at the end and
+ * the "1" after the "s" will be modified, if they exist. The string
+ * length will not be changed. In the case of the last string, the
+ * whole string will be built up and nul, '\0' terminated.
+ */
+static void
+fixup_boot_drv(caddr_t addr, int klen, int bs, int bp)
+{
+ const u_int8_t op[] = "ufs:ROOTDEVNAME";
+ const u_int8_t op2[] = "ufs:ad0";
+ u_int8_t *p, *ps;
+
+ DPRINTF("fixup_boot_drv: 0x%x, %d, slice %d, partition %d\n",
+ (int)addr, klen, bs, bp);
+ if (bs > 4)
+ return;
+ if (bp > 7)
+ return;
+ ps = memmem(addr, klen, op, sizeof(op));
+ if (ps != NULL) {
+ p = ps + 4; /* past ufs: */
+ DPRINTF("Found it at 0x%x\n", (int)ps);
+ p[0] = 'a'; p[1] = 'd'; p[2] = '0'; /* ad0 */
+ p += 3;
+ if (bs > 0) {
+ /* append slice */
+ *p++ = 's';
+ *p++ = bs + '0';
+ }
+ if (disk_layout != DL_SLICE) {
+ /* append partition */
+ *p++ = bp + 'a';
+ }
+ *p = '\0';
+ } else {
+ ps = memmem(addr, klen, op2, sizeof(op2) - 1);
+ if (ps != NULL) {
+ p = ps + sizeof(op2) - 1;
+ DPRINTF("Found it at 0x%x\n", (int)ps);
+ if (*p == 's') {
+ /* fix slice */
+ p++;
+ *p++ = bs + '0';
+ }
+ if (*p == 'a')
+ *p = bp + 'a';
+ }
+ }
+ if (ps == NULL) {
+ printf("Could not locate \"%s\" to fix kernel boot device, "
+ "check ROOTDEVNAME is set\n", op);
+ return;
+ }
+ DPRINTF("Changed boot device to %s\n", ps);
+}
+#endif
Property changes on: trunk/sys/boot/arm/at91/boot2/boot2.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/bwct_board.c
===================================================================
--- trunk/sys/boot/arm/at91/boot2/bwct_board.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/bwct_board.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,126 @@
+/* $MidnightBSD$ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+
+#include "at91rm9200_lowlevel.h"
+#include "at91rm9200.h"
+#include "emac.h"
+#include "lib.h"
+#include "ee.h"
+#include "board.h"
+#include "sd-card.h"
+
+unsigned char mac[6] = { 0x00, 0x0e, 0x42, 0x02, 0x00, 0x28 };
+
+static void USART0_Init();
+static void USART1_Init();
+static void USART2_Init();
+static void USART3_Init();
+static void DS1672_Init();
+
+static void
+DS1672_Init() {
+ char buf[] = {0x00, 0xa9};
+
+ EEWrite(0xd0, buf, sizeof(buf));
+}
+
+static void
+USART0_Init() {
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ // setup GPIO
+ pPio->PIO_ASR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
+ pPio->PIO_PDR = AT91C_PA17_TXD0 | AT91C_PA18_RXD0;
+
+ // enable power
+ pPMC->PMC_PCER = 1u << AT91C_ID_US0;
+}
+
+static void
+USART1_Init() {
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ // setup GPIO
+ pPio->PIO_ASR = AT91C_PB20_TXD1 | AT91C_PB21_RXD1;
+ pPio->PIO_PDR = AT91C_PB20_TXD1 | AT91C_PB21_RXD1;
+
+ // enable power
+ pPMC->PMC_PCER = 1u << AT91C_ID_US1;
+}
+
+static void
+USART2_Init() {
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ // setup GPIO
+ pPio->PIO_ASR = AT91C_PA23_TXD2 | AT91C_PA22_RXD2;
+ pPio->PIO_PDR = AT91C_PA23_TXD2 | AT91C_PA22_RXD2;
+
+ // enable power
+ pPMC->PMC_PCER = 1u << AT91C_ID_US2;
+}
+
+static void
+USART3_Init() {
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ // setup GPIO
+ pPio->PIO_BSR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
+ pPio->PIO_PDR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3;
+
+ // enable power
+ pPMC->PMC_PCER = 1u << AT91C_ID_US3;
+}
+
+void
+board_init(void)
+{
+
+ printf("\n\n");
+ printf("BWCT FSB-A920-1\n");
+ printf("http://www.bwct.de\n");
+ printf("\n");
+#if defined(SDRAM_128M)
+ printf("AT92RM9200 180MHz 128MB\n");
+#else
+ printf("AT92RM9200 180MHz 64MB\n");
+#endif
+ printf("Initialising USART0\n");
+ USART0_Init();
+ printf("Initialising USART1\n");
+ USART1_Init();
+ printf("Initialising USART2\n");
+ USART2_Init();
+ printf("Initialising USART3\n");
+ USART3_Init();
+ printf("Initialising TWI\n");
+ EEInit();
+ printf("Initialising DS1672\n");
+ DS1672_Init();
+ printf("Initialising Ethernet\n");
+ printf("MAC %x:%x:%x:%x:%x:%x\n", mac[0],
+ mac[1], mac[2], mac[3], mac[4], mac[5]);
+ EMAC_Init();
+ EMAC_SetMACAddress(mac);
+ printf("Initialising SD-card\n");
+ sdcard_init();
+}
+
+#include "../bootspi/ee.c"
+
+int
+drvread(void *buf, unsigned lba, unsigned nblk)
+{
+ return (MCI_read((char *)buf, lba << 9, nblk << 9));
+}
Property changes on: trunk/sys/boot/arm/at91/boot2/bwct_board.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/centipad_board.c
===================================================================
--- trunk/sys/boot/arm/at91/boot2/centipad_board.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/centipad_board.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,69 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+
+#include "emac.h"
+#include "lib.h"
+#include "board.h"
+#include "sd-card.h"
+
+unsigned char mac[6] = { 0x42, 0x53, 0x44, 0, 1, 1 };
+
+static void
+MacFromEE()
+{
+#if 0
+ uint32_t sig;
+ sig = 0;
+ ReadEEPROM(12 * 1024, (uint8_t *)&sig, sizeof(sig));
+ if (sig != 0x92021054)
+ return;
+ ReadEEPROM(12 * 1024 + 4, mac, 6);
+#endif
+ printf("MAC %x:%x:%x:%x:%x:%x\n", mac[0],
+ mac[1], mac[2], mac[3], mac[4], mac[5]);
+}
+
+void
+board_init(void)
+{
+ InitEEPROM();
+ MacFromEE();
+ EMAC_Init();
+ EMAC_SetMACAddress(mac);
+ while (sdcard_init() == 0)
+ printf("Looking for SD card\n");
+}
+
+int
+drvread(void *buf, unsigned lba, unsigned nblk)
+{
+ return (MCI_read((char *)buf, lba << 9, nblk << 9));
+}
Property changes on: trunk/sys/boot/arm/at91/boot2/centipad_board.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/boot2/kb920x_board.c
===================================================================
--- trunk/sys/boot/arm/at91/boot2/kb920x_board.c (rev 0)
+++ trunk/sys/boot/arm/at91/boot2/kb920x_board.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,67 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+
+#include "emac.h"
+#include "lib.h"
+#include "board.h"
+#include "sd-card.h"
+
+unsigned char mac[6] = { 0x42, 0x53, 0x44, 0, 0, 1 };
+
+static void
+MacFromEE()
+{
+ uint32_t sig;
+ sig = 0;
+ ReadEEPROM(12 * 1024, (uint8_t *)&sig, sizeof(sig));
+ if (sig != 0x92021054)
+ return;
+ ReadEEPROM(12 * 1024 + 4, mac, 6);
+ printf("MAC %x:%x:%x:%x:%x:%x\n", mac[0],
+ mac[1], mac[2], mac[3], mac[4], mac[5]);
+}
+
+void
+board_init(void)
+{
+ InitEEPROM();
+ MacFromEE();
+ EMAC_Init();
+ EMAC_SetMACAddress(mac);
+ while (sdcard_init() == 0)
+ printf("Looking for SD card\n");
+}
+
+int
+drvread(void *buf, unsigned lba, unsigned nblk)
+{
+ return (MCI_read((char *)buf, lba << 9, nblk << 9));
+}
Property changes on: trunk/sys/boot/arm/at91/boot2/kb920x_board.c
___________________________________________________________________
Added: svn:eol-style
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+native
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,14 @@
+# $MidnightBSD$
+
+.PATH: ${.CURDIR}/../libat91
+
+P=bootiic
+FILES=${P}
+SRCS=arm_init.S main.c loader_prompt.c env_vars.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/../linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+CFLAGS += -DBOOT_IIC -DBOOT_COMMANDS
Property changes on: trunk/sys/boot/arm/at91/bootiic/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/README
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/README (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/README 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,35 @@
+$MidnightBSD$
+
+This image is intended to be programmed into boot EEPROM. The image is nearly
+0x4000 so it will not fit in KB9200's 0x2000. It is intended for KB9201 or
+later. Alternatively, the KB9200 can be upgraded with larger EEPROM.
+It performs basic functions prior to executing an image at a
+specified address. The pre-boot functions can be modified and saved back into
+EEPROM.
+The MAC address is set with 0.0.0.0.0.0 by default. This is an invalid address
+and must be changed to a valid value in order to use the ethernet interface.
+
+Memory usage:
+
+EEPROM = 0x4000
+SDRAM =
+ run stack = 0x21800000
+ variables = 0x21200000
+ ethernet = 0x21000000 (buffers and descriptors)
+
+
+Functions supported:
+
+ c - copy
+ d - display auto command table (in RAM)
+ e - execute image
+ ? - help
+ ip - set local ip
+ m - set mac
+ server_ip - set server ip
+ s - set auto command entry
+ t - create linux boot tag list
+ tftp - download image via tftp
+ w - update auto command table
+ x - download image via xmodem
+
Property changes on: trunk/sys/boot/arm/at91/bootiic/README
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/env_vars.c
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/env_vars.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/env_vars.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,208 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: env_vars.c
+ *
+ * Instantiation of environment variables, structures, and other globals.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "env_vars.h"
+#include "loader_prompt.h"
+#include "lib.h"
+
+/******************************* GLOBALS *************************************/
+char boot_commands[MAX_BOOT_COMMANDS][MAX_INPUT_SIZE];
+
+char env_table[MAX_ENV_SIZE_BYTES];
+
+extern char BootCommandSection;
+
+/************************** PRIVATE FUNCTIONS ********************************/
+
+
+static int currentIndex;
+static int currentOffset;
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int ReadCharFromEnvironment(char *)
+ * This private function reads characters from the enviroment variables
+ * to service the command prompt during auto-boot or just to setup the
+ * default environment. Returns positive value if valid character was
+ * set in the pointer. Returns negative value to signal input stream
+ * terminated. Returns 0 to indicate _wait_ condition.
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+ReadCharFromEnvironment(int timeout)
+{
+ int ch;
+
+ if (currentIndex < MAX_BOOT_COMMANDS) {
+ ch = boot_commands[currentIndex][currentOffset++];
+ if (ch == '\0' || (currentOffset >= MAX_INPUT_SIZE)) {
+ currentOffset = 0;
+ ++currentIndex;
+ ch = '\r';
+ }
+ return (ch);
+ }
+
+ return (-1);
+}
+
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void WriteCommandTable(void)
+ * This global function write the current command table to the non-volatile
+ * memory.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+WriteCommandTable(void)
+{
+ int i, size = MAX_ENV_SIZE_BYTES, copySize;
+ char *cPtr = env_table;
+
+ p_memset(env_table, 0, sizeof(env_table));
+
+ for (i = 0; i < MAX_BOOT_COMMANDS; ++i) {
+
+ copySize = p_strlen(boot_commands[i]);
+ size -= copySize + 1;
+
+ if (size < 0) {
+ continue;
+ }
+ memcpy(cPtr, boot_commands[i], copySize);
+ cPtr += copySize;
+ *cPtr++ = 0;
+ }
+
+ /* We're executing in low RAM so addr in ram == offset in eeprom */
+ WriteEEPROM((unsigned)&BootCommandSection, env_table,
+ sizeof(env_table));
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SetBootCommand(int index, char *command)
+ * This global function replaces the specified index with the string residing
+ * at command. Execute this function with a NULL string to clear the
+ * associated command index.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SetBootCommand(int index, char *command)
+{
+ int i;
+
+ if ((unsigned)index < MAX_BOOT_COMMANDS) {
+
+ p_memset(boot_commands[index], 0, MAX_INPUT_SIZE);
+
+ if (!command)
+ return ;
+
+ for (i = 0; i < MAX_INPUT_SIZE; ++i) {
+ boot_commands[index][i] = command[i];
+ if (!(boot_commands[index][i]))
+ return;
+ }
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void DumpBootCommands(void)
+ * This global function displays the current boot commands.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+DumpBootCommands(void)
+{
+ int i, j;
+
+ for (i = 0; i < MAX_BOOT_COMMANDS; ++i) {
+ printf("0x%x : ", i);
+ for (j = 0; j < MAX_INPUT_SIZE; ++j) {
+ putchar(boot_commands[i][j]);
+ if (!(boot_commands[i][j]))
+ break;
+ }
+ printf("[E]\n\r");
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void LoadBootCommands(void)
+ * This global function loads the existing boot commands from raw format and
+ * coverts it to the standard, command-index format. Notice, the processed
+ * boot command table has much more space allocated than the actual table
+ * stored in non-volatile memory. This is because the processed table
+ * exists in RAM which is larger than the non-volatile space.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+LoadBootCommands(void)
+{
+ int index, j, size;
+ char *cPtr;
+
+ p_memset((char*)boot_commands, 0, sizeof(boot_commands));
+
+ cPtr = &BootCommandSection;
+
+ size = MAX_ENV_SIZE_BYTES;
+
+ for (index = 0; (index < MAX_BOOT_COMMANDS) && size; ++index) {
+ for (j = 0; (j < MAX_INPUT_SIZE) && size; ++j) {
+ size--;
+ boot_commands[index][j] = *cPtr++;
+ if (!(boot_commands[index][j])) {
+ break;
+ }
+ }
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ExecuteEnvironmentFunctions(void)
+ * This global function executes applicable entries in the environment.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+ExecuteEnvironmentFunctions(void)
+{
+ currentIndex = 0;
+ currentOffset = 0;
+
+ DumpBootCommands();
+ Bootloader(ReadCharFromEnvironment);
+}
Property changes on: trunk/sys/boot/arm/at91/bootiic/env_vars.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/env_vars.h
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/env_vars.h (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/env_vars.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,55 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: env_vars.h
+ *
+ * Definition of environment variables, structures, and other globals.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#ifndef _ENV_VARS_H_
+#define _ENV_VARS_H_
+
+/* each environment variable is a string following the standard command */
+/* definition used by the interactive loader in the following format: */
+/* <command> <parm1> <parm2> ... */
+/* all environment variables (or commands) are stored in a string */
+/* format: NULL-terminated. */
+/* this implies that commands can never utilize 0-values: actual 0, not */
+/* the string '0'. this is not an issue as the string '0' is handled */
+/* by the command parse routine. */
+
+/* the following defines the maximum size of the environment for */
+/* including variables. */
+/* this value must match that declared in the low-level file that */
+/* actually reserves the space for the non-volatile environment. */
+#define MAX_ENV_SIZE_BYTES 0x100
+
+#define MAX_BOOT_COMMANDS 10
+
+/* C-style reference section */
+#ifndef __ASSEMBLY__
+
+extern void WriteCommandTable(void);
+extern void SetBootCommand(int index, char *command);
+extern void DumpBootCommands(void);
+extern void LoadBootCommands(void);
+extern void ExecuteEnvironmentFunctions(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ENV_VARS_H_ */
Property changes on: trunk/sys/boot/arm/at91/bootiic/env_vars.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/loader_prompt.c
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/loader_prompt.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/loader_prompt.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,388 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: loader_prompt.c
+ *
+ * Instantiation of the interactive loader functions.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin massive changes for tftp, strings, and more
+ * 05JUL2005 kb_admin save tag address, and set registers on boot
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "at91rm9200_lowlevel.h"
+#ifdef SUPPORT_TAG_LIST
+#include "tag_list.h"
+#endif
+#include "emac.h"
+#include "loader_prompt.h"
+#include "env_vars.h"
+#include "lib.h"
+
+
+/******************************* GLOBALS *************************************/
+
+
+/*********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+static char inputBuffer[MAX_INPUT_SIZE];
+static int buffCount;
+
+// argv pointer are either NULL or point to locations in inputBuffer
+static char *argv[MAX_COMMAND_PARAMS];
+
+static const char *backspaceString = "\010 \010";
+
+static const command_entry_t CommandTable[] = {
+ {COMMAND_COPY, "c"},
+ {COMMAND_DUMP, "d"},
+ {COMMAND_EXEC, "e"},
+ {COMMAND_HELP, "?"},
+ {COMMAND_LOCAL_IP, "ip"},
+ {COMMAND_MAC, "m"},
+ {COMMAND_SERVER_IP, "server_ip"},
+ {COMMAND_SET, "s"},
+#ifdef SUPPORT_TAG_LIST
+ {COMMAND_TAG, "t"},
+#endif
+ {COMMAND_TFTP, "tftp"},
+ {COMMAND_WRITE, "w"},
+ {COMMAND_XMODEM, "x"},
+ {COMMAND_FINAL_FLAG, 0}
+};
+
+static unsigned tagAddress;
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned BuildIP(void)
+ * This private function packs the test IP info to an unsigned value.
+ * .KB_C_FN_DEFINITION_END
+ */
+static unsigned
+BuildIP(void)
+{
+ return ((p_ASCIIToDec(argv[1]) << 24) |
+ (p_ASCIIToDec(argv[2]) << 16) |
+ (p_ASCIIToDec(argv[3]) << 8) |
+ p_ASCIIToDec(argv[4]));
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int StringToCommand(char *cPtr)
+ * This private function converts a command string to a command code.
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+StringToCommand(char *cPtr)
+{
+ int i;
+
+ for (i = 0; CommandTable[i].command != COMMAND_FINAL_FLAG; ++i)
+ if (!strcmp(CommandTable[i].c_string, cPtr))
+ return (CommandTable[i].command);
+
+ return (COMMAND_INVALID);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void RestoreSpace(int)
+ * This private function restores NULL characters to spaces in order to
+ * process the remaining args as a string. The number passed is the argc
+ * of the first entry to begin restoring space in the inputBuffer.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+RestoreSpace(int startArgc)
+{
+ char *cPtr;
+
+ for (startArgc++; startArgc < MAX_COMMAND_PARAMS; startArgc++) {
+ if ((cPtr = argv[startArgc]))
+ *(cPtr - 1) = ' ';
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int BreakCommand(char *)
+ * This private function splits the buffer into separate strings as pointed
+ * by argv and returns the number of parameters (< 0 on failure).
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+BreakCommand(char *buffer)
+{
+ int pCount, cCount, state;
+
+ state = pCount = 0;
+ p_memset((char*)argv, 0, sizeof(argv));
+
+ for (cCount = 0; cCount < MAX_INPUT_SIZE; ++cCount) {
+
+ if (!state) {
+ /* look for next command */
+ if (!p_IsWhiteSpace(buffer[cCount])) {
+ argv[pCount++] = &buffer[cCount];
+ state = 1;
+ } else {
+ buffer[cCount] = 0;
+ }
+ } else {
+ /* in command, find next white space */
+ if (p_IsWhiteSpace(buffer[cCount])) {
+ buffer[cCount] = 0;
+ state = 0;
+ }
+ }
+
+ if (pCount >= MAX_COMMAND_PARAMS) {
+ return (-1);
+ }
+ }
+
+ return (pCount);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ParseCommand(char *)
+ * This private function executes matching functions.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+ParseCommand(char *buffer)
+{
+ int argc, i;
+
+ if ((argc = BreakCommand(buffer)) < 1)
+ return;
+
+ switch (StringToCommand(argv[0])) {
+ case COMMAND_COPY:
+ {
+ // "c <to> <from> <size in bytes>"
+ // copy memory
+ char *to, *from;
+ unsigned size;
+
+ if (argc > 3) {
+ to = (char *)p_ASCIIToHex(argv[1]);
+ from = (char *)p_ASCIIToHex(argv[2]);
+ size = p_ASCIIToHex(argv[3]);
+ memcpy(to, from, size);
+ }
+ break;
+ }
+
+ case COMMAND_DUMP:
+ // display boot commands
+ DumpBootCommands();
+ break;
+
+ case COMMAND_EXEC:
+ {
+ // "e <address>"
+ // execute at address
+ void (*execAddr)(unsigned, unsigned, unsigned);
+
+ if (argc > 1) {
+ /* in future, include machtypes (MACH_KB9200 = 612) */
+ execAddr = (void (*)(unsigned, unsigned, unsigned))
+ p_ASCIIToHex(argv[1]);
+ (*execAddr)(0, 612, tagAddress);
+ }
+ break;
+ }
+
+ case COMMAND_TFTP:
+ {
+ // "tftp <local_dest_addr filename>"
+ // tftp download
+ unsigned address = 0;
+
+ if (argc > 2)
+ address = p_ASCIIToHex(argv[1]);
+ TFTP_Download(address, argv[2]);
+ break;
+ }
+
+ case COMMAND_SERVER_IP:
+ // "server_ip <server IP 192 200 1 20>"
+ // set download server address
+ if (argc > 4)
+ SetServerIPAddress(BuildIP());
+ break;
+
+ case COMMAND_HELP:
+ // dump command info
+ printf("Commands:\n"
+ "\tc\n"
+ "\td\n"
+ "\te\n"
+ "\tip\n"
+ "\tserver_ip\n"
+ "\tm\n"
+ "\ttftp\n"
+ "\ts\n"
+#ifdef SUPPORT_TAG_LIST
+ "\tt\n"
+#endif
+ "\tw\n"
+ "\tx\n");
+ break;
+
+ case COMMAND_LOCAL_IP:
+ // "local_ip <local IP 192 200 1 21>
+ // set ip of this module
+ if (argc > 4)
+ SetLocalIPAddress(BuildIP());
+ break;
+
+ case COMMAND_MAC:
+ {
+ // "m <mac address 12 34 56 78 9a bc>
+ // set mac address using 6 byte values
+ unsigned char mac[6];
+
+ if (argc > 6) {
+ for (i = 0; i < 6; i++)
+ mac[i] = p_ASCIIToHex(argv[i + 1]);
+ EMAC_SetMACAddress(mac);
+ }
+ break;
+ }
+
+ case COMMAND_SET:
+ {
+ // s <index> <new boot command>
+ // set the boot command at index (0-based)
+ unsigned index;
+
+ if (argc > 1) {
+ RestoreSpace(2);
+ index = p_ASCIIToHex(argv[1]);
+ SetBootCommand(index, argv[2]);
+ }
+ break;
+ }
+
+#ifdef SUPPORT_TAG_LIST
+ case COMMAND_TAG:
+ // t <address> <boot command line>
+ // create tag-list for linux boot
+ if (argc > 2) {
+ RestoreSpace(2);
+ tagAddress = p_ASCIIToHex(argv[1]);
+ InitTagList(argv[2], (void*)tagAddress);
+ }
+ break;
+#endif
+
+ case COMMAND_WRITE:
+ // write the command table to non-volatile
+ WriteCommandTable();
+ break;
+
+ case COMMAND_XMODEM:
+ {
+ // "x <address>"
+ // download X-modem record at address
+ if (argc > 1)
+ xmodem_rx((char *)p_ASCIIToHex(argv[1]));
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ printf("\n");
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ServicePrompt(char)
+ * This private function process each character checking for valid commands.
+ * This function is only executed if the character is considered valid.
+ * Each command is terminated with NULL (0) or ''.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+ServicePrompt(char p_char)
+{
+ if (p_char == '\r')
+ p_char = 0;
+
+ if (p_char == '\010') {
+ if (buffCount) {
+ /* handle backspace BS */
+ inputBuffer[--buffCount] = 0;
+ printf(backspaceString);
+ }
+ return;
+ }
+ if (buffCount < MAX_INPUT_SIZE - 1) {
+ inputBuffer[buffCount++] = p_char;
+ putchar(p_char);
+ }
+ if (!p_char) {
+ printf("\n");
+ ParseCommand(inputBuffer);
+ p_memset(inputBuffer, 0, MAX_INPUT_SIZE);
+ buffCount = 0;
+ printf("\n>");
+ }
+}
+
+
+/* ************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void Bootloader(void *inputFunction)
+ * This global function is the entry point for the bootloader. If the
+ * inputFunction pointer is NULL, the loader input will be serviced from
+ * the uart. Otherwise, inputFunction is called to get characters which
+ * the loader will parse.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+Bootloader(int(*inputFunction)(int))
+{
+ int ch = 0;
+
+ p_memset((void*)inputBuffer, 0, sizeof(inputBuffer));
+
+ buffCount = 0;
+ if (!inputFunction) {
+ inputFunction = getc;
+ }
+
+ printf("\n>");
+
+ while (1)
+ if ((ch = ((*inputFunction)(0))) > 0)
+ ServicePrompt(ch);
+}
Property changes on: trunk/sys/boot/arm/at91/bootiic/loader_prompt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/loader_prompt.h
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/loader_prompt.h (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/loader_prompt.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,56 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: loader_prompt.h
+ *
+ * Definition of the interactive loader functions.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#ifndef _LOADER_PROMPT_H_
+#define _LOADER_PROMPT_H_
+
+#define MAX_INPUT_SIZE 256
+#define MAX_COMMAND_PARAMS 10
+
+enum {
+ COMMAND_INVALID = 0,
+ COMMAND_COPY,
+ COMMAND_DUMP,
+ COMMAND_EXEC,
+ COMMAND_HELP,
+ COMMAND_LOCAL_IP,
+ COMMAND_MAC,
+ COMMAND_SERVER_IP,
+ COMMAND_SET,
+ COMMAND_TAG,
+ COMMAND_TFTP,
+ COMMAND_WRITE,
+ COMMAND_XMODEM,
+ COMMAND_FINAL_FLAG
+} e_cmd_t;
+
+
+typedef struct {
+ int command;
+ const char *c_string;
+} command_entry_t;
+
+void EnterInteractiveBootloader(int(*inputFunction)(int));
+void Bootloader(int(*inputFunction)(int));
+
+#endif /* _LOADER_PROMPT_H_ */
Property changes on: trunk/sys/boot/arm/at91/bootiic/loader_prompt.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootiic/main.c
===================================================================
--- trunk/sys/boot/arm/at91/bootiic/main.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootiic/main.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,54 @@
+/* $MidnightBSD$ */
+/*******************************************************************************
+ *
+ * Filename: main.c
+ *
+ * Basic entry points for top-level functions
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin cosmetic changes
+ * 29APR2005 kb_admin modified boot delay
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ ******************************************************************************/
+
+#include "env_vars.h"
+#include "at91rm9200_lowlevel.h"
+#include "loader_prompt.h"
+#include "emac.h"
+#include "lib.h"
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int main(void)
+ * This global function waits at least one second, but not more than two
+ * seconds, for input from the serial port. If no response is recognized,
+ * it acts according to the parameters specified by the environment. For
+ * example, the function might boot an operating system. Do not return
+ * from this function.
+ * .KB_C_FN_DEFINITION_END
+ */
+int
+main(void)
+{
+ InitEEPROM();
+ EMAC_Init();
+ LoadBootCommands();
+ printf("\n\rKB9202(www.kwikbyte.com)\n\rAuto boot..\n\r");
+ if (getc(1) == -1)
+ ExecuteEnvironmentFunctions();
+ Bootloader(0);
+
+ return (1);
+}
Property changes on: trunk/sys/boot/arm/at91/bootiic/main.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,18 @@
+# $MidnightBSD$
+# $FreeBSD$
+
+.PATH: ${.CURDIR}/../libat91
+
+P=bootspi
+FILES=${P}
+SRCS=arm_init.S main.c loader_prompt.c env_vars.c ee.c
+NO_MAN=
+LDFLAGS=-e 0 -T ${.CURDIR}/../linker.cfg
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+
+.include <bsd.prog.mk>
+
+.if ${MK_FPGA} == "yes"
+CFLAGS += -DTSC_FPGA
+.endif
+CFLAGS += -DBOOT_COMMANDS
Property changes on: trunk/sys/boot/arm/at91/bootspi/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/README
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/README (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/README 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,34 @@
+$MidnightBSD$
+
+This image is intended to be programmed into boot EEPROM. The image is nearly
+0x4000 so it will not fit in KB9200's 0x2000. It is intended for KB9201 or
+later. Alternatively, the KB9200 can be upgraded with larger EEPROM.
+It performs basic functions prior to executing an image at a
+specified address. The pre-boot functions can be modified and saved back into
+EEPROM.
+The MAC address is set with 0.0.0.0.0.0 by default. This is an invalid address
+and must be changed to a valid value in order to use the ethernet interface.
+
+Memory usage:
+
+EEPROM = 0x4000
+SDRAM =
+ run stack = 0x21800000
+ variables = 0x21200000
+ ethernet = 0x21000000 (buffers and descriptors)
+
+
+Functions supported:
+
+ c - copy
+ d - display auto command table (in RAM)
+ e - execute image
+ ? - help
+ ip - set local ip
+ m - set mac
+ server_ip - set server ip
+ s - set auto command entry
+ t - create linux boot tag list
+ tftp - download image via tftp
+ w - update auto command table
+ x - download image via xmodem
Property changes on: trunk/sys/boot/arm/at91/bootspi/README
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/ee.c
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/ee.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/ee.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,161 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: eeprom.c
+ *
+ * Instantiation of eeprom routines
+ *
+ * Revision information:
+ *
+ * 28AUG2004 kb_admin initial creation - adapted from Atmel sources
+ * 12JAN2005 kb_admin fixed clock generation, write polling, init
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "at91rm9200_lowlevel.h"
+#include "at91rm9200.h"
+#include "lib.h"
+#include "ee.h"
+
+/******************************* GLOBALS *************************************/
+
+
+/*********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+
+/* Use a macro to calculate the TWI clock generator value to save code space. */
+#define AT91C_TWSI_CLOCK 100000
+#define TWSI_EEPROM_ADDRESS 0x40
+
+#define TWI_CLK_BASE_DIV ((AT91C_MASTER_CLOCK/(4*AT91C_TWSI_CLOCK)) - 2)
+#define SET_TWI_CLOCK ((0x00010000) | (TWI_CLK_BASE_DIV) | (TWI_CLK_BASE_DIV << 8))
+
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void InitEEPROM(void)
+ * This global function initializes the EEPROM interface (TWI). Intended
+ * to be called a single time.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+EEInit(void)
+{
+
+ AT91PS_TWI twiPtr = (AT91PS_TWI)AT91C_BASE_TWI;
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ pPio->PIO_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ pPio->PIO_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+
+ pPio->PIO_MDDR = ~AT91C_PA25_TWD;
+ pPio->PIO_MDER = AT91C_PA25_TWD;
+
+ pPMC->PMC_PCER = 1u << AT91C_ID_TWI;
+
+ twiPtr->TWI_IDR = 0xffffffffu;
+ twiPtr->TWI_CR = AT91C_TWI_SWRST;
+ twiPtr->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+
+ twiPtr->TWI_CWGR = SET_TWI_CLOCK;
+}
+
+static inline unsigned
+iicaddr(unsigned ee_off)
+{
+ return (TWSI_EEPROM_ADDRESS | ((ee_off >> 8) & 0x7));
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ReadEEPROM(unsigned ee_addr, char *data_addr, unsigned size)
+ * This global function reads data from the eeprom at ee_addr storing data
+ * to data_addr for size bytes. Assume the TWI has been initialized.
+ * This function does not utilize the page read mode to simplify the code.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+EERead(unsigned ee_off, char *data_addr, unsigned size)
+{
+ const AT91PS_TWI twiPtr = AT91C_BASE_TWI;
+ unsigned int status;
+
+ if ((ee_off & ~0xff) != ((ee_off + size) & ~0xff)) {
+ printf("Crosses page boundary: 0x%x 0x%x\n", ee_off, size);
+ return;
+ }
+
+ status = twiPtr->TWI_SR;
+ status = twiPtr->TWI_RHR;
+ twiPtr->TWI_MMR = (iicaddr(ee_off) << 16) | AT91C_TWI_IADRSZ_1_BYTE |
+ AT91C_TWI_MREAD;
+ twiPtr->TWI_IADR = ee_off & 0xff;
+ twiPtr->TWI_CR = AT91C_TWI_START;
+ while (size-- > 1) {
+ while (!(twiPtr->TWI_SR & AT91C_TWI_RXRDY))
+ continue;
+ *(data_addr++) = twiPtr->TWI_RHR;
+ }
+ twiPtr->TWI_CR = AT91C_TWI_STOP;
+ status = twiPtr->TWI_SR;
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXCOMP))
+ continue;
+ *data_addr = twiPtr->TWI_RHR;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void WriteEEPROM(unsigned ee_off, char *data_addr, unsigned size)
+ * This global function writes data to the eeprom at ee_off using data
+ * from data_addr for size bytes. Assume the TWI has been initialized.
+ * This function does not utilize the page write mode as the write time is
+ * much greater than the time required to access the device for byte-write
+ * functionality. This allows the function to be much simpler.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+EEWrite(unsigned ee_off, const char *data_addr, unsigned size)
+{
+ const AT91PS_TWI twiPtr = AT91C_BASE_TWI;
+ unsigned status;
+ char test_data;
+
+ while (size--) {
+ // Set the TWI Master Mode Register
+ twiPtr->TWI_MMR = (iicaddr(ee_off) << 16) |
+ AT91C_TWI_IADRSZ_1_BYTE;
+ twiPtr->TWI_IADR = ee_off++;
+ status = twiPtr->TWI_SR;
+
+ // Load one data byte
+ twiPtr->TWI_THR = *(data_addr++);
+ twiPtr->TWI_CR = AT91C_TWI_START;
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXRDY))
+ continue;
+ twiPtr->TWI_CR = AT91C_TWI_STOP;
+ status = twiPtr->TWI_SR;
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXCOMP))
+ continue;
+
+ // wait for write operation to complete, it is done once
+ // we can read it back...
+ EERead(ee_off, &test_data, 1);
+ }
+}
Property changes on: trunk/sys/boot/arm/at91/bootspi/ee.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/ee.h
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/ee.h (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/ee.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,7 @@
+/* $MidnightBSD$ */
+/* $FreeBSD$ */
+
+void EEInit(void);
+void EERead(unsigned ee_off, char *data_addr, unsigned size);
+void EEWrite(unsigned ee_off, const char *data_addr, unsigned size);
+
Property changes on: trunk/sys/boot/arm/at91/bootspi/ee.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/env_vars.c
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/env_vars.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/env_vars.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,131 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: env_vars.c
+ *
+ * Instantiation of environment variables, structures, and other globals.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "env_vars.h"
+#include "loader_prompt.h"
+#include "lib.h"
+
+/******************************* GLOBALS *************************************/
+char boot_commands[MAX_BOOT_COMMANDS][MAX_INPUT_SIZE];
+
+char env_table[MAX_ENV_SIZE_BYTES];
+
+extern char BootCommandSection;
+
+/************************** PRIVATE FUNCTIONS ********************************/
+
+
+static int currentIndex;
+static int currentOffset;
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int ReadCharFromEnvironment(char *)
+ * This private function reads characters from the enviroment variables
+ * to service the command prompt during auto-boot or just to setup the
+ * default environment. Returns positive value if valid character was
+ * set in the pointer. Returns negative value to signal input stream
+ * terminated. Returns 0 to indicate _wait_ condition.
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+ReadCharFromEnvironment(int timeout)
+{
+ int ch;
+
+ if (currentIndex < MAX_BOOT_COMMANDS) {
+ ch = boot_commands[currentIndex][currentOffset++];
+ if (ch == '\0' || (currentOffset >= MAX_INPUT_SIZE)) {
+ currentOffset = 0;
+ ++currentIndex;
+ ch = '\r';
+ }
+ return (ch);
+ }
+
+ return (-1);
+}
+
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void DumpBootCommands(void)
+ * This global function displays the current boot commands.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+DumpBootCommands(void)
+{
+ int i;
+
+ for (i = 0; boot_commands[i][0]; i++)
+ printf("0x%x : %s[E]\n", i, boot_commands[i]);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void LoadBootCommands(void)
+ * This global function loads the existing boot commands from raw format and
+ * coverts it to the standard, command-index format. Notice, the processed
+ * boot command table has much more space allocated than the actual table
+ * stored in non-volatile memory. This is because the processed table
+ * exists in RAM which is larger than the non-volatile space.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+LoadBootCommands(void)
+{
+ int index, j;
+ char *cptr;
+
+ p_memset((char*)boot_commands, 0, sizeof(boot_commands));
+ cptr = &BootCommandSection;
+ for (index = 0; *cptr; index++) {
+ for (j = 0; *cptr; j++)
+ boot_commands[index][j] = *cptr++;
+ cptr++;
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ExecuteEnvironmentFunctions(void)
+ * This global function executes applicable entries in the environment.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+ExecuteEnvironmentFunctions(void)
+{
+ currentIndex = 0;
+ currentOffset = 0;
+
+ DumpBootCommands();
+ printf("Autoboot...\n");
+ Bootloader(ReadCharFromEnvironment);
+}
Property changes on: trunk/sys/boot/arm/at91/bootspi/env_vars.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/env_vars.h
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/env_vars.h (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/env_vars.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,55 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: env_vars.h
+ *
+ * Definition of environment variables, structures, and other globals.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#ifndef _ENV_VARS_H_
+#define _ENV_VARS_H_
+
+/* each environment variable is a string following the standard command */
+/* definition used by the interactive loader in the following format: */
+/* <command> <parm1> <parm2> ... */
+/* all environment variables (or commands) are stored in a string */
+/* format: NULL-terminated. */
+/* this implies that commands can never utilize 0-values: actual 0, not */
+/* the string '0'. this is not an issue as the string '0' is handled */
+/* by the command parse routine. */
+
+/* the following defines the maximum size of the environment for */
+/* including variables. */
+/* this value must match that declared in the low-level file that */
+/* actually reserves the space for the non-volatile environment. */
+#define MAX_ENV_SIZE_BYTES 0x100
+
+#define MAX_BOOT_COMMANDS 10
+
+/* C-style reference section */
+#ifndef __ASSEMBLY__
+
+extern void WriteCommandTable(void);
+extern void SetBootCommand(int index, char *command);
+extern void DumpBootCommands(void);
+extern void LoadBootCommands(void);
+extern void ExecuteEnvironmentFunctions(void);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ENV_VARS_H_ */
Property changes on: trunk/sys/boot/arm/at91/bootspi/env_vars.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/loader_prompt.c
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/loader_prompt.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/loader_prompt.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,364 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: loader_prompt.c
+ *
+ * Instantiation of the interactive loader functions.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin massive changes for tftp, strings, and more
+ * 05JUL2005 kb_admin save tag address, and set registers on boot
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "at91rm9200_lowlevel.h"
+#include "at91rm9200.h"
+#include "emac.h"
+#include "loader_prompt.h"
+#include "env_vars.h"
+#include "lib.h"
+#include "spi_flash.h"
+#include "ee.h"
+
+/******************************* GLOBALS *************************************/
+
+
+/*********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+static char inputBuffer[MAX_INPUT_SIZE];
+static int buffCount;
+
+// argv pointer are either NULL or point to locations in inputBuffer
+static char *argv[MAX_COMMAND_PARAMS];
+
+#define FLASH_OFFSET (0 * FLASH_PAGE_SIZE)
+#define KERNEL_OFFSET (220 * FLASH_PAGE_SIZE)
+#define KERNEL_LEN (6 * 1024 * FLASH_PAGE_SIZE)
+static const char *backspaceString = "\010 \010";
+
+static const command_entry_t CommandTable[] = {
+ {COMMAND_DUMP, "d"},
+ {COMMAND_EXEC, "e"},
+ {COMMAND_LOCAL_IP, "ip"},
+ {COMMAND_MAC, "m"},
+ {COMMAND_SERVER_IP, "server_ip"},
+ {COMMAND_TFTP, "tftp"},
+ {COMMAND_XMODEM, "x"},
+ {COMMAND_RESET, "R"},
+ {COMMAND_LOAD_SPI_KERNEL, "k"},
+ {COMMAND_REPLACE_KERNEL_VIA_XMODEM, "K"},
+ {COMMAND_REPLACE_FLASH_VIA_XMODEM, "I"},
+ {COMMAND_REPLACE_ID_EEPROM, "E"},
+ {COMMAND_FINAL_FLAG, 0}
+};
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned BuildIP(void)
+ * This private function packs the test IP info to an unsigned value.
+ * .KB_C_FN_DEFINITION_END
+ */
+static unsigned
+BuildIP(void)
+{
+ return ((p_ASCIIToDec(argv[1]) << 24) |
+ (p_ASCIIToDec(argv[2]) << 16) |
+ (p_ASCIIToDec(argv[3]) << 8) |
+ p_ASCIIToDec(argv[4]));
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int StringToCommand(char *cPtr)
+ * This private function converts a command string to a command code.
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+StringToCommand(char *cPtr)
+{
+ int i;
+
+ for (i = 0; CommandTable[i].command != COMMAND_FINAL_FLAG; ++i)
+ if (!strcmp(CommandTable[i].c_string, cPtr))
+ return (CommandTable[i].command);
+
+ return (COMMAND_INVALID);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int BreakCommand(char *)
+ * This private function splits the buffer into separate strings as pointed
+ * by argv and returns the number of parameters (< 0 on failure).
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+BreakCommand(char *buffer)
+{
+ int pCount, cCount, state;
+
+ state = pCount = 0;
+ p_memset((char*)argv, 0, sizeof(argv));
+
+ for (cCount = 0; cCount < MAX_INPUT_SIZE; ++cCount) {
+
+ if (!state) {
+ /* look for next command */
+ if (!p_IsWhiteSpace(buffer[cCount])) {
+ argv[pCount++] = &buffer[cCount];
+ state = 1;
+ } else {
+ buffer[cCount] = 0;
+ }
+ } else {
+ /* in command, find next white space */
+ if (p_IsWhiteSpace(buffer[cCount])) {
+ buffer[cCount] = 0;
+ state = 0;
+ }
+ }
+
+ if (pCount >= MAX_COMMAND_PARAMS) {
+ return (-1);
+ }
+ }
+
+ return (pCount);
+}
+
+#if 0
+static void
+UpdateEEProm(int eeaddr)
+{
+ char *addr = (char *)SDRAM_BASE + (1 << 20); /* Load to base + 1MB */
+ int len;
+
+ while ((len = xmodem_rx(addr)) == -1)
+ continue;
+ printf("\nDownloaded %u bytes.\n", len);
+ WriteEEPROM(eeaddr, 0, addr, len);
+}
+#endif
+
+static void
+UpdateFlash(int offset)
+{
+ char *addr = (char *)SDRAM_BASE + (1 << 20); /* Load to base + 1MB */
+ int len, i, off;
+
+ while ((len = xmodem_rx(addr)) == -1)
+ continue;
+ printf("\nDownloaded %u bytes.\n", len);
+ for (i = 0; i < len; i+= FLASH_PAGE_SIZE) {
+ off = i + offset;
+ SPI_WriteFlash(off, addr + i, FLASH_PAGE_SIZE);
+ }
+}
+
+static void
+LoadKernelFromSpi(char *addr)
+{
+ int i, off;
+
+ for (i = 0; i < KERNEL_LEN; i+= FLASH_PAGE_SIZE) {
+ off = i + KERNEL_OFFSET;
+ SPI_ReadFlash(off, addr + i, FLASH_PAGE_SIZE);
+ }
+}
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ParseCommand(char *)
+ * This private function executes matching functions.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+ParseCommand(char *buffer)
+{
+ int argc, i;
+
+ if ((argc = BreakCommand(buffer)) < 1)
+ return;
+
+ switch (StringToCommand(argv[0])) {
+ case COMMAND_DUMP:
+ // display boot commands
+ DumpBootCommands();
+ break;
+
+ case COMMAND_EXEC:
+ {
+ // "e <address>"
+ // execute at address
+ void (*execAddr)(unsigned, unsigned);
+
+ if (argc > 1) {
+ /* in future, include machtypes (MACH_KB9200 = 612) */
+ execAddr = (void (*)(unsigned, unsigned))
+ p_ASCIIToHex(argv[1]);
+ (*execAddr)(0, 612);
+ }
+ break;
+ }
+
+ case COMMAND_TFTP:
+ {
+ // "tftp <local_dest_addr filename>"
+ // tftp download
+ unsigned address = 0;
+
+ if (argc > 2)
+ address = p_ASCIIToHex(argv[1]);
+ TFTP_Download(address, argv[2]);
+ break;
+ }
+
+ case COMMAND_SERVER_IP:
+ // "server_ip <server IP 192 200 1 20>"
+ // set download server address
+ if (argc > 4)
+ SetServerIPAddress(BuildIP());
+ break;
+
+ case COMMAND_LOCAL_IP:
+ // "local_ip <local IP 192 200 1 21>
+ // set ip of this module
+ if (argc > 4)
+ SetLocalIPAddress(BuildIP());
+ break;
+
+ case COMMAND_MAC:
+ {
+ // "m <mac address 12 34 56 78 9a bc>
+ // set mac address using 6 byte values
+ unsigned char mac[6];
+
+ if (argc > 6) {
+ for (i = 0; i < 6; i++)
+ mac[i] = p_ASCIIToHex(argv[i + 1]);
+ EMAC_SetMACAddress(mac);
+ }
+ break;
+ }
+
+ case COMMAND_LOAD_SPI_KERNEL:
+ // "k <address>"
+ if (argc > 1)
+ LoadKernelFromSpi((char *)p_ASCIIToHex(argv[1]));
+ break;
+
+ case COMMAND_XMODEM:
+ // "x <address>"
+ // download X-modem record at address
+ if (argc > 1)
+ xmodem_rx((char *)p_ASCIIToHex(argv[1]));
+ break;
+
+ case COMMAND_RESET:
+ printf("Reset\n");
+ reset();
+ while (1) continue;
+ break;
+
+ case COMMAND_REPLACE_KERNEL_VIA_XMODEM:
+ printf("Updating KERNEL image\n");
+ UpdateFlash(KERNEL_OFFSET);
+ break;
+ case COMMAND_REPLACE_FLASH_VIA_XMODEM:
+ printf("Updating FLASH image\n");
+ UpdateFlash(FLASH_OFFSET);
+ break;
+
+ case COMMAND_REPLACE_ID_EEPROM:
+ {
+ char buf[25];
+ printf("Testing Config EEPROM\n");
+ EEWrite(0, "This is a test", 15);
+ EERead(0, buf, 15);
+ printf("Found '%s'\n", buf);
+ break;
+ }
+ default:
+ break;
+ }
+
+ printf("\n");
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ServicePrompt(char)
+ * This private function process each character checking for valid commands.
+ * This function is only executed if the character is considered valid.
+ * Each command is terminated with NULL (0) or ''.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+ServicePrompt(char p_char)
+{
+ if (p_char == '\r')
+ p_char = 0;
+
+ if (p_char == '\010') {
+ if (buffCount) {
+ /* handle backspace BS */
+ inputBuffer[--buffCount] = 0;
+ printf(backspaceString);
+ }
+ return;
+ }
+ if (buffCount < MAX_INPUT_SIZE - 1) {
+ inputBuffer[buffCount++] = p_char;
+ putchar(p_char);
+ }
+ if (!p_char) {
+ printf("\n");
+ ParseCommand(inputBuffer);
+ p_memset(inputBuffer, 0, MAX_INPUT_SIZE);
+ buffCount = 0;
+ printf("\n>");
+ }
+}
+
+
+/* ************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void Bootloader(void *inputFunction)
+ * This global function is the entry point for the bootloader. If the
+ * inputFunction pointer is NULL, the loader input will be serviced from
+ * the uart. Otherwise, inputFunction is called to get characters which
+ * the loader will parse.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+Bootloader(int(*inputFunction)(int))
+{
+ int ch = 0;
+
+ p_memset((void*)inputBuffer, 0, sizeof(inputBuffer));
+ buffCount = 0;
+
+ printf("\n>");
+
+ while (1)
+ if ((ch = ((*inputFunction)(0))) > 0)
+ ServicePrompt(ch);
+}
Property changes on: trunk/sys/boot/arm/at91/bootspi/loader_prompt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/loader_prompt.h
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/loader_prompt.h (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/loader_prompt.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,63 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: loader_prompt.h
+ *
+ * Definition of the interactive loader functions.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#ifndef _LOADER_PROMPT_H_
+#define _LOADER_PROMPT_H_
+
+#define MAX_INPUT_SIZE 256
+#define MAX_COMMAND_PARAMS 10
+
+enum {
+ COMMAND_INVALID = 0,
+ COMMAND_COPY,
+ COMMAND_DUMP,
+ COMMAND_EXEC,
+ COMMAND_HELP,
+ COMMAND_LOCAL_IP,
+ COMMAND_MAC,
+ COMMAND_SERVER_IP,
+ COMMAND_SET,
+ COMMAND_TAG,
+ COMMAND_TFTP,
+ COMMAND_WRITE,
+ COMMAND_XMODEM,
+ COMMAND_RESET,
+ COMMAND_LOAD_SPI_KERNEL,
+ COMMAND_REPLACE_KERNEL_VIA_XMODEM,
+ COMMAND_REPLACE_FLASH_VIA_XMODEM,
+ COMMAND_REPLACE_FPGA_VIA_XMODEM,
+ COMMAND_REPLACE_ID_EEPROM,
+ COMMAND_FINAL_FLAG
+} e_cmd_t;
+
+
+typedef struct {
+ int command;
+ const char *c_string;
+} command_entry_t;
+
+void EnterInteractiveBootloader(int(*inputFunction)(int));
+void Bootloader(int(*inputFunction)(int));
+void fpga_load(void);
+
+#endif /* _LOADER_PROMPT_H_ */
Property changes on: trunk/sys/boot/arm/at91/bootspi/loader_prompt.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/bootspi/main.c
===================================================================
--- trunk/sys/boot/arm/at91/bootspi/main.c (rev 0)
+++ trunk/sys/boot/arm/at91/bootspi/main.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,64 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provided by kwikbyte without
+ * copyright as follows:
+ *
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ *
+ * $FreeBSD$
+ */
+
+#include "env_vars.h"
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+#include "loader_prompt.h"
+#include "emac.h"
+#include "lib.h"
+#include "spi_flash.h"
+#include "ee.h"
+
+int
+main(void)
+{
+ printf("\nBoot\n");
+ EEInit();
+ SPI_InitFlash();
+#ifdef TSC_FPGA
+ fpga_load();
+#endif
+ EMAC_Init();
+ LoadBootCommands();
+ if (getc(1) == -1) {
+ start_wdog(30);
+ ExecuteEnvironmentFunctions();
+ }
+ Bootloader(getc);
+ return (1);
+}
Property changes on: trunk/sys/boot/arm/at91/bootspi/main.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/Makefile
===================================================================
--- trunk/sys/boot/arm/at91/libat91/Makefile (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,20 @@
+# $MidnightBSD$
+# $FreeBSD$
+
+.include "${.CURDIR}/../Makefile.inc"
+
+LIB= at91
+INTERNALLIB=
+SRCS=at91rm9200_lowlevel.c delay.c eeprom.c emac.c emac_init.c getc.c \
+ putchar.c printf.c reset.c spi_flash.c xmodem.c \
+ sd-card.c strcvt.c strlen.c strcmp.c memcpy.c strcpy.c \
+ memset.c memcmp.c
+SRCS+=ashldi3.c divsi3.S
+NO_MAN=
+
+.if ${MK_TAG_LIST} != "no"
+CFLAGS += -I${.CURDIR}/.. -DSUPPORT_TAG_LIST
+SRCS+=tag_list.c
+.endif
+
+.include <bsd.lib.mk>
Property changes on: trunk/sys/boot/arm/at91/libat91/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/arm_init.S
===================================================================
--- trunk/sys/boot/arm/at91/libat91/arm_init.S (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/arm_init.S 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,129 @@
+/*******************************************************************************
+ *
+ * Filename: arm_init.s
+ *
+ * Initialization for C-environment and basic operation. Adapted from
+ * ATMEL cstartup.s.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin updated for 16KB eeprom
+ * Atmel stack prevents loading full size at once
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $MidnightBSD$
+ ******************************************************************************/
+
+ .equ TWI_EEPROM_SIZE, 0x3000
+ .equ ARM_MODE_USER, 0x10
+ .equ ARM_MODE_FIQ, 0x11
+ .equ ARM_MODE_IRQ, 0x12
+ .equ ARM_MODE_SVC, 0x13
+ .equ ARM_MODE_ABORT, 0x17
+ .equ ARM_MODE_UNDEF, 0x1B
+ .equ ARM_MODE_SYS, 0x1F
+ .equ I_BIT, 0x80
+ .equ F_BIT, 0x40
+ .equ T_BIT, 0x20
+
+/*
+ * Stack definitions
+ *
+ * Start near top of internal RAM.
+ */
+ .equ END_INT_SRAM, 0x4000
+ .equ SVC_STACK_START, (END_INT_SRAM - 0x4)
+ .equ SVC_STACK_USE, 0x21800000
+
+start:
+
+/* vectors - must reside at address 0 */
+/* the format of this table is defined in the datasheet */
+ B InitReset @; reset
+undefvec:
+ B undefvec @; Undefined Instruction
+swivec:
+ B swivec @; Software Interrupt
+pabtvec:
+ B pabtvec @; Prefetch Abort
+dabtvec:
+ B dabtvec @; Data Abort
+rsvdvec:
+#ifdef BOOT_IIC
+ .long (TWI_EEPROM_SIZE >> 9)
+#else
+#ifdef BOOT_BWCT
+ .long ((528 << 17) | (13 << 13) | (12 * 2))
+#else
+ .long ((1056 << 17) | (13 << 13) | (12 * 2))
+#endif
+#endif
+irqvec:
+ ldr pc, [pc,#-0xF20] @; IRQ : read the AIC
+fiqvec:
+ B fiqvec @; FIQ
+
+InitReset:
+
+/* Set stack and init for SVC */
+ ldr r1, = SVC_STACK_START
+ mov sp, r1 @; Init stack SYS
+
+ msr cpsr_c, #(ARM_MODE_SVC | I_BIT | F_BIT)
+ mov sp, r1 @ ; Init stack SYS
+
+/* Perform system initialization */
+
+ .extern _init
+ bl _init
+#ifndef BOOT_BOOT0
+ ldr r1, = SVC_STACK_USE
+ mov sp, r1 @ ; Move the stack to SDRAM
+#endif
+
+/* Start execution at main */
+ .extern main
+_main:
+__main:
+ bl main
+/* main should not return. If it does, spin forever */
+infiniteLoop:
+ b infiniteLoop
+
+#ifdef BOOT_COMMANDS
+/* the following section is used to store boot commands in */
+/* non-volatile memory. */
+
+ .global BootCommandSection
+BootCommandSection:
+#ifdef SUPPORT_LINUX
+ .string "Bootloader for KB9202 Evaluation Board."
+ .string "c 0x20210000 0x10100000 0x80000 "
+ .string "m 0 0 0 0 0 0 "
+ .string "t 0x20000100 console=ttyS0,115200 root=/dev/ram rw initrd=0x20210000,654933"
+ .string "e 0x10000000 "
+ .string " "
+#else
+#if 1
+ .string "m 42 53 44 0 0 1"
+ .string "ip 206 168 13 194"
+ .string "server_ip 206 168 13 207"
+ .string "tftp 0x20000000 kernel.bin"
+ .string "e 0x20000000"
+#else
+ .string "m 42 53 44 0 0 1"
+ .string "k 0x20000000"
+ .string "e 0x20000000"
+#endif
+ .word 0
+#endif
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/arm_init.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/at91rm9200.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/at91rm9200.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/at91rm9200.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,2410 @@
+/* $MidnightBSD$ */
+// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// The software is delivered "AS IS" without warranty or condition of any
+// kind, either express, implied or statutory. This includes without
+// limitation any warranty or condition with respect to merchantability or
+// fitness for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// $FreeBSD$
+//
+// File Name : AT91RM9200.h
+// Object : AT91RM9200 definitions
+// Generated : AT91 SW Application Group 07/04/2003 (11:05:04)
+//
+// CVS Reference : /AT91RM9200.pl/1.16/Fri Feb 07 09:29:50 2003//
+// CVS Reference : /SYS_AT91RM9200.pl/1.2/Fri Jan 17 11:44:36 2003//
+// CVS Reference : /MC_1760A.pl/1.1/Fri Aug 23 13:38:22 2002//
+// CVS Reference : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 08:36:46 2002//
+// CVS Reference : /PMC_2636A.pl/1.1.1.1/Fri Jun 28 08:36:48 2002//
+// CVS Reference : /ST_1763B.pl/1.1/Fri Aug 23 13:41:42 2002//
+// CVS Reference : /RTC_1245D.pl/1.2/Fri Jan 31 11:19:06 2003//
+// CVS Reference : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 08:36:46 2002//
+// CVS Reference : /DBGU_1754A.pl/1.4/Fri Jan 31 11:18:24 2003//
+// CVS Reference : /UDP_1765B.pl/1.3/Fri Aug 02 13:45:38 2002//
+// CVS Reference : /MCI_1764A.pl/1.2/Thu Nov 14 16:48:24 2002//
+// CVS Reference : /US_1739C.pl/1.2/Fri Jul 12 06:49:24 2002//
+// CVS Reference : /SPI_AT91RMxxxx.pl/1.3/Tue Nov 26 09:20:28 2002//
+// CVS Reference : /SSC_1762A.pl/1.2/Fri Nov 08 12:26:38 2002//
+// CVS Reference : /TC_1753B.pl/1.2/Fri Jan 31 11:19:54 2003//
+// CVS Reference : /TWI_1761B.pl/1.4/Fri Feb 07 09:30:06 2003//
+// CVS Reference : /PDC_1734B.pl/1.2/Thu Nov 21 15:38:22 2002//
+// CVS Reference : /UHP_xxxxA.pl/1.1/Mon Jul 22 11:21:58 2002//
+// CVS Reference : /EMAC_1794A.pl/1.4/Fri Jan 17 11:11:54 2003//
+// CVS Reference : /EBI_1759B.pl/1.10/Fri Jan 17 11:44:28 2003//
+// CVS Reference : /SMC_1783A.pl/1.3/Thu Oct 31 13:38:16 2002//
+// CVS Reference : /SDRC_1758B.pl/1.2/Thu Oct 03 12:04:40 2002//
+// CVS Reference : /BFC_1757B.pl/1.3/Thu Oct 31 13:38:00 2002//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91RM9200_H
+#define AT91RM9200_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved2[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved3[7]; //
+ AT91_REG DBGU_C1R; // Chip ID1 Register
+ AT91_REG DBGU_C2R; // Chip ID2 Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved4[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved5[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved6[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved7[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved8[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved9[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved10[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved11[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved12[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[85]; //
+ AT91_REG PIOC_PER; // PIO Enable Register
+ AT91_REG PIOC_PDR; // PIO Disable Register
+ AT91_REG PIOC_PSR; // PIO Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PIOC_OER; // Output Enable Register
+ AT91_REG PIOC_ODR; // Output Disable Registerr
+ AT91_REG PIOC_OSR; // Output Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PIOC_IFER; // Input Filter Enable Register
+ AT91_REG PIOC_IFDR; // Input Filter Disable Register
+ AT91_REG PIOC_IFSR; // Input Filter Status Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PIOC_SODR; // Set Output Data Register
+ AT91_REG PIOC_CODR; // Clear Output Data Register
+ AT91_REG PIOC_ODSR; // Output Data Status Register
+ AT91_REG PIOC_PDSR; // Pin Data Status Register
+ AT91_REG PIOC_IER; // Interrupt Enable Register
+ AT91_REG PIOC_IDR; // Interrupt Disable Register
+ AT91_REG PIOC_IMR; // Interrupt Mask Register
+ AT91_REG PIOC_ISR; // Interrupt Status Register
+ AT91_REG PIOC_MDER; // Multi-driver Enable Register
+ AT91_REG PIOC_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOC_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved23[1]; //
+ AT91_REG PIOC_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOC_PPUER; // Pull-up Enable Register
+ AT91_REG PIOC_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved24[1]; //
+ AT91_REG PIOC_ASR; // Select A Register
+ AT91_REG PIOC_BSR; // Select B Register
+ AT91_REG PIOC_ABSR; // AB Select Status Register
+ AT91_REG Reserved25[9]; //
+ AT91_REG PIOC_OWER; // Output Write Enable Register
+ AT91_REG PIOC_OWDR; // Output Write Disable Register
+ AT91_REG PIOC_OWSR; // Output Write Status Register
+ AT91_REG Reserved26[85]; //
+ AT91_REG PIOD_PER; // PIO Enable Register
+ AT91_REG PIOD_PDR; // PIO Disable Register
+ AT91_REG PIOD_PSR; // PIO Status Register
+ AT91_REG Reserved27[1]; //
+ AT91_REG PIOD_OER; // Output Enable Register
+ AT91_REG PIOD_ODR; // Output Disable Registerr
+ AT91_REG PIOD_OSR; // Output Status Register
+ AT91_REG Reserved28[1]; //
+ AT91_REG PIOD_IFER; // Input Filter Enable Register
+ AT91_REG PIOD_IFDR; // Input Filter Disable Register
+ AT91_REG PIOD_IFSR; // Input Filter Status Register
+ AT91_REG Reserved29[1]; //
+ AT91_REG PIOD_SODR; // Set Output Data Register
+ AT91_REG PIOD_CODR; // Clear Output Data Register
+ AT91_REG PIOD_ODSR; // Output Data Status Register
+ AT91_REG PIOD_PDSR; // Pin Data Status Register
+ AT91_REG PIOD_IER; // Interrupt Enable Register
+ AT91_REG PIOD_IDR; // Interrupt Disable Register
+ AT91_REG PIOD_IMR; // Interrupt Mask Register
+ AT91_REG PIOD_ISR; // Interrupt Status Register
+ AT91_REG PIOD_MDER; // Multi-driver Enable Register
+ AT91_REG PIOD_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOD_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved30[1]; //
+ AT91_REG PIOD_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOD_PPUER; // Pull-up Enable Register
+ AT91_REG PIOD_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved31[1]; //
+ AT91_REG PIOD_ASR; // Select A Register
+ AT91_REG PIOD_BSR; // Select B Register
+ AT91_REG PIOD_ABSR; // AB Select Status Register
+ AT91_REG Reserved32[9]; //
+ AT91_REG PIOD_OWER; // Output Write Enable Register
+ AT91_REG PIOD_OWDR; // Output Write Disable Register
+ AT91_REG PIOD_OWSR; // Output Write Status Register
+ AT91_REG Reserved33[85]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved34[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved35[1]; //
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG CKGR_PLLAR; // PLL A Register
+ AT91_REG CKGR_PLLBR; // PLL B Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved36[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved37[36]; //
+ AT91_REG ST_CR; // Control Register
+ AT91_REG ST_PIMR; // Period Interval Mode Register
+ AT91_REG ST_WDMR; // Watchdog Mode Register
+ AT91_REG ST_RTMR; // Real-time Mode Register
+ AT91_REG ST_SR; // Status Register
+ AT91_REG ST_IER; // Interrupt Enable Register
+ AT91_REG ST_IDR; // Interrupt Disable Register
+ AT91_REG ST_IMR; // Interrupt Mask Register
+ AT91_REG ST_RTAR; // Real-time Alarm Register
+ AT91_REG ST_CRTR; // Current Real-time Register
+ AT91_REG Reserved38[54]; //
+ AT91_REG RTC_CR; // Control Register
+ AT91_REG RTC_MR; // Mode Register
+ AT91_REG RTC_TIMR; // Time Register
+ AT91_REG RTC_CALR; // Calendar Register
+ AT91_REG RTC_TIMALR; // Time Alarm Register
+ AT91_REG RTC_CALALR; // Calendar Alarm Register
+ AT91_REG RTC_SR; // Status Register
+ AT91_REG RTC_SCCR; // Status Clear Command Register
+ AT91_REG RTC_IER; // Interrupt Enable Register
+ AT91_REG RTC_IDR; // Interrupt Disable Register
+ AT91_REG RTC_IMR; // Interrupt Mask Register
+ AT91_REG RTC_VER; // Valid Entry Register
+ AT91_REG Reserved39[52]; //
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved40[1]; //
+ AT91_REG MC_PUIA[16]; // MC Protection Unit Area
+ AT91_REG MC_PUP; // MC Protection Unit Peripherals
+ AT91_REG MC_PUER; // MC Protection Unit Enable Register
+ AT91_REG Reserved41[2]; //
+ AT91_REG EBI_CSA; // Chip Select Assignment Register
+ AT91_REG EBI_CFGR; // Configuration Register
+ AT91_REG Reserved42[2]; //
+ AT91_REG EBI_SMC2_CSR[8]; // SMC2 Chip Select Register
+ AT91_REG EBI_SDRC_MR; // SDRAM Controller Mode Register
+ AT91_REG EBI_SDRC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG EBI_SDRC_CR; // SDRAM Controller Configuration Register
+ AT91_REG EBI_SDRC_SRR; // SDRAM Controller Self Refresh Register
+ AT91_REG EBI_SDRC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG EBI_SDRC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG EBI_SDRC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG EBI_SDRC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG EBI_SDRC_ISR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG Reserved43[3]; //
+ AT91_REG EBI_BFC_MR; // BFC Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+ AT91_REG MC_RCR; // MC Remap Control Register
+ AT91_REG MC_ASR; // MC Abort Status Register
+ AT91_REG MC_AASR; // MC Abort Address Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG MC_PUIA[16]; // MC Protection Unit Area
+ AT91_REG MC_PUP; // MC Protection Unit Peripherals
+ AT91_REG MC_PUER; // MC Protection Unit Enable Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
+#define AT91C_MC_RCB (0x1u << 0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
+#define AT91C_MC_UNDADD (0x1u << 0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD (0x1u << 1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_MPU (0x1u << 2) // (MC) Memory protection Unit Abort Status
+#define AT91C_MC_ABTSZ (0x3u << 8) // (MC) Abort Size Status
+#define AT91C_MC_ABTSZ_BYTE (0x0u << 8) // (MC) Byte
+#define AT91C_MC_ABTSZ_HWORD (0x1u << 8) // (MC) Half-word
+#define AT91C_MC_ABTSZ_WORD (0x2u << 8) // (MC) Word
+#define AT91C_MC_ABTTYP (0x3u << 10) // (MC) Abort Type Status
+#define AT91C_MC_ABTTYP_DATAR (0x0u << 10) // (MC) Data Read
+#define AT91C_MC_ABTTYP_DATAW (0x1u << 10) // (MC) Data Write
+#define AT91C_MC_ABTTYP_FETCH (0x2u << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0 (0x1u << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1 (0x1u << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0 (0x1u << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1 (0x1u << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_PUIA : (MC Offset: 0x10) MC Protection Unit Area --------
+#define AT91C_MC_PROT (0x3u << 0) // (MC) Protection
+#define AT91C_MC_PROT_PNAUNA 0x0u // (MC) Privilege: No Access, User: No Access
+#define AT91C_MC_PROT_PRWUNA 0x1u // (MC) Privilege: Read/Write, User: No Access
+#define AT91C_MC_PROT_PRWURO 0x2u // (MC) Privilege: Read/Write, User: Read Only
+#define AT91C_MC_PROT_PRWURW 0x3u // (MC) Privilege: Read/Write, User: Read/Write
+#define AT91C_MC_SIZE (0xFu << 4) // (MC) Internal Area Size
+#define AT91C_MC_SIZE_1KB (0x0u << 4) // (MC) Area size 1KByte
+#define AT91C_MC_SIZE_2KB (0x1u << 4) // (MC) Area size 2KByte
+#define AT91C_MC_SIZE_4KB (0x2u << 4) // (MC) Area size 4KByte
+#define AT91C_MC_SIZE_8KB (0x3u << 4) // (MC) Area size 8KByte
+#define AT91C_MC_SIZE_16KB (0x4u << 4) // (MC) Area size 16KByte
+#define AT91C_MC_SIZE_32KB (0x5u << 4) // (MC) Area size 32KByte
+#define AT91C_MC_SIZE_64KB (0x6u << 4) // (MC) Area size 64KByte
+#define AT91C_MC_SIZE_128KB (0x7u << 4) // (MC) Area size 128KByte
+#define AT91C_MC_SIZE_256KB (0x8u << 4) // (MC) Area size 256KByte
+#define AT91C_MC_SIZE_512KB (0x9u << 4) // (MC) Area size 512KByte
+#define AT91C_MC_SIZE_1MB (0xAu << 4) // (MC) Area size 1MByte
+#define AT91C_MC_SIZE_2MB (0xBu << 4) // (MC) Area size 2MByte
+#define AT91C_MC_SIZE_4MB (0xCu << 4) // (MC) Area size 4MByte
+#define AT91C_MC_SIZE_8MB (0xDu << 4) // (MC) Area size 8MByte
+#define AT91C_MC_SIZE_16MB (0xEu << 4) // (MC) Area size 16MByte
+#define AT91C_MC_SIZE_64MB (0xFu << 4) // (MC) Area size 64MByte
+#define AT91C_MC_BA (0x3FFFFu << 10) // (MC) Internal Area Base Address
+// -------- MC_PUP : (MC Offset: 0x50) MC Protection Unit Peripheral --------
+// -------- MC_PUER : (MC Offset: 0x54) MC Protection Unit Area --------
+#define AT91C_MC_PUEB (0x1u << 0) // (MC) Protection Unit enable Bit
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface
+// *****************************************************************************
+typedef struct _AT91S_RTC {
+ AT91_REG RTC_CR; // Control Register
+ AT91_REG RTC_MR; // Mode Register
+ AT91_REG RTC_TIMR; // Time Register
+ AT91_REG RTC_CALR; // Calendar Register
+ AT91_REG RTC_TIMALR; // Time Alarm Register
+ AT91_REG RTC_CALALR; // Calendar Alarm Register
+ AT91_REG RTC_SR; // Status Register
+ AT91_REG RTC_SCCR; // Status Clear Command Register
+ AT91_REG RTC_IER; // Interrupt Enable Register
+ AT91_REG RTC_IDR; // Interrupt Disable Register
+ AT91_REG RTC_IMR; // Interrupt Mask Register
+ AT91_REG RTC_VER; // Valid Entry Register
+} AT91S_RTC, *AT91PS_RTC;
+
+// -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register --------
+#define AT91C_RTC_UPDTIM (0x1u << 0) // (RTC) Update Request Time Register
+#define AT91C_RTC_UPDCAL (0x1u << 1) // (RTC) Update Request Calendar Register
+#define AT91C_RTC_TIMEVSEL (0x3u << 8) // (RTC) Time Event Selection
+#define AT91C_RTC_TIMEVSEL_MINUTE (0x0u << 8) // (RTC) Minute change.
+#define AT91C_RTC_TIMEVSEL_HOUR (0x1u << 8) // (RTC) Hour change.
+#define AT91C_RTC_TIMEVSEL_DAY24 (0x2u << 8) // (RTC) Every day at midnight.
+#define AT91C_RTC_TIMEVSEL_DAY12 (0x3u << 8) // (RTC) Every day at noon.
+#define AT91C_RTC_CALEVSEL (0x3u << 16) // (RTC) Calendar Event Selection
+#define AT91C_RTC_CALEVSEL_WEEK (0x0u << 16) // (RTC) Week change (every Monday at time 00:00:00).
+#define AT91C_RTC_CALEVSEL_MONTH (0x1u << 16) // (RTC) Month change (every 01 of each month at time 00:00:00).
+#define AT91C_RTC_CALEVSEL_YEAR (0x2u << 16) // (RTC) Year change (every January 1 at time 00:00:00).
+// -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register --------
+#define AT91C_RTC_HRMOD (0x1u << 0) // (RTC) 12-24 hour Mode
+// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register --------
+#define AT91C_RTC_SEC (0x7Fu << 0) // (RTC) Current Second
+#define AT91C_RTC_MIN (0x7Fu << 8) // (RTC) Current Minute
+#define AT91C_RTC_HOUR (0x1Fu << 16) // (RTC) Current Hour
+#define AT91C_RTC_AMPM (0x1u << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator
+// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register --------
+#define AT91C_RTC_CENT (0x3Fu << 0) // (RTC) Current Century
+#define AT91C_RTC_YEAR (0xFFu << 8) // (RTC) Current Year
+#define AT91C_RTC_MONTH (0x1Fu << 16) // (RTC) Current Month
+#define AT91C_RTC_DAY (0x7u << 21) // (RTC) Current Day
+#define AT91C_RTC_DATE (0x3Fu << 24) // (RTC) Current Date
+// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register --------
+#define AT91C_RTC_SECEN (0x1u << 7) // (RTC) Second Alarm Enable
+#define AT91C_RTC_MINEN (0x1u << 15) // (RTC) Minute Alarm
+#define AT91C_RTC_HOUREN (0x1u << 23) // (RTC) Current Hour
+// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register --------
+#define AT91C_RTC_MONTHEN (0x1u << 23) // (RTC) Month Alarm Enable
+#define AT91C_RTC_DATEEN (0x1u << 31) // (RTC) Date Alarm Enable
+// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register --------
+#define AT91C_RTC_ACKUPD (0x1u << 0) // (RTC) Acknowledge for Update
+#define AT91C_RTC_ALARM (0x1u << 1) // (RTC) Alarm Flag
+#define AT91C_RTC_SECEV (0x1u << 2) // (RTC) Second Event
+#define AT91C_RTC_TIMEV (0x1u << 3) // (RTC) Time Event
+#define AT91C_RTC_CALEV (0x1u << 4) // (RTC) Calendar event
+// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register --------
+// -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register --------
+// -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register --------
+// -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register --------
+// -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register --------
+#define AT91C_RTC_NVTIM (0x1u << 0) // (RTC) Non valid Time
+#define AT91C_RTC_NVCAL (0x1u << 1) // (RTC) Non valid Calendar
+#define AT91C_RTC_NVTIMALR (0x1u << 2) // (RTC) Non valid time Alarm
+#define AT91C_RTC_NVCALALR (0x1u << 3) // (RTC) Nonvalid Calendar Alarm
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Timer Interface
+// *****************************************************************************
+typedef struct _AT91S_ST {
+ AT91_REG ST_CR; // Control Register
+ AT91_REG ST_PIMR; // Period Interval Mode Register
+ AT91_REG ST_WDMR; // Watchdog Mode Register
+ AT91_REG ST_RTMR; // Real-time Mode Register
+ AT91_REG ST_SR; // Status Register
+ AT91_REG ST_IER; // Interrupt Enable Register
+ AT91_REG ST_IDR; // Interrupt Disable Register
+ AT91_REG ST_IMR; // Interrupt Mask Register
+ AT91_REG ST_RTAR; // Real-time Alarm Register
+ AT91_REG ST_CRTR; // Current Real-time Register
+} AT91S_ST, *AT91PS_ST;
+
+// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register --------
+#define AT91C_ST_WDRST (0x1u << 0) // (ST) Watchdog Timer Restart
+// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register --------
+#define AT91C_ST_PIV (0xFFFFu << 0) // (ST) Watchdog Timer Restart
+// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register --------
+#define AT91C_ST_WDV (0xFFFFu << 0) // (ST) Watchdog Timer Restart
+#define AT91C_ST_RSTEN (0x1u << 16) // (ST) Reset Enable
+#define AT91C_ST_EXTEN (0x1u << 17) // (ST) External Signal Assertion Enable
+// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register --------
+#define AT91C_ST_RTPRES (0xFFFFu << 0) // (ST) Real-time Timer Prescaler Value
+// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register --------
+#define AT91C_ST_PITS (0x1u << 0) // (ST) Period Interval Timer Interrupt
+#define AT91C_ST_WDOVF (0x1u << 1) // (ST) Watchdog Overflow
+#define AT91C_ST_RTTINC (0x1u << 2) // (ST) Real-time Timer Increment
+#define AT91C_ST_ALMS (0x1u << 3) // (ST) Alarm Status
+// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register --------
+// -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register --------
+// -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register --------
+// -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register --------
+#define AT91C_ST_ALMV (0xFFFFFu << 0) // (ST) Alarm Value Value
+// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register --------
+#define AT91C_ST_CRTV (0xFFFFFu << 0) // (ST) Current Real-time Value
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[5]; //
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved2[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1u << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP (0x1u << 1) // (PMC) USB Device Port Clock
+#define AT91C_PMC_MCKUDP (0x1u << 2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend
+#define AT91C_PMC_UHP (0x1u << 4) // (PMC) USB Host Port Clock
+#define AT91C_PMC_PCK0 (0x1u << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1u << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1u << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1u << 11) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK4 (0x1u << 12) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK5 (0x1u << 13) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK6 (0x1u << 14) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK7 (0x1u << 15) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3u << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK 0x0u // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK 0x1u // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLLA_CLK 0x2u // (PMC) Clock from PLL A is selected
+#define AT91C_PMC_CSS_PLLB_CLK 0x3u // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES (0x7u << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0u << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1u << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2u << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3u << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4u << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5u << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6u << 2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV (0x3u << 8) // (PMC) Master Clock Division
+#define AT91C_PMC_MDIV_1 (0x0u << 8) // (PMC) The master clock and the processor clock are the same
+#define AT91C_PMC_MDIV_2 (0x1u << 8) // (PMC) The processor clock is twice as fast as the master clock
+#define AT91C_PMC_MDIV_3 (0x2u << 8) // (PMC) The processor clock is three times faster than the master clock
+#define AT91C_PMC_MDIV_4 (0x3u << 8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1u << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA (0x1u << 1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB (0x1u << 2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1u << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1u << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1u << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1u << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1u << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK4RDY (0x1u << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK5RDY (0x1u << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK6RDY (0x1u << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK7RDY (0x1u << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG CKGR_PLLAR; // PLL A Register
+ AT91_REG CKGR_PLLBR; // PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1u << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCTEST (0x1u << 1) // (CKGR) Oscillator Test
+#define AT91C_CKGR_OSCOUNT (0xFFu << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFFu << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1u << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
+#define AT91C_CKGR_DIVA (0xFFu << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIVA_0 0x0u // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIVA_BYPASS 0x1u // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLACOUNT (0x3Fu << 8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA (0x3u << 14) // (CKGR) PLL A Output Frequency Range
+#define AT91C_CKGR_OUTA_0 (0x0u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_1 (0x1u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_2 (0x2u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_3 (0x3u << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA (0x7FFu << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA (0x1u << 29) // (CKGR) PLL A Source
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIVB (0xFFu << 0) // (CKGR) Divider Selected
+#define AT91C_CKGR_DIVB_0 0x0u // (CKGR) Divider output is 0
+#define AT91C_CKGR_DIVB_BYPASS 0x1u // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLBCOUNT (0x3Fu << 8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB (0x3u << 14) // (CKGR) PLL B Output Frequency Range
+#define AT91C_CKGR_OUTB_0 (0x0u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_1 (0x1u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_2 (0x2u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_3 (0x3u << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB (0x7FFu << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USB_96M (0x1u << 28) // (CKGR) Divider for USB Ports
+#define AT91C_CKGR_USB_PLL (0x1u << 29) // (CKGR) PLL Use
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pad Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_C1R; // Chip ID1 Register
+ AT91_REG DBGU_C2R; // Chip ID2 Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1u << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1u << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1u << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1u << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1u << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1u << 7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7u << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0u << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1u << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2u << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3u << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4u << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6u << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3u << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0u << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1u << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2u << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3u << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1u << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1u << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1u << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1u << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1u << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1u << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1u << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1u << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1u << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1u << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1u << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1u << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1u << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral Data Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1u << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1u << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1u << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1u << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7u << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST 0x0u // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST 0x7u // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3u << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0u << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1u << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2u << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3u << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1u << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1u << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1u << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1u << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1u << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1u << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1u << 7) // (SPI) SPI Software reset
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1u << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1u << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0u << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1u << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1u << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_DIV32 (0x1u << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1u << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1u << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xFu << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFFu << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFFu << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFFu << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xFu << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1u << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1u << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1u << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1u << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_SPENDRX (0x1u << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_SPENDTX (0x1u << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1u << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1u << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_SPIENS (0x1u << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1u << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1u << 1) // (SPI) Clock Phase
+#define AT91C_SPI_BITS (0xFu << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0u << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1u << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2u << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3u << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4u << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5u << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6u << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7u << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8u << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFFu << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFFu << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT (0xFFu << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG SSC_RC0R; // Receive Compare 0 Register
+ AT91_REG SSC_RC1R; // Receive Compare 1 Register
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1u << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1u << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1u << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1u << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1u << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3u << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV 0x0u // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK 0x1u // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK 0x2u // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7u << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0u << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1u << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2u << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1u << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG (0x3u << 6) // (SSC) Receive/Transmit Clock Gating Selection
+#define AT91C_SSC_CKG_NONE (0x0u << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define AT91C_SSC_CKG_LOW (0x1u << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define AT91C_SSC_CKG_HIGH (0x2u << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START (0xFu << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0u << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1u << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2u << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3u << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4u << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5u << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6u << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7u << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8u << 8) // (SSC) Compare 0
+#define AT91C_SSC_STOP (0x1u << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT (0x1u << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY (0xFFu << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFFu << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1Fu << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1u << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1u << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xFu << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xFu << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7u << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5u << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1u << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1u << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1u << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1u << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1u << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1u << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1u << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1u << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1u << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1u << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1u << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0 (0x1u << 8) // (SSC) Compare 0
+#define AT91C_SSC_CP1 (0x1u << 9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN (0x1u << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1u << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1u << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1u << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG US_XXR; // XON_XOFF Register
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved1[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTSTA (0x1u << 8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK (0x1u << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1u << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1u << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1u << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1u << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1u << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1u << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1u << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1u << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1u << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1u << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xFu << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL 0x0u // (USART) Normal
+#define AT91C_US_USMODE_RS485 0x1u // (USART) RS485
+#define AT91C_US_USMODE_HWHSH 0x2u // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM 0x3u // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 0x4u // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 0x6u // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA 0x8u // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH 0xCu // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3u << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0u << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1u << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2u << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3u << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3u << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0u << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1u << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2u << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3u << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1u << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3u << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0u << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1u << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2u << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1u << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1u << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1u << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1u << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1u << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1u << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1u << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1u << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1u << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1u << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1u << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1u << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1u << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1u << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1u << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1u << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1u << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1u << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1u << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1u << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG TWI_SMR; // Slave Mode Register
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved0[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1u << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1u << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1u << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1u << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN (0x1u << 4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS (0x1u << 5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST (0x1u << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3u << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0u << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1u << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2u << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3u << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1u << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7Fu << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
+#define AT91C_TWI_SADR (0x7Fu << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFFu << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFFu << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7u << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP (0x1u << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1u << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY (0x1u << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD (0x1u << 3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC (0x1u << 4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC (0x1u << 5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE (0x1u << 6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE (0x1u << 7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK (0x1u << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST (0x1u << 9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Multimedia Card Interface
+// *****************************************************************************
+typedef struct _AT91S_MCI {
+ AT91_REG MCI_CR; // MCI Control Register
+ AT91_REG MCI_MR; // MCI Mode Register
+ AT91_REG MCI_DTOR; // MCI Data Timeout Register
+ AT91_REG MCI_SDCR; // MCI SD Card Register
+ AT91_REG MCI_ARGR; // MCI Argument Register
+ AT91_REG MCI_CMDR; // MCI Command Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG MCI_RSPR[4]; // MCI Response Register
+ AT91_REG MCI_RDR; // MCI Receive Data Register
+ AT91_REG MCI_TDR; // MCI Transmit Data Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG MCI_SR; // MCI Status Register
+ AT91_REG MCI_IER; // MCI Interrupt Enable Register
+ AT91_REG MCI_IDR; // MCI Interrupt Disable Register
+ AT91_REG MCI_IMR; // MCI Interrupt Mask Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG MCI_RPR; // Receive Pointer Register
+ AT91_REG MCI_RCR; // Receive Counter Register
+ AT91_REG MCI_TPR; // Transmit Pointer Register
+ AT91_REG MCI_TCR; // Transmit Counter Register
+ AT91_REG MCI_RNPR; // Receive Next Pointer Register
+ AT91_REG MCI_RNCR; // Receive Next Counter Register
+ AT91_REG MCI_TNPR; // Transmit Next Pointer Register
+ AT91_REG MCI_TNCR; // Transmit Next Counter Register
+ AT91_REG MCI_PTCR; // PDC Transfer Control Register
+ AT91_REG MCI_PTSR; // PDC Transfer Status Register
+} AT91S_MCI, *AT91PS_MCI;
+
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
+#define AT91C_MCI_MCIEN (0x1u << 0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIDIS (0x1u << 1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_PWSEN (0x1u << 2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSDIS (0x1u << 3) // (MCI) Power Save Mode Disable
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
+#define AT91C_MCI_CLKDIV (0x1u << 0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV (0x1u << 8) // (MCI) Power Saving Divider
+#define AT91C_MCI_PDCPADV (0x1u << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE (0x1u << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_BLKLEN (0x1u << 18) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
+#define AT91C_MCI_DTOCYC (0x1u << 0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL (0x7u << 4) // (MCI) Data Timeout Multiplier
+#define AT91C_MCI_DTOMUL_1 (0x0u << 4) // (MCI) DTOCYC x 1
+#define AT91C_MCI_DTOMUL_16 (0x1u << 4) // (MCI) DTOCYC x 16
+#define AT91C_MCI_DTOMUL_128 (0x2u << 4) // (MCI) DTOCYC x 128
+#define AT91C_MCI_DTOMUL_256 (0x3u << 4) // (MCI) DTOCYC x 256
+#define AT91C_MCI_DTOMUL_1024 (0x4u << 4) // (MCI) DTOCYC x 1024
+#define AT91C_MCI_DTOMUL_4096 (0x5u << 4) // (MCI) DTOCYC x 4096
+#define AT91C_MCI_DTOMUL_65536 (0x6u << 4) // (MCI) DTOCYC x 65536
+#define AT91C_MCI_DTOMUL_1048576 (0x7u << 4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
+#define AT91C_MCI_SCDSEL (0x1u << 0) // (MCI) SD Card Selector
+#define AT91C_MCI_SCDBUS (0x1u << 7) // (MCI) SD Card Bus Width
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
+#define AT91C_MCI_CMDRDY (0x1u << 0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY (0x1u << 1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY (0x1u << 2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE (0x1u << 3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP (0x1u << 4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY (0x1u << 5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX (0x1u << 6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX (0x1u << 7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_RXBUFF (0x1u << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE (0x1u << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE (0x1u << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE (0x1u << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE (0x1u << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE (0x1u << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE (0x1u << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE (0x1u << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE (0x1u << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_OVRE (0x1u << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE (0x1u << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[8]; // Endpoint Control and Status Register
+ AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FFu << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1u << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1u << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1u << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1u << 1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE (0x1u << 2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR (0x1u << 3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFFu << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1u << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1u << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1u << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1u << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1u << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1u << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1u << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6 (0x1u << 6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7 (0x1u << 7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP (0x1u << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1u << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1u << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1u << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1u << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1u << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1u << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1u << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1u << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1u << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1u << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1u << 5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6 (0x1u << 6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7 (0x1u << 7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1u << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1u << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1u << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1u << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1u << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1u << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1u << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1u << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7u << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0u << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1u << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2u << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3u << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5u << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6u << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7u << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1u << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1u << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FFu << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1u << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1u << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1u << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CPCSTOP (0x1u << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_CPCDIS (0x1u << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_EEVTEDG (0x3u << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0u << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1u << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2u << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3u << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3u << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_NONE (0x0u << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_RISING (0x1u << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_FALLING (0x2u << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_BOTH (0x3u << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG (0x1u << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3u << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0u << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x1u << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x2u << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3u << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1u << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1u << 15) // (TC)
+#define AT91C_TC_ACPA (0x3u << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0u << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1u << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2u << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3u << 16) // (TC) Effect: toggle
+#define AT91C_TC_ACPC (0x3u << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0u << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1u << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2u << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3u << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT (0x3u << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0u << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1u << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2u << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3u << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3u << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0u << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1u << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2u << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3u << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3u << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0u << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1u << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2u << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3u << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3u << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0u << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1u << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2u << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3u << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3u << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0u << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1u << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2u << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3u << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3u << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0u << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1u << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2u << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3u << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1u << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1u << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1u << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1u << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1u << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1u << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1u << 6) // (TC) RB Loading
+#define AT91C_TC_ETRCS (0x1u << 7) // (TC) External Trigger
+#define AT91C_TC_ETRGS (0x1u << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1u << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1u << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1u << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x1u << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 0x0u // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE 0x1u // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 0x2u // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 0x3u // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x1u << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0u << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1u << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2u << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3u << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x1u << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0u << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1u << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2u << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA2 (0x3u << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Host Interface
+// *****************************************************************************
+typedef struct _AT91S_UHP {
+ AT91_REG UHP_HcRevision; // Revision
+ AT91_REG UHP_HcControl; // Operating modes for the Host Controller
+ AT91_REG UHP_HcCommandStatus; // Command & status Register
+ AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
+ AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
+ AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
+ AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
+ AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
+ AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
+ AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
+ AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
+ AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
+ AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
+ AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
+ AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
+ AT91_REG UHP_HcFmNumber; // Frame number
+ AT91_REG UHP_HcPeriodicStart; // Periodic Start
+ AT91_REG UHP_HcLSThreshold; // LS Threshold
+ AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
+ AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
+ AT91_REG UHP_HcRhStatus; // Root Hub Status register
+ AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Ethernet MAC
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+ AT91_REG EMAC_CTL; // Network Control Register
+ AT91_REG EMAC_CFG; // Network Configuration Register
+ AT91_REG EMAC_SR; // Network Status Register
+ AT91_REG EMAC_TAR; // Transmit Address Register
+ AT91_REG EMAC_TCR; // Transmit Control Register
+ AT91_REG EMAC_TSR; // Transmit Status Register
+ AT91_REG EMAC_RBQP; // Receive Buffer Queue Pointer
+ AT91_REG Reserved0[1]; //
+ AT91_REG EMAC_RSR; // Receive Status Register
+ AT91_REG EMAC_ISR; // Interrupt Status Register
+ AT91_REG EMAC_IER; // Interrupt Enable Register
+ AT91_REG EMAC_IDR; // Interrupt Disable Register
+ AT91_REG EMAC_IMR; // Interrupt Mask Register
+ AT91_REG EMAC_MAN; // PHY Maintenance Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG EMAC_FRA; // Frames Transmitted OK Register
+ AT91_REG EMAC_SCOL; // Single Collision Frame Register
+ AT91_REG EMAC_MCOL; // Multiple Collision Frame Register
+ AT91_REG EMAC_OK; // Frames Received OK Register
+ AT91_REG EMAC_SEQE; // Frame Check Sequence Error Register
+ AT91_REG EMAC_ALE; // Alignment Error Register
+ AT91_REG EMAC_DTE; // Deferred Transmission Frame Register
+ AT91_REG EMAC_LCOL; // Late Collision Register
+ AT91_REG EMAC_ECOL; // Excessive Collision Register
+ AT91_REG EMAC_CSE; // Carrier Sense Error Register
+ AT91_REG EMAC_TUE; // Transmit Underrun Error Register
+ AT91_REG EMAC_CDE; // Code Error Register
+ AT91_REG EMAC_ELR; // Excessive Length Error Register
+ AT91_REG EMAC_RJB; // Receive Jabber Register
+ AT91_REG EMAC_USF; // Undersize Frame Register
+ AT91_REG EMAC_SQEE; // SQE Test Error Register
+ AT91_REG EMAC_DRFC; // Discarded RX Frame Register
+ AT91_REG Reserved2[3]; //
+ AT91_REG EMAC_HSH; // Hash Address High[63:32]
+ AT91_REG EMAC_HSL; // Hash Address Low[31:0]
+ AT91_REG EMAC_SA1L; // Specific Address 1 Low, First 4 bytes
+ AT91_REG EMAC_SA1H; // Specific Address 1 High, Last 2 bytes
+ AT91_REG EMAC_SA2L; // Specific Address 2 Low, First 4 bytes
+ AT91_REG EMAC_SA2H; // Specific Address 2 High, Last 2 bytes
+ AT91_REG EMAC_SA3L; // Specific Address 3 Low, First 4 bytes
+ AT91_REG EMAC_SA3H; // Specific Address 3 High, Last 2 bytes
+ AT91_REG EMAC_SA4L; // Specific Address 4 Low, First 4 bytes
+ AT91_REG EMAC_SA4H; // Specific Address 4 High, Last 2 bytesr
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_CTL : (EMAC Offset: 0x0) --------
+#define AT91C_EMAC_LB (0x1u << 0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LBL (0x1u << 1) // (EMAC) Loopback local.
+#define AT91C_EMAC_RE (0x1u << 2) // (EMAC) Receive enable.
+#define AT91C_EMAC_TE (0x1u << 3) // (EMAC) Transmit enable.
+#define AT91C_EMAC_MPE (0x1u << 4) // (EMAC) Management port enable.
+#define AT91C_EMAC_CSR (0x1u << 5) // (EMAC) Clear statistics registers.
+#define AT91C_EMAC_ISR (0x1u << 6) // (EMAC) Increment statistics registers.
+#define AT91C_EMAC_WES (0x1u << 7) // (EMAC) Write enable for statistics registers.
+#define AT91C_EMAC_BP (0x1u << 8) // (EMAC) Back pressure.
+// -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------
+#define AT91C_EMAC_SPD (0x1u << 0) // (EMAC) Speed.
+#define AT91C_EMAC_FD (0x1u << 1) // (EMAC) Full duplex.
+#define AT91C_EMAC_BR (0x1u << 2) // (EMAC) Bit rate.
+#define AT91C_EMAC_CAF (0x1u << 4) // (EMAC) Copy all frames.
+#define AT91C_EMAC_NBC (0x1u << 5) // (EMAC) No broadcast.
+#define AT91C_EMAC_MTI (0x1u << 6) // (EMAC) Multicast hash enable
+#define AT91C_EMAC_UNI (0x1u << 7) // (EMAC) Unicast hash enable.
+#define AT91C_EMAC_BIG (0x1u << 8) // (EMAC) Receive 1522 bytes.
+#define AT91C_EMAC_EAE (0x1u << 9) // (EMAC) External address match enable.
+#define AT91C_EMAC_CLK (0x3u << 10) // (EMAC)
+#define AT91C_EMAC_CLK_HCLK_8 (0x0u << 10) // (EMAC) HCLK divided by 8
+#define AT91C_EMAC_CLK_HCLK_16 (0x1u << 10) // (EMAC) HCLK divided by 16
+#define AT91C_EMAC_CLK_HCLK_32 (0x2u << 10) // (EMAC) HCLK divided by 32
+#define AT91C_EMAC_CLK_HCLK_64 (0x3u << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY (0x1u << 12) // (EMAC)
+#define AT91C_EMAC_RMII (0x1u << 13) // (EMAC)
+// -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------
+#define AT91C_EMAC_MDIO (0x1u << 1) // (EMAC)
+#define AT91C_EMAC_IDLE (0x1u << 2) // (EMAC)
+// -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------
+#define AT91C_EMAC_LEN (0x7FFu << 0) // (EMAC)
+#define AT91C_EMAC_NCRC (0x1u << 15) // (EMAC)
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------
+#define AT91C_EMAC_OVR (0x1u << 0) // (EMAC)
+#define AT91C_EMAC_COL (0x1u << 1) // (EMAC)
+#define AT91C_EMAC_RLE (0x1u << 2) // (EMAC)
+#define AT91C_EMAC_TXIDLE (0x1u << 3) // (EMAC)
+#define AT91C_EMAC_BNQ (0x1u << 4) // (EMAC)
+#define AT91C_EMAC_COMP (0x1u << 5) // (EMAC)
+#define AT91C_EMAC_UND (0x1u << 6) // (EMAC)
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------
+#define AT91C_EMAC_BNA (0x1u << 0) // (EMAC)
+#define AT91C_EMAC_REC (0x1u << 1) // (EMAC)
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------
+#define AT91C_EMAC_DONE (0x1u << 0) // (EMAC)
+#define AT91C_EMAC_RCOM (0x1u << 1) // (EMAC)
+#define AT91C_EMAC_RBNA (0x1u << 2) // (EMAC)
+#define AT91C_EMAC_TOVR (0x1u << 3) // (EMAC)
+#define AT91C_EMAC_TUND (0x1u << 4) // (EMAC)
+#define AT91C_EMAC_RTRY (0x1u << 5) // (EMAC)
+#define AT91C_EMAC_TBRE (0x1u << 6) // (EMAC)
+#define AT91C_EMAC_TCOM (0x1u << 7) // (EMAC)
+#define AT91C_EMAC_TIDLE (0x1u << 8) // (EMAC)
+#define AT91C_EMAC_LINK (0x1u << 9) // (EMAC)
+#define AT91C_EMAC_ROVR (0x1u << 10) // (EMAC)
+#define AT91C_EMAC_HRESP (0x1u << 11) // (EMAC)
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register --------
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------
+#define AT91C_EMAC_DATA (0xFFFFu << 0) // (EMAC)
+#define AT91C_EMAC_CODE (0x3u << 16) // (EMAC)
+#define AT91C_EMAC_REGA (0x1Fu << 18) // (EMAC)
+#define AT91C_EMAC_PHYA (0x1Fu << 23) // (EMAC)
+#define AT91C_EMAC_RW (0x3u << 28) // (EMAC)
+#define AT91C_EMAC_HIGH (0x1u << 30) // (EMAC)
+#define AT91C_EMAC_LOW (0x1u << 31) // (EMAC)
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR External Bus Interface
+// *****************************************************************************
+typedef struct _AT91S_EBI {
+ AT91_REG EBI_CSA; // Chip Select Assignment Register
+ AT91_REG EBI_CFGR; // Configuration Register
+} AT91S_EBI, *AT91PS_EBI;
+
+// -------- EBI_CSA : (EBI Offset: 0x0) Chip Select Assignment Register --------
+#define AT91C_EBI_CS0A (0x1u << 0) // (EBI) Chip Select 0 Assignment
+#define AT91C_EBI_CS0A_SMC 0x0u // (EBI) Chip Select 0 is assigned to the Static Memory Controller.
+#define AT91C_EBI_CS0A_BFC 0x1u // (EBI) Chip Select 0 is assigned to the Burst Flash Controller.
+#define AT91C_EBI_CS1A (0x1u << 1) // (EBI) Chip Select 1 Assignment
+#define AT91C_EBI_CS1A_SMC (0x0u << 1) // (EBI) Chip Select 1 is assigned to the Static Memory Controller.
+#define AT91C_EBI_CS1A_SDRAMC (0x1u << 1) // (EBI) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_EBI_CS3A (0x1u << 3) // (EBI) Chip Select 3 Assignment
+#define AT91C_EBI_CS3A_SMC (0x0u << 3) // (EBI) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC2.
+#define AT91C_EBI_CS3A_SMC_SmartMedia (0x1u << 3) // (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_EBI_CS4A (0x1u << 4) // (EBI) Chip Select 4 Assignment
+#define AT91C_EBI_CS4A_SMC (0x0u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and NCS4,NCS5 and NCS6 behave as defined by the SMC2.
+#define AT91C_EBI_CS4A_SMC_CompactFlash (0x1u << 4) // (EBI) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated.
+// -------- EBI_CFGR : (EBI Offset: 0x4) Configuration Register --------
+#define AT91C_EBI_DBPUC (0x1u << 0) // (EBI) Data Bus Pull-Up Configuration
+#define AT91C_EBI_EBSEN (0x1u << 1) // (EBI) Bus Sharing Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface
+// *****************************************************************************
+typedef struct _AT91S_SMC2 {
+ AT91_REG SMC2_CSR[8]; // SMC2 Chip Select Register
+} AT91S_SMC2, *AT91PS_SMC2;
+
+// -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------
+#define AT91C_SMC2_NWS (0x7Fu << 0) // (SMC2) Number of Wait States
+#define AT91C_SMC2_WSEN (0x1u << 7) // (SMC2) Wait State Enable
+#define AT91C_SMC2_TDF (0xFu << 8) // (SMC2) Data Float Time
+#define AT91C_SMC2_BAT (0x1u << 12) // (SMC2) Byte Access Type
+#define AT91C_SMC2_DBW (0x1u << 13) // (SMC2) Data Bus Width
+#define AT91C_SMC2_DBW_16 (0x1u << 13) // (SMC2) 16-bit.
+#define AT91C_SMC2_DBW_8 (0x2u << 13) // (SMC2) 8-bit.
+#define AT91C_SMC2_DRP (0x1u << 15) // (SMC2) Data Read Protocol
+#define AT91C_SMC2_ACSS (0x3u << 16) // (SMC2) Address to Chip Select Setup
+#define AT91C_SMC2_ACSS_STANDARD (0x0u << 16) // (SMC2) Standard, asserted at the beginning of the access and deasserted at the end.
+#define AT91C_SMC2_ACSS_1_CYCLE (0x1u << 16) // (SMC2) One cycle less at the beginning and the end of the access.
+#define AT91C_SMC2_ACSS_2_CYCLES (0x2u << 16) // (SMC2) Two cycles less at the beginning and the end of the access.
+#define AT91C_SMC2_ACSS_3_CYCLES (0x3u << 16) // (SMC2) Three cycles less at the beginning and the end of the access.
+#define AT91C_SMC2_RWSETUP (0x7u << 24) // (SMC2) Read and Write Signal Setup Time
+#define AT91C_SMC2_RWHOLD (0x7u << 29) // (SMC2) Read and Write Signal Hold Time
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SDRC {
+ AT91_REG SDRC_MR; // SDRAM Controller Mode Register
+ AT91_REG SDRC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG SDRC_CR; // SDRAM Controller Configuration Register
+ AT91_REG SDRC_SRR; // SDRAM Controller Self Refresh Register
+ AT91_REG SDRC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG SDRC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG SDRC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG SDRC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRC_ISR; // SDRAM Controller Interrupt Mask Register
+} AT91S_SDRC, *AT91PS_SDRC;
+
+// -------- SDRC_MR : (SDRC Offset: 0x0) SDRAM Controller Mode Register --------
+#define AT91C_SDRC_MODE (0xFu << 0) // (SDRC) Mode
+#define AT91C_SDRC_MODE_NORMAL_CMD 0x0u // (SDRC) Normal Mode
+#define AT91C_SDRC_MODE_NOP_CMD 0x1u // (SDRC) NOP Command
+#define AT91C_SDRC_MODE_PRCGALL_CMD 0x2u // (SDRC) All Banks Precharge Command
+#define AT91C_SDRC_MODE_LMR_CMD 0x3u // (SDRC) Load Mode Register Command
+#define AT91C_SDRC_MODE_RFSH_CMD 0x4u // (SDRC) Refresh Command
+#define AT91C_SDRC_DBW (0x1u << 4) // (SDRC) Data Bus Width
+#define AT91C_SDRC_DBW_32_BITS (0x0u << 4) // (SDRC) 32 Bits datas bus
+#define AT91C_SDRC_DBW_16_BITS (0x1u << 4) // (SDRC) 16 Bits datas bus
+// -------- SDRC_TR : (SDRC Offset: 0x4) SDRC Refresh Timer Register --------
+#define AT91C_SDRC_COUNT (0xFFFu << 0) // (SDRC) Refresh Counter
+// -------- SDRC_CR : (SDRC Offset: 0x8) SDRAM Configuration Register --------
+#define AT91C_SDRC_NC (0x3u << 0) // (SDRC) Number of Column Bits
+#define AT91C_SDRC_NC_8 0x0u // (SDRC) 8 Bits
+#define AT91C_SDRC_NC_9 0x1u // (SDRC) 9 Bits
+#define AT91C_SDRC_NC_10 0x2u // (SDRC) 10 Bits
+#define AT91C_SDRC_NC_11 0x3u // (SDRC) 11 Bits
+#define AT91C_SDRC_NR (0x3u << 2) // (SDRC) Number of Row Bits
+#define AT91C_SDRC_NR_11 (0x0u << 2) // (SDRC) 11 Bits
+#define AT91C_SDRC_NR_12 (0x1u << 2) // (SDRC) 12 Bits
+#define AT91C_SDRC_NR_13 (0x2u << 2) // (SDRC) 13 Bits
+#define AT91C_SDRC_NB (0x1u << 4) // (SDRC) Number of Banks
+#define AT91C_SDRC_NB_2_BANKS (0x0u << 4) // (SDRC) 2 banks
+#define AT91C_SDRC_NB_4_BANKS (0x1u << 4) // (SDRC) 4 banks
+#define AT91C_SDRC_CAS (0x3u << 5) // (SDRC) CAS Latency
+#define AT91C_SDRC_CAS_2 (0x2u << 5) // (SDRC) 2 cycles
+#define AT91C_SDRC_TWR (0xFu << 7) // (SDRC) Number of Write Recovery Time Cycles
+#define AT91C_SDRC_TRC (0xFu << 11) // (SDRC) Number of RAS Cycle Time Cycles
+#define AT91C_SDRC_TRP (0xFu << 15) // (SDRC) Number of RAS Precharge Time Cycles
+#define AT91C_SDRC_TRCD (0xFu << 19) // (SDRC) Number of RAS to CAS Delay Cycles
+#define AT91C_SDRC_TRAS (0xFu << 23) // (SDRC) Number of RAS Active Time Cycles
+#define AT91C_SDRC_TXSR (0xFu << 27) // (SDRC) Number of Command Recovery Time Cycles
+// -------- SDRC_SRR : (SDRC Offset: 0xc) SDRAM Controller Self-refresh Register --------
+#define AT91C_SDRC_SRCB (0x1u << 0) // (SDRC) Self-refresh Command Bit
+// -------- SDRC_LPR : (SDRC Offset: 0x10) SDRAM Controller Low-power Register --------
+#define AT91C_SDRC_LPCB (0x1u << 0) // (SDRC) Low-power Command Bit
+// -------- SDRC_IER : (SDRC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
+#define AT91C_SDRC_RES (0x1u << 0) // (SDRC) Refresh Error Status
+// -------- SDRC_IDR : (SDRC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
+// -------- SDRC_IMR : (SDRC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
+// -------- SDRC_ISR : (SDRC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Burst Flash Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_BFC {
+ AT91_REG BFC_MR; // BFC Mode Register
+} AT91S_BFC, *AT91PS_BFC;
+
+// -------- BFC_MR : (BFC Offset: 0x0) BFC Mode Register --------
+#define AT91C_BFC_BFCOM (0x3u << 0) // (BFC) Burst Flash Controller Operating Mode
+#define AT91C_BFC_BFCOM_DISABLED 0x0u // (BFC) NPCS0 is driven by the SMC or remains high.
+#define AT91C_BFC_BFCOM_ASYNC 0x1u // (BFC) Asynchronous
+#define AT91C_BFC_BFCOM_BURST_READ 0x2u // (BFC) Burst Read
+#define AT91C_BFC_BFCC (0x3u << 2) // (BFC) Burst Flash Controller Operating Mode
+#define AT91C_BFC_BFCC_MCK (0x1u << 2) // (BFC) Master Clock.
+#define AT91C_BFC_BFCC_MCK_DIV_2 (0x2u << 2) // (BFC) Master Clock divided by 2.
+#define AT91C_BFC_BFCC_MCK_DIV_4 (0x3u << 2) // (BFC) Master Clock divided by 4.
+#define AT91C_BFC_AVL (0xFu << 4) // (BFC) Address Valid Latency
+#define AT91C_BFC_PAGES (0x7u << 8) // (BFC) Page Size
+#define AT91C_BFC_PAGES_NO_PAGE (0x0u << 8) // (BFC) No page handling.
+#define AT91C_BFC_PAGES_16 (0x1u << 8) // (BFC) 16 bytes page size.
+#define AT91C_BFC_PAGES_32 (0x2u << 8) // (BFC) 32 bytes page size.
+#define AT91C_BFC_PAGES_64 (0x3u << 8) // (BFC) 64 bytes page size.
+#define AT91C_BFC_PAGES_128 (0x4u << 8) // (BFC) 128 bytes page size.
+#define AT91C_BFC_PAGES_256 (0x5u << 8) // (BFC) 256 bytes page size.
+#define AT91C_BFC_PAGES_512 (0x6u << 8) // (BFC) 512 bytes page size.
+#define AT91C_BFC_PAGES_1024 (0x7u << 8) // (BFC) 1024 bytes page size.
+#define AT91C_BFC_OEL (0x3u << 12) // (BFC) Output Enable Latency
+#define AT91C_BFC_BAAEN (0x1u << 16) // (BFC) Burst Address Advance Enable
+#define AT91C_BFC_BFOEH (0x1u << 17) // (BFC) Burst Flash Output Enable Handling
+#define AT91C_BFC_MUXEN (0x1u << 18) // (BFC) Multiplexed Bus Enable
+#define AT91C_BFC_RDYEN (0x1u << 19) // (BFC) Ready Enable Mode
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91RM9200
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+// ========== Register definition for MC peripheral ==========
+#define AT91C_MC_PUER ((AT91_REG *) 0xFFFFFF54) // (MC) MC Protection Unit Enable Register
+#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_PUP ((AT91_REG *) 0xFFFFFF50) // (MC) MC Protection Unit Peripherals
+#define AT91C_MC_PUIA ((AT91_REG *) 0xFFFFFF10) // (MC) MC Protection Unit Area
+#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for RTC peripheral ==========
+#define AT91C_RTC_IMR ((AT91_REG *) 0xFFFFFE28) // (RTC) Interrupt Mask Register
+#define AT91C_RTC_IER ((AT91_REG *) 0xFFFFFE20) // (RTC) Interrupt Enable Register
+#define AT91C_RTC_SR ((AT91_REG *) 0xFFFFFE18) // (RTC) Status Register
+#define AT91C_RTC_TIMALR ((AT91_REG *) 0xFFFFFE10) // (RTC) Time Alarm Register
+#define AT91C_RTC_TIMR ((AT91_REG *) 0xFFFFFE08) // (RTC) Time Register
+#define AT91C_RTC_CR ((AT91_REG *) 0xFFFFFE00) // (RTC) Control Register
+#define AT91C_RTC_VER ((AT91_REG *) 0xFFFFFE2C) // (RTC) Valid Entry Register
+#define AT91C_RTC_IDR ((AT91_REG *) 0xFFFFFE24) // (RTC) Interrupt Disable Register
+#define AT91C_RTC_SCCR ((AT91_REG *) 0xFFFFFE1C) // (RTC) Status Clear Command Register
+#define AT91C_RTC_CALALR ((AT91_REG *) 0xFFFFFE14) // (RTC) Calendar Alarm Register
+#define AT91C_RTC_CALR ((AT91_REG *) 0xFFFFFE0C) // (RTC) Calendar Register
+#define AT91C_RTC_MR ((AT91_REG *) 0xFFFFFE04) // (RTC) Mode Register
+// ========== Register definition for ST peripheral ==========
+#define AT91C_ST_CRTR ((AT91_REG *) 0xFFFFFD24) // (ST) Current Real-time Register
+#define AT91C_ST_IMR ((AT91_REG *) 0xFFFFFD1C) // (ST) Interrupt Mask Register
+#define AT91C_ST_IER ((AT91_REG *) 0xFFFFFD14) // (ST) Interrupt Enable Register
+#define AT91C_ST_RTMR ((AT91_REG *) 0xFFFFFD0C) // (ST) Real-time Mode Register
+#define AT91C_ST_PIMR ((AT91_REG *) 0xFFFFFD04) // (ST) Period Interval Mode Register
+#define AT91C_ST_RTAR ((AT91_REG *) 0xFFFFFD20) // (ST) Real-time Alarm Register
+#define AT91C_ST_IDR ((AT91_REG *) 0xFFFFFD18) // (ST) Interrupt Disable Register
+#define AT91C_ST_SR ((AT91_REG *) 0xFFFFFD10) // (ST) Status Register
+#define AT91C_ST_WDMR ((AT91_REG *) 0xFFFFFD08) // (ST) Watchdog Mode Register
+#define AT91C_ST_CR ((AT91_REG *) 0xFFFFFD00) // (ST) Control Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+#define AT91C_CKGR_PLLAR ((AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
+#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PIOD peripheral ==========
+#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) // (PIOD) Pin Data Status Register
+#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) // (PIOD) Clear Output Data Register
+#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) // (PIOD) Output Write Enable Register
+#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) // (PIOD) Multi-driver Enable Register
+#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) // (PIOD) Interrupt Mask Register
+#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) // (PIOD) Interrupt Enable Register
+#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) // (PIOD) Output Data Status Register
+#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) // (PIOD) Set Output Data Register
+#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) // (PIOD) PIO Enable Register
+#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) // (PIOD) Output Write Disable Register
+#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) // (PIOD) Pull-up Enable Register
+#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) // (PIOD) Multi-driver Disable Register
+#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) // (PIOD) Interrupt Status Register
+#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) // (PIOD) Interrupt Disable Register
+#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) // (PIOD) PIO Disable Register
+#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) // (PIOD) Output Disable Registerr
+#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) // (PIOD) Output Write Status Register
+#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) // (PIOD) AB Select Status Register
+#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) // (PIOD) Select A Register
+#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) // (PIOD) Pad Pull-up Status Register
+#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) // (PIOD) Pull-up Disable Register
+#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) // (PIOD) Multi-driver Status Register
+#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) // (PIOD) PIO Status Register
+#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) // (PIOD) Output Enable Register
+#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) // (PIOD) Output Status Register
+#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) // (PIOD) Input Filter Enable Register
+#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) // (PIOD) Select B Register
+#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) // (PIOD) Input Filter Disable Register
+#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) // (PIOD) Input Filter Status Register
+// ========== Register definition for PIOC peripheral ==========
+#define AT91C_PIOC_IFDR ((AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_ABSR ((AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_IFSR ((AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_ODSR ((AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_IER ((AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_IMR ((AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_OWDR ((AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_MDDR ((AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_IDR ((AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_ISR ((AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_OWSR ((AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_OWER ((AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
+#define AT91C_PIOC_PPUSR ((AT91_REG *) 0xFFFFF868) // (PIOC) Pad Pull-up Status Register
+#define AT91C_PIOC_PPUDR ((AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_MDSR ((AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_MDER ((AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_IFER ((AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
+#define AT91C_PIOC_OSR ((AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
+#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
+#define AT91C_PIOC_PSR ((AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
+#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
+#define AT91C_PIOC_BSR ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
+#define AT91C_PIOC_PPUER ((AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWSR ((AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 0xFFFFF668) // (PIOB) Pad Pull-up Status Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_IMR ((AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_OSR ((AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_OER ((AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PSR ((AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_ABSR ((AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_ASR ((AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_IFSR ((AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_IER ((AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_OWDR ((AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_ISR ((AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_IDR ((AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_C2R ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_SSC2 peripheral ==========
+#define AT91C_SSC2_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_SSC2) PDC Transfer Control Register
+#define AT91C_SSC2_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_SSC2) Transmit Next Pointer Register
+#define AT91C_SSC2_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_SSC2) Receive Next Pointer Register
+#define AT91C_SSC2_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_SSC2) Transmit Pointer Register
+#define AT91C_SSC2_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_SSC2) Receive Pointer Register
+#define AT91C_SSC2_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_SSC2) PDC Transfer Status Register
+#define AT91C_SSC2_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_SSC2) Transmit Next Counter Register
+#define AT91C_SSC2_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_SSC2) Receive Next Counter Register
+#define AT91C_SSC2_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_SSC2) Transmit Counter Register
+#define AT91C_SSC2_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_SSC2) Receive Counter Register
+// ========== Register definition for SSC2 peripheral ==========
+#define AT91C_SSC2_IMR ((AT91_REG *) 0xFFFD804C) // (SSC2) Interrupt Mask Register
+#define AT91C_SSC2_IER ((AT91_REG *) 0xFFFD8044) // (SSC2) Interrupt Enable Register
+#define AT91C_SSC2_RC1R ((AT91_REG *) 0xFFFD803C) // (SSC2) Receive Compare 1 Register
+#define AT91C_SSC2_TSHR ((AT91_REG *) 0xFFFD8034) // (SSC2) Transmit Sync Holding Register
+#define AT91C_SSC2_CMR ((AT91_REG *) 0xFFFD8004) // (SSC2) Clock Mode Register
+#define AT91C_SSC2_IDR ((AT91_REG *) 0xFFFD8048) // (SSC2) Interrupt Disable Register
+#define AT91C_SSC2_TCMR ((AT91_REG *) 0xFFFD8018) // (SSC2) Transmit Clock Mode Register
+#define AT91C_SSC2_RCMR ((AT91_REG *) 0xFFFD8010) // (SSC2) Receive Clock ModeRegister
+#define AT91C_SSC2_CR ((AT91_REG *) 0xFFFD8000) // (SSC2) Control Register
+#define AT91C_SSC2_RFMR ((AT91_REG *) 0xFFFD8014) // (SSC2) Receive Frame Mode Register
+#define AT91C_SSC2_TFMR ((AT91_REG *) 0xFFFD801C) // (SSC2) Transmit Frame Mode Register
+#define AT91C_SSC2_THR ((AT91_REG *) 0xFFFD8024) // (SSC2) Transmit Holding Register
+#define AT91C_SSC2_SR ((AT91_REG *) 0xFFFD8040) // (SSC2) Status Register
+#define AT91C_SSC2_RC0R ((AT91_REG *) 0xFFFD8038) // (SSC2) Receive Compare 0 Register
+#define AT91C_SSC2_RSHR ((AT91_REG *) 0xFFFD8030) // (SSC2) Receive Sync Holding Register
+#define AT91C_SSC2_RHR ((AT91_REG *) 0xFFFD8020) // (SSC2) Receive Holding Register
+// ========== Register definition for PDC_SSC1 peripheral ==========
+#define AT91C_SSC1_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC1) PDC Transfer Control Register
+#define AT91C_SSC1_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC1) Transmit Next Pointer Register
+#define AT91C_SSC1_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC1) Receive Next Pointer Register
+#define AT91C_SSC1_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC1) Transmit Pointer Register
+#define AT91C_SSC1_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC1) Receive Pointer Register
+#define AT91C_SSC1_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC1) PDC Transfer Status Register
+#define AT91C_SSC1_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC1) Transmit Next Counter Register
+#define AT91C_SSC1_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC1) Receive Next Counter Register
+#define AT91C_SSC1_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC1) Transmit Counter Register
+#define AT91C_SSC1_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC1) Receive Counter Register
+// ========== Register definition for SSC1 peripheral ==========
+#define AT91C_SSC1_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC1) Receive Frame Mode Register
+#define AT91C_SSC1_CMR ((AT91_REG *) 0xFFFD4004) // (SSC1) Clock Mode Register
+#define AT91C_SSC1_IDR ((AT91_REG *) 0xFFFD4048) // (SSC1) Interrupt Disable Register
+#define AT91C_SSC1_SR ((AT91_REG *) 0xFFFD4040) // (SSC1) Status Register
+#define AT91C_SSC1_RC0R ((AT91_REG *) 0xFFFD4038) // (SSC1) Receive Compare 0 Register
+#define AT91C_SSC1_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC1) Receive Sync Holding Register
+#define AT91C_SSC1_RHR ((AT91_REG *) 0xFFFD4020) // (SSC1) Receive Holding Register
+#define AT91C_SSC1_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC1) Transmit Clock Mode Register
+#define AT91C_SSC1_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC1) Receive Clock ModeRegister
+#define AT91C_SSC1_CR ((AT91_REG *) 0xFFFD4000) // (SSC1) Control Register
+#define AT91C_SSC1_IMR ((AT91_REG *) 0xFFFD404C) // (SSC1) Interrupt Mask Register
+#define AT91C_SSC1_IER ((AT91_REG *) 0xFFFD4044) // (SSC1) Interrupt Enable Register
+#define AT91C_SSC1_RC1R ((AT91_REG *) 0xFFFD403C) // (SSC1) Receive Compare 1 Register
+#define AT91C_SSC1_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC1) Transmit Sync Holding Register
+#define AT91C_SSC1_THR ((AT91_REG *) 0xFFFD4024) // (SSC1) Transmit Holding Register
+#define AT91C_SSC1_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC1) Transmit Frame Mode Register
+// ========== Register definition for PDC_SSC0 peripheral ==========
+#define AT91C_SSC0_PTCR ((AT91_REG *) 0xFFFD0120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_TNPR ((AT91_REG *) 0xFFFD0118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_RNPR ((AT91_REG *) 0xFFFD0110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_TPR ((AT91_REG *) 0xFFFD0108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RPR ((AT91_REG *) 0xFFFD0100) // (PDC_SSC0) Receive Pointer Register
+#define AT91C_SSC0_PTSR ((AT91_REG *) 0xFFFD0124) // (PDC_SSC0) PDC Transfer Status Register
+#define AT91C_SSC0_TNCR ((AT91_REG *) 0xFFFD011C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_RNCR ((AT91_REG *) 0xFFFD0114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_TCR ((AT91_REG *) 0xFFFD010C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RCR ((AT91_REG *) 0xFFFD0104) // (PDC_SSC0) Receive Counter Register
+// ========== Register definition for SSC0 peripheral ==========
+#define AT91C_SSC0_IMR ((AT91_REG *) 0xFFFD004C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_IER ((AT91_REG *) 0xFFFD0044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_RC1R ((AT91_REG *) 0xFFFD003C) // (SSC0) Receive Compare 1 Register
+#define AT91C_SSC0_TSHR ((AT91_REG *) 0xFFFD0034) // (SSC0) Transmit Sync Holding Register
+#define AT91C_SSC0_THR ((AT91_REG *) 0xFFFD0024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_TFMR ((AT91_REG *) 0xFFFD001C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_RFMR ((AT91_REG *) 0xFFFD0014) // (SSC0) Receive Frame Mode Register
+#define AT91C_SSC0_CMR ((AT91_REG *) 0xFFFD0004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_IDR ((AT91_REG *) 0xFFFD0048) // (SSC0) Interrupt Disable Register
+#define AT91C_SSC0_SR ((AT91_REG *) 0xFFFD0040) // (SSC0) Status Register
+#define AT91C_SSC0_RC0R ((AT91_REG *) 0xFFFD0038) // (SSC0) Receive Compare 0 Register
+#define AT91C_SSC0_RSHR ((AT91_REG *) 0xFFFD0030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_RHR ((AT91_REG *) 0xFFFD0020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_TCMR ((AT91_REG *) 0xFFFD0018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_RCMR ((AT91_REG *) 0xFFFD0010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_CR ((AT91_REG *) 0xFFFD0000) // (SSC0) Control Register
+// ========== Register definition for PDC_US3 peripheral ==========
+#define AT91C_US3_PTSR ((AT91_REG *) 0xFFFCC124) // (PDC_US3) PDC Transfer Status Register
+#define AT91C_US3_TNCR ((AT91_REG *) 0xFFFCC11C) // (PDC_US3) Transmit Next Counter Register
+#define AT91C_US3_RNCR ((AT91_REG *) 0xFFFCC114) // (PDC_US3) Receive Next Counter Register
+#define AT91C_US3_TCR ((AT91_REG *) 0xFFFCC10C) // (PDC_US3) Transmit Counter Register
+#define AT91C_US3_RCR ((AT91_REG *) 0xFFFCC104) // (PDC_US3) Receive Counter Register
+#define AT91C_US3_PTCR ((AT91_REG *) 0xFFFCC120) // (PDC_US3) PDC Transfer Control Register
+#define AT91C_US3_TNPR ((AT91_REG *) 0xFFFCC118) // (PDC_US3) Transmit Next Pointer Register
+#define AT91C_US3_RNPR ((AT91_REG *) 0xFFFCC110) // (PDC_US3) Receive Next Pointer Register
+#define AT91C_US3_TPR ((AT91_REG *) 0xFFFCC108) // (PDC_US3) Transmit Pointer Register
+#define AT91C_US3_RPR ((AT91_REG *) 0xFFFCC100) // (PDC_US3) Receive Pointer Register
+// ========== Register definition for US3 peripheral ==========
+#define AT91C_US3_IF ((AT91_REG *) 0xFFFCC04C) // (US3) IRDA_FILTER Register
+#define AT91C_US3_NER ((AT91_REG *) 0xFFFCC044) // (US3) Nb Errors Register
+#define AT91C_US3_RTOR ((AT91_REG *) 0xFFFCC024) // (US3) Receiver Time-out Register
+#define AT91C_US3_THR ((AT91_REG *) 0xFFFCC01C) // (US3) Transmitter Holding Register
+#define AT91C_US3_CSR ((AT91_REG *) 0xFFFCC014) // (US3) Channel Status Register
+#define AT91C_US3_IDR ((AT91_REG *) 0xFFFCC00C) // (US3) Interrupt Disable Register
+#define AT91C_US3_MR ((AT91_REG *) 0xFFFCC004) // (US3) Mode Register
+#define AT91C_US3_XXR ((AT91_REG *) 0xFFFCC048) // (US3) XON_XOFF Register
+#define AT91C_US3_FIDI ((AT91_REG *) 0xFFFCC040) // (US3) FI_DI_Ratio Register
+#define AT91C_US3_TTGR ((AT91_REG *) 0xFFFCC028) // (US3) Transmitter Time-guard Register
+#define AT91C_US3_BRGR ((AT91_REG *) 0xFFFCC020) // (US3) Baud Rate Generator Register
+#define AT91C_US3_RHR ((AT91_REG *) 0xFFFCC018) // (US3) Receiver Holding Register
+#define AT91C_US3_IMR ((AT91_REG *) 0xFFFCC010) // (US3) Interrupt Mask Register
+#define AT91C_US3_IER ((AT91_REG *) 0xFFFCC008) // (US3) Interrupt Enable Register
+#define AT91C_US3_CR ((AT91_REG *) 0xFFFCC000) // (US3) Control Register
+// ========== Register definition for PDC_US2 peripheral ==========
+#define AT91C_US2_PTSR ((AT91_REG *) 0xFFFC8124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_TNCR ((AT91_REG *) 0xFFFC811C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_RNCR ((AT91_REG *) 0xFFFC8114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_TCR ((AT91_REG *) 0xFFFC810C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_PTCR ((AT91_REG *) 0xFFFC8120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_RCR ((AT91_REG *) 0xFFFC8104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_TNPR ((AT91_REG *) 0xFFFC8118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_RPR ((AT91_REG *) 0xFFFC8100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_TPR ((AT91_REG *) 0xFFFC8108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RNPR ((AT91_REG *) 0xFFFC8110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ==========
+#define AT91C_US2_XXR ((AT91_REG *) 0xFFFC8048) // (US2) XON_XOFF Register
+#define AT91C_US2_FIDI ((AT91_REG *) 0xFFFC8040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_TTGR ((AT91_REG *) 0xFFFC8028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_BRGR ((AT91_REG *) 0xFFFC8020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_RHR ((AT91_REG *) 0xFFFC8018) // (US2) Receiver Holding Register
+#define AT91C_US2_IMR ((AT91_REG *) 0xFFFC8010) // (US2) Interrupt Mask Register
+#define AT91C_US2_IER ((AT91_REG *) 0xFFFC8008) // (US2) Interrupt Enable Register
+#define AT91C_US2_CR ((AT91_REG *) 0xFFFC8000) // (US2) Control Register
+#define AT91C_US2_IF ((AT91_REG *) 0xFFFC804C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_NER ((AT91_REG *) 0xFFFC8044) // (US2) Nb Errors Register
+#define AT91C_US2_RTOR ((AT91_REG *) 0xFFFC8024) // (US2) Receiver Time-out Register
+#define AT91C_US2_THR ((AT91_REG *) 0xFFFC801C) // (US2) Transmitter Holding Register
+#define AT91C_US2_CSR ((AT91_REG *) 0xFFFC8014) // (US2) Channel Status Register
+#define AT91C_US2_IDR ((AT91_REG *) 0xFFFC800C) // (US2) Interrupt Disable Register
+#define AT91C_US2_MR ((AT91_REG *) 0xFFFC8004) // (US2) Mode Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_XXR ((AT91_REG *) 0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR ((AT91_REG *) 0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR ((AT91_REG *) 0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for PDC_MCI peripheral ==========
+#define AT91C_MCI_PTCR ((AT91_REG *) 0xFFFB4120) // (PDC_MCI) PDC Transfer Control Register
+#define AT91C_MCI_TNPR ((AT91_REG *) 0xFFFB4118) // (PDC_MCI) Transmit Next Pointer Register
+#define AT91C_MCI_RNPR ((AT91_REG *) 0xFFFB4110) // (PDC_MCI) Receive Next Pointer Register
+#define AT91C_MCI_TPR ((AT91_REG *) 0xFFFB4108) // (PDC_MCI) Transmit Pointer Register
+#define AT91C_MCI_RPR ((AT91_REG *) 0xFFFB4100) // (PDC_MCI) Receive Pointer Register
+#define AT91C_MCI_PTSR ((AT91_REG *) 0xFFFB4124) // (PDC_MCI) PDC Transfer Status Register
+#define AT91C_MCI_TNCR ((AT91_REG *) 0xFFFB411C) // (PDC_MCI) Transmit Next Counter Register
+#define AT91C_MCI_RNCR ((AT91_REG *) 0xFFFB4114) // (PDC_MCI) Receive Next Counter Register
+#define AT91C_MCI_TCR ((AT91_REG *) 0xFFFB410C) // (PDC_MCI) Transmit Counter Register
+#define AT91C_MCI_RCR ((AT91_REG *) 0xFFFB4104) // (PDC_MCI) Receive Counter Register
+// ========== Register definition for MCI peripheral ==========
+#define AT91C_MCI_IDR ((AT91_REG *) 0xFFFB4048) // (MCI) MCI Interrupt Disable Register
+#define AT91C_MCI_SR ((AT91_REG *) 0xFFFB4040) // (MCI) MCI Status Register
+#define AT91C_MCI_RDR ((AT91_REG *) 0xFFFB4030) // (MCI) MCI Receive Data Register
+#define AT91C_MCI_RSPR ((AT91_REG *) 0xFFFB4020) // (MCI) MCI Response Register
+#define AT91C_MCI_ARGR ((AT91_REG *) 0xFFFB4010) // (MCI) MCI Argument Register
+#define AT91C_MCI_DTOR ((AT91_REG *) 0xFFFB4008) // (MCI) MCI Data Timeout Register
+#define AT91C_MCI_CR ((AT91_REG *) 0xFFFB4000) // (MCI) MCI Control Register
+#define AT91C_MCI_IMR ((AT91_REG *) 0xFFFB404C) // (MCI) MCI Interrupt Mask Register
+#define AT91C_MCI_IER ((AT91_REG *) 0xFFFB4044) // (MCI) MCI Interrupt Enable Register
+#define AT91C_MCI_TDR ((AT91_REG *) 0xFFFB4034) // (MCI) MCI Transmit Data Register
+#define AT91C_MCI_CMDR ((AT91_REG *) 0xFFFB4014) // (MCI) MCI Command Register
+#define AT91C_MCI_SDCR ((AT91_REG *) 0xFFFB400C) // (MCI) MCI SD Card Register
+#define AT91C_MCI_MR ((AT91_REG *) 0xFFFB4004) // (MCI) MCI Mode Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register
+// ========== Register definition for TC5 peripheral ==========
+#define AT91C_TC5_CMR ((AT91_REG *) 0xFFFA4084) // (TC5) Channel Mode Register
+#define AT91C_TC5_IDR ((AT91_REG *) 0xFFFA40A8) // (TC5) Interrupt Disable Register
+#define AT91C_TC5_SR ((AT91_REG *) 0xFFFA40A0) // (TC5) Status Register
+#define AT91C_TC5_RB ((AT91_REG *) 0xFFFA4098) // (TC5) Register B
+#define AT91C_TC5_CV ((AT91_REG *) 0xFFFA4090) // (TC5) Counter Value
+#define AT91C_TC5_CCR ((AT91_REG *) 0xFFFA4080) // (TC5) Channel Control Register
+#define AT91C_TC5_IMR ((AT91_REG *) 0xFFFA40AC) // (TC5) Interrupt Mask Register
+#define AT91C_TC5_IER ((AT91_REG *) 0xFFFA40A4) // (TC5) Interrupt Enable Register
+#define AT91C_TC5_RC ((AT91_REG *) 0xFFFA409C) // (TC5) Register C
+#define AT91C_TC5_RA ((AT91_REG *) 0xFFFA4094) // (TC5) Register A
+// ========== Register definition for TC4 peripheral ==========
+#define AT91C_TC4_IMR ((AT91_REG *) 0xFFFA406C) // (TC4) Interrupt Mask Register
+#define AT91C_TC4_IER ((AT91_REG *) 0xFFFA4064) // (TC4) Interrupt Enable Register
+#define AT91C_TC4_RC ((AT91_REG *) 0xFFFA405C) // (TC4) Register C
+#define AT91C_TC4_RA ((AT91_REG *) 0xFFFA4054) // (TC4) Register A
+#define AT91C_TC4_CMR ((AT91_REG *) 0xFFFA4044) // (TC4) Channel Mode Register
+#define AT91C_TC4_IDR ((AT91_REG *) 0xFFFA4068) // (TC4) Interrupt Disable Register
+#define AT91C_TC4_SR ((AT91_REG *) 0xFFFA4060) // (TC4) Status Register
+#define AT91C_TC4_RB ((AT91_REG *) 0xFFFA4058) // (TC4) Register B
+#define AT91C_TC4_CV ((AT91_REG *) 0xFFFA4050) // (TC4) Counter Value
+#define AT91C_TC4_CCR ((AT91_REG *) 0xFFFA4040) // (TC4) Channel Control Register
+// ========== Register definition for TC3 peripheral ==========
+#define AT91C_TC3_IMR ((AT91_REG *) 0xFFFA402C) // (TC3) Interrupt Mask Register
+#define AT91C_TC3_CV ((AT91_REG *) 0xFFFA4010) // (TC3) Counter Value
+#define AT91C_TC3_CCR ((AT91_REG *) 0xFFFA4000) // (TC3) Channel Control Register
+#define AT91C_TC3_IER ((AT91_REG *) 0xFFFA4024) // (TC3) Interrupt Enable Register
+#define AT91C_TC3_CMR ((AT91_REG *) 0xFFFA4004) // (TC3) Channel Mode Register
+#define AT91C_TC3_RA ((AT91_REG *) 0xFFFA4014) // (TC3) Register A
+#define AT91C_TC3_RC ((AT91_REG *) 0xFFFA401C) // (TC3) Register C
+#define AT91C_TC3_IDR ((AT91_REG *) 0xFFFA4028) // (TC3) Interrupt Disable Register
+#define AT91C_TC3_RB ((AT91_REG *) 0xFFFA4018) // (TC3) Register B
+#define AT91C_TC3_SR ((AT91_REG *) 0xFFFA4020) // (TC3) Status Register
+// ========== Register definition for TCB1 peripheral ==========
+#define AT91C_TCB1_BCR ((AT91_REG *) 0xFFFA4140) // (TCB1) TC Block Control Register
+#define AT91C_TCB1_BMR ((AT91_REG *) 0xFFFA4144) // (TCB1) TC Block Mode Register
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register
+#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register
+#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register
+#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB0 peripheral ==========
+#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
+// ========== Register definition for UHP peripheral ==========
+#define AT91C_UHP_HcRhDescriptorA ((AT91_REG *) 0x00300048) // (UHP) Root Hub characteristics A
+#define AT91C_UHP_HcRhPortStatus ((AT91_REG *) 0x00300054) // (UHP) Root Hub Port Status Register
+#define AT91C_UHP_HcRhDescriptorB ((AT91_REG *) 0x0030004C) // (UHP) Root Hub characteristics B
+#define AT91C_UHP_HcControl ((AT91_REG *) 0x00300004) // (UHP) Operating modes for the Host Controller
+#define AT91C_UHP_HcInterruptStatus ((AT91_REG *) 0x0030000C) // (UHP) Interrupt Status Register
+#define AT91C_UHP_HcRhStatus ((AT91_REG *) 0x00300050) // (UHP) Root Hub Status register
+#define AT91C_UHP_HcRevision ((AT91_REG *) 0x00300000) // (UHP) Revision
+#define AT91C_UHP_HcCommandStatus ((AT91_REG *) 0x00300008) // (UHP) Command & status Register
+#define AT91C_UHP_HcInterruptEnable ((AT91_REG *) 0x00300010) // (UHP) Interrupt Enable Register
+#define AT91C_UHP_HcHCCA ((AT91_REG *) 0x00300018) // (UHP) Pointer to the Host Controller Communication Area
+#define AT91C_UHP_HcControlHeadED ((AT91_REG *) 0x00300020) // (UHP) First Endpoint Descriptor of the Control list
+#define AT91C_UHP_HcInterruptDisable ((AT91_REG *) 0x00300014) // (UHP) Interrupt Disable Register
+#define AT91C_UHP_HcPeriodCurrentED ((AT91_REG *) 0x0030001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_UHP_HcControlCurrentED ((AT91_REG *) 0x00300024) // (UHP) Endpoint Control and Status Register
+#define AT91C_UHP_HcBulkCurrentED ((AT91_REG *) 0x0030002C) // (UHP) Current endpoint of the Bulk list
+#define AT91C_UHP_HcFmInterval ((AT91_REG *) 0x00300034) // (UHP) Bit time between 2 consecutive SOFs
+#define AT91C_UHP_HcBulkHeadED ((AT91_REG *) 0x00300028) // (UHP) First endpoint register of the Bulk list
+#define AT91C_UHP_HcBulkDoneHead ((AT91_REG *) 0x00300030) // (UHP) Last completed transfer descriptor
+#define AT91C_UHP_HcFmRemaining ((AT91_REG *) 0x00300038) // (UHP) Bit time remaining in the current Frame
+#define AT91C_UHP_HcPeriodicStart ((AT91_REG *) 0x00300040) // (UHP) Periodic Start
+#define AT91C_UHP_HcLSThreshold ((AT91_REG *) 0x00300044) // (UHP) LS Threshold
+#define AT91C_UHP_HcFmNumber ((AT91_REG *) 0x0030003C) // (UHP) Frame number
+// ========== Register definition for EMAC peripheral ==========
+#define AT91C_EMAC_RSR ((AT91_REG *) 0xFFFBC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_MAN ((AT91_REG *) 0xFFFBC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_HSH ((AT91_REG *) 0xFFFBC090) // (EMAC) Hash Address High[63:32]
+#define AT91C_EMAC_MCOL ((AT91_REG *) 0xFFFBC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_IER ((AT91_REG *) 0xFFFBC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 0xFFFBC0A4) // (EMAC) Specific Address 2 High, Last 2 bytes
+#define AT91C_EMAC_HSL ((AT91_REG *) 0xFFFBC094) // (EMAC) Hash Address Low[31:0]
+#define AT91C_EMAC_LCOL ((AT91_REG *) 0xFFFBC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_OK ((AT91_REG *) 0xFFFBC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_CFG ((AT91_REG *) 0xFFFBC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 0xFFFBC0A8) // (EMAC) Specific Address 3 Low, First 4 bytes
+#define AT91C_EMAC_SEQE ((AT91_REG *) 0xFFFBC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 0xFFFBC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_ELR ((AT91_REG *) 0xFFFBC070) // (EMAC) Excessive Length Error Register
+#define AT91C_EMAC_SR ((AT91_REG *) 0xFFFBC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 0xFFFBC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_CSE ((AT91_REG *) 0xFFFBC064) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_RJB ((AT91_REG *) 0xFFFBC074) // (EMAC) Receive Jabber Register
+#define AT91C_EMAC_USF ((AT91_REG *) 0xFFFBC078) // (EMAC) Undersize Frame Register
+#define AT91C_EMAC_IDR ((AT91_REG *) 0xFFFBC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_SA1L ((AT91_REG *) 0xFFFBC098) // (EMAC) Specific Address 1 Low, First 4 bytes
+#define AT91C_EMAC_IMR ((AT91_REG *) 0xFFFBC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_FRA ((AT91_REG *) 0xFFFBC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 0xFFFBC0AC) // (EMAC) Specific Address 3 High, Last 2 bytes
+#define AT91C_EMAC_SA1H ((AT91_REG *) 0xFFFBC09C) // (EMAC) Specific Address 1 High, Last 2 bytes
+#define AT91C_EMAC_SCOL ((AT91_REG *) 0xFFFBC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_ALE ((AT91_REG *) 0xFFFBC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_TAR ((AT91_REG *) 0xFFFBC00C) // (EMAC) Transmit Address Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 0xFFFBC0B0) // (EMAC) Specific Address 4 Low, First 4 bytes
+#define AT91C_EMAC_SA2L ((AT91_REG *) 0xFFFBC0A0) // (EMAC) Specific Address 2 Low, First 4 bytes
+#define AT91C_EMAC_TUE ((AT91_REG *) 0xFFFBC068) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_DTE ((AT91_REG *) 0xFFFBC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TCR ((AT91_REG *) 0xFFFBC010) // (EMAC) Transmit Control Register
+#define AT91C_EMAC_CTL ((AT91_REG *) 0xFFFBC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 0xFFFBC0B4) // (EMAC) Specific Address 4 High, Last 2 bytesr
+#define AT91C_EMAC_CDE ((AT91_REG *) 0xFFFBC06C) // (EMAC) Code Error Register
+#define AT91C_EMAC_SQEE ((AT91_REG *) 0xFFFBC07C) // (EMAC) SQE Test Error Register
+#define AT91C_EMAC_TSR ((AT91_REG *) 0xFFFBC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_DRFC ((AT91_REG *) 0xFFFBC080) // (EMAC) Discarded RX Frame Register
+// ========== Register definition for EBI peripheral ==========
+#define AT91C_EBI_CFGR ((AT91_REG *) 0xFFFFFF64) // (EBI) Configuration Register
+#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) // (EBI) Chip Select Assignment Register
+// ========== Register definition for SMC2 peripheral ==========
+#define AT91C_SMC2_CSR ((AT91_REG *) 0xFFFFFF70) // (SMC2) SMC2 Chip Select Register
+// ========== Register definition for SDRC peripheral ==========
+#define AT91C_SDRC_IMR ((AT91_REG *) 0xFFFFFFAC) // (SDRC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRC_IER ((AT91_REG *) 0xFFFFFFA4) // (SDRC) SDRAM Controller Interrupt Enable Register
+#define AT91C_SDRC_SRR ((AT91_REG *) 0xFFFFFF9C) // (SDRC) SDRAM Controller Self Refresh Register
+#define AT91C_SDRC_TR ((AT91_REG *) 0xFFFFFF94) // (SDRC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRC_ISR ((AT91_REG *) 0xFFFFFFB0) // (SDRC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRC_IDR ((AT91_REG *) 0xFFFFFFA8) // (SDRC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRC_LPR ((AT91_REG *) 0xFFFFFFA0) // (SDRC) SDRAM Controller Low Power Register
+#define AT91C_SDRC_CR ((AT91_REG *) 0xFFFFFF98) // (SDRC) SDRAM Controller Configuration Register
+#define AT91C_SDRC_MR ((AT91_REG *) 0xFFFFFF90) // (SDRC) SDRAM Controller Mode Register
+// ========== Register definition for BFC peripheral ==========
+#define AT91C_BFC_MR ((AT91_REG *) 0xFFFFFFC0) // (BFC) BFC Mode Register
+
+#include <at91/at91_pio_rm9200.h>
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_ID_FIQ 0u // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS 1u // System Peripheral
+#define AT91C_ID_PIOA 2u // Parallel IO Controller A
+#define AT91C_ID_PIOB 3u // Parallel IO Controller B
+#define AT91C_ID_PIOC 4u // Parallel IO Controller C
+#define AT91C_ID_PIOD 5u // Parallel IO Controller D
+#define AT91C_ID_US0 6u // USART 0
+#define AT91C_ID_US1 7u // USART 1
+#define AT91C_ID_US2 8u // USART 2
+#define AT91C_ID_US3 9u // USART 3
+#define AT91C_ID_MCI 10u // Multimedia Card Interface
+#define AT91C_ID_UDP 11u // USB Device Port
+#define AT91C_ID_TWI 12u // Two-Wire Interface
+#define AT91C_ID_SPI 13u // Serial Peripheral Interface
+#define AT91C_ID_SSC0 14u // Serial Synchronous Controller 0
+#define AT91C_ID_SSC1 15u // Serial Synchronous Controller 1
+#define AT91C_ID_SSC2 16u // Serial Synchronous Controller 2
+#define AT91C_ID_TC0 17u // Timer Counter 0
+#define AT91C_ID_TC1 18u // Timer Counter 1
+#define AT91C_ID_TC2 19u // Timer Counter 2
+#define AT91C_ID_TC3 20u // Timer Counter 3
+#define AT91C_ID_TC4 21u // Timer Counter 4
+#define AT91C_ID_TC5 22u // Timer Counter 5
+#define AT91C_ID_UHP 23u // USB Host port
+#define AT91C_ID_EMAC 24u // Ethernet MAC
+#define AT91C_ID_IRQ0 25u // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 26u // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2 27u // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ID_IRQ3 28u // Advanced Interrupt Controller (IRQ3)
+#define AT91C_ID_IRQ4 29u // Advanced Interrupt Controller (IRQ4)
+#define AT91C_ID_IRQ5 30u // Advanced Interrupt Controller (IRQ5)
+#define AT91C_ID_IRQ6 31u // Advanced Interrupt Controller (IRQ6)
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) // (RTC) Base Address
+#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) // (ST) Base Address
+#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) // (PIOD) Base Address
+#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
+#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_SSC2 ((AT91PS_PDC) 0xFFFD8100) // (PDC_SSC2) Base Address
+#define AT91C_BASE_SSC2 ((AT91PS_SSC) 0xFFFD8000) // (SSC2) Base Address
+#define AT91C_BASE_PDC_SSC1 ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC1) Base Address
+#define AT91C_BASE_SSC1 ((AT91PS_SSC) 0xFFFD4000) // (SSC1) Base Address
+#define AT91C_BASE_PDC_SSC0 ((AT91PS_PDC) 0xFFFD0100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0 ((AT91PS_SSC) 0xFFFD0000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_US3 ((AT91PS_PDC) 0xFFFCC100) // (PDC_US3) Base Address
+#define AT91C_BASE_US3 ((AT91PS_USART) 0xFFFCC000) // (US3) Base Address
+#define AT91C_BASE_PDC_US2 ((AT91PS_PDC) 0xFFFC8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2 ((AT91PS_USART) 0xFFFC8000) // (US2) Base Address
+#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PDC_MCI ((AT91PS_PDC) 0xFFFB4100) // (PDC_MCI) Base Address
+#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) // (MCI) Base Address
+#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC5 ((AT91PS_TC) 0xFFFA4080) // (TC5) Base Address
+#define AT91C_BASE_TC4 ((AT91PS_TC) 0xFFFA4040) // (TC4) Base Address
+#define AT91C_BASE_TC3 ((AT91PS_TC) 0xFFFA4000) // (TC3) Base Address
+#define AT91C_BASE_TCB1 ((AT91PS_TCB) 0xFFFA4080) // (TCB1) Base Address
+#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
+#define AT91C_BASE_UHP ((AT91PS_UHP) 0x00300000) // (UHP) Base Address
+#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) // (EMAC) Base Address
+#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFFFFF60) // (EBI) Base Address
+#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) // (SMC2) Base Address
+#define AT91C_BASE_SDRC ((AT91PS_SDRC) 0xFFFFFF90) // (SDRC) Base Address
+#define AT91C_BASE_BFC ((AT91PS_BFC) 0xFFFFFFC0) // (BFC) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91RM9200
+// *****************************************************************************
+#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE 0x00004000u // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IROM ((char *) 0x00100000) // Internal ROM base address
+#define AT91C_IROM_SIZE 0x00020000u // Internal ROM size in byte (128 Kbyte)
+
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/at91rm9200.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
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Added: trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,224 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+
+extern int __bss_start__[];
+extern int __bss_end__[];
+
+#define BAUD 115200
+#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \
+ AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK)
+
+/*
+ * void DefaultSystemInit(void)
+ * Load the system with sane values based on how the system is configured.
+ * at91rm9200_lowlevel.h is expected to define the necessary parameters.
+ */
+void
+_init(void)
+{
+ int *i;
+
+ AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
+ AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
+
+ register unsigned value;
+ volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE;
+
+ AT91C_BASE_ST->ST_RTMR = 1;
+#ifdef BOOT_TSC
+ // For the TSC board, we turn ON the one LED we have while
+ // early in boot.
+ AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10;
+ AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10;
+ AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10;
+#endif
+
+#if defined(BOOT_KB920X)
+ AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
+ AT91C_PIO_PC20;
+ AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
+ AT91C_PIO_PC20;
+ AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
+ AT91C_PIO_PC20;
+ AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC18;
+#endif
+
+ // configure clocks
+ // assume:
+ // main osc = 10Mhz
+ // PLLB configured for 96MHz (48MHz after div)
+ // CSS = PLLB
+ // set PLLA = 180MHz
+ // assume main osc = 10Mhz
+ // div = 5 , out = 2 (150MHz = 240MHz)
+ value = AT91C_BASE_CKGR->CKGR_PLLAR;
+ value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA);
+ value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA |
+ ((OSC_MAIN_MULT - 1) << 16);
+ AT91C_BASE_CKGR->CKGR_PLLAR = value;
+
+ // wait for lock
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA))
+ continue;
+
+ // change divider = 3, pres = 1
+ value = AT91C_BASE_PMC->PMC_MCKR;
+ value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES);
+ value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK;
+ AT91C_BASE_PMC->PMC_MCKR = value;
+
+ // wait for update
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
+ continue;
+
+ // change CSS = PLLA
+ value &= ~AT91C_PMC_CSS;
+ value |= AT91C_PMC_CSS_PLLA_CLK;
+ AT91C_BASE_PMC->PMC_MCKR = value;
+
+ // wait for update
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
+ continue;
+
+#ifdef BOOT_KB920X
+ // setup flash access (allow ample margin)
+ // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
+ ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] =
+ AT91C_SMC2_WSEN |
+ (9 & AT91C_SMC2_NWS) |
+ ((1 << 8) & AT91C_SMC2_TDF) |
+ AT91C_SMC2_DBW_8 |
+ ((1 << 24) & AT91C_SMC2_RWSETUP) |
+ ((1 << 29) & AT91C_SMC2_RWHOLD);
+#endif
+
+ // setup SDRAM access
+ // EBI chip-select register (CS1 = SDRAM controller)
+ // 9 col, 13row, 4 bank, CAS2
+ // write recovery = 2 (Twr)
+ // row cycle = 5 (Trc)
+ // precharge delay = 2 (Trp)
+ // row to col delay 2 (Trcd)
+ // active to precharge = 4 (Tras)
+ // exit self refresh to active = 6 (Txsr)
+ value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA;
+ value &= ~AT91C_EBI_CS1A;
+ value |= AT91C_EBI_CS1A_SDRAMC;
+ AT91C_BASE_EBI->EBI_CSA = value;
+
+ AT91C_BASE_SDRC->SDRC_CR =
+#if defined(KB9202_B) || defined(SDRAM_128M)
+ AT91C_SDRC_NC_10 |
+#else
+ AT91C_SDRC_NC_9 |
+#endif
+ AT91C_SDRC_NR_13 |
+ AT91C_SDRC_NB_4_BANKS |
+ AT91C_SDRC_CAS_2 |
+ ((2 << 7) & AT91C_SDRC_TWR) |
+ ((5 << 11) & AT91C_SDRC_TRC) |
+ ((2 << 15) & AT91C_SDRC_TRP) |
+ ((2 << 19) & AT91C_SDRC_TRCD) |
+ ((4 << 23) & AT91C_SDRC_TRAS) |
+ ((6 << 27) & AT91C_SDRC_TXSR);
+
+ // Step 1: We assume 200us of idle time.
+ // Step 2: Issue an all banks precharge command
+ AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD;
+ *p = 0;
+
+ // Step 3: Issue 8 Auto-refresh (CBR) cycles
+ AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+ *p = 0;
+
+ // Step 4: Issue an Mode Set Register (MRS) cycle to program in
+ // the parameters that we setup in the SDRC_CR register above.
+ AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD;
+ *p = 0;
+
+ // Step 5: set the refresh timer and access memory to start it
+ // running. We have to wait 3 clocks after the LMR_CMD above,
+ // and this fits the bill nicely.
+ AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000;
+ *p = 0;
+
+ // Step 6: Set normal mode.
+ AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD;
+ *p = 0;
+
+#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS
+ // Turn on the upper 16 bits on the SDRAM bus.
+ AT91C_BASE_PIOC->PIO_ASR = 0xffff0000;
+ AT91C_BASE_PIOC->PIO_PDR = 0xffff0000;
+#endif
+ // Configure DBGU -use local routine optimized for space
+ AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
+ AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
+ pUSART->US_IDR = (unsigned int) -1;
+ pUSART->US_CR =
+ AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
+ pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10);
+ pUSART->US_TTGR = 0;
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+ pPDC->PDC_TNPR = 0;
+ pPDC->PDC_TNCR = 0;
+
+ pPDC->PDC_RNPR = 0;
+ pPDC->PDC_RNCR = 0;
+
+ pPDC->PDC_TPR = 0;
+ pPDC->PDC_TCR = 0;
+
+ pPDC->PDC_RPR = 0;
+ pPDC->PDC_RCR = 0;
+
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+
+ pUSART->US_MR = AT91C_US_ASYNC_MODE;
+ pUSART->US_CR = AT91C_US_TXEN;
+ pUSART->US_CR = AT91C_US_RXEN;
+
+ /* Zero BSS now that we have memory setup */
+ i = (int *)__bss_start__;
+ while (i < (int *)__bss_end__)
+ *i++ = 0;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.c
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Added: trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,75 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _AT91RM9200_LOWLEVEL_H_
+#define _AT91RM9200_LOWLEVEL_H_
+
+/* default system config parameters */
+
+#define SDRAM_BASE 0x20000000
+
+#ifdef BOOT_KB920X
+/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
+#define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */
+#define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS
+typedef unsigned short sdram_size_t;
+#define OSC_MAIN_MULT 90
+#endif
+
+#ifdef BOOT_CENTIPAD
+/* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */
+#define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */
+#define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS
+typedef unsigned short sdram_size_t;
+#define OSC_MAIN_MULT 90
+#endif
+
+#ifdef BOOT_BWCT
+/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
+#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */
+#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS
+typedef unsigned int sdram_size_t;
+#define OSC_MAIN_MULT 45
+#endif
+
+#ifdef BOOT_TSC
+/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */
+#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */
+#define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS
+typedef unsigned int sdram_size_t;
+#define OSC_MAIN_MULT 45
+#endif
+
+/* Master clock frequency at power-up */
+#define AT91C_MASTER_CLOCK 60000000
+
+/* #define GetSeconds() (AT91C_BASE_RTC->RTC_TIMR & AT91C_RTC_SEC) */
+#define GetSeconds() (AT91C_BASE_ST->ST_CRTR >> 15)
+
+extern void _init(void);
+
+#endif /* _AT91RM9200_LOWLEVEL_H_ */
Property changes on: trunk/sys/boot/arm/at91/libat91/at91rm9200_lowlevel.h
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Added: trunk/sys/boot/arm/at91/libat91/delay.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/delay.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/delay.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,44 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "spi_flash.h"
+#include "lib.h"
+
+void
+Delay(int us)
+{
+ unsigned later, now;
+
+ now = AT91C_BASE_ST->ST_CRTR;
+ later = (now + us / 25 + 1) & AT91C_ST_CRTV;
+ while (later != AT91C_BASE_ST->ST_CRTR)
+ continue;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/delay.c
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Added: trunk/sys/boot/arm/at91/libat91/eeprom.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/eeprom.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/eeprom.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,186 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: eeprom.c
+ *
+ * Instantiation of eeprom routines
+ *
+ * Revision information:
+ *
+ * 28AUG2004 kb_admin initial creation - adapted from Atmel sources
+ * 12JAN2005 kb_admin fixed clock generation, write polling, init
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "at91rm9200_lowlevel.h"
+#include "at91rm9200.h"
+#include "lib.h"
+
+/******************************* GLOBALS *************************************/
+
+
+/*********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+
+/* Use a macro to calculate the TWI clock generator value to save code space. */
+#define AT91C_TWSI_CLOCK 100000
+#define TWSI_EEPROM_ADDRESS 0x50
+
+#define TWI_CLK_BASE_DIV ((AT91C_MASTER_CLOCK/(4*AT91C_TWSI_CLOCK)) - 2)
+#define SET_TWI_CLOCK ((0x00010000) | (TWI_CLK_BASE_DIV) | (TWI_CLK_BASE_DIV << 8))
+
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void InitEEPROM(void)
+ * This global function initializes the EEPROM interface (TWI). Intended
+ * to be called a single time.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+InitEEPROM(void)
+{
+
+ AT91PS_TWI twiPtr = (AT91PS_TWI)AT91C_BASE_TWI;
+
+ AT91PS_PIO pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ AT91PS_PMC pPMC = (AT91PS_PMC)AT91C_BASE_PMC;
+
+ pPio->PIO_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+ pPio->PIO_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
+
+ pPio->PIO_MDDR = ~AT91C_PA25_TWD;
+ pPio->PIO_MDER = AT91C_PA25_TWD;
+
+ pPMC->PMC_PCER = 1u << AT91C_ID_TWI;
+
+ twiPtr->TWI_IDR = 0xffffffffu;
+ twiPtr->TWI_CR = AT91C_TWI_SWRST;
+ twiPtr->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+
+ twiPtr->TWI_CWGR = SET_TWI_CLOCK;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void ReadEEPROM(unsigned ee_addr, char *data_addr, unsigned size)
+ * This global function reads data from the eeprom at ee_addr storing data
+ * to data_addr for size bytes. Assume the TWI has been initialized.
+ * This function does not utilize the page read mode to simplify the code.
+ * .KB_C_FN_DEFINITION_END
+ */
+int
+ReadEEPROM(unsigned ee_off, unsigned char *data_addr, unsigned size)
+{
+ const AT91PS_TWI twiPtr = AT91C_BASE_TWI;
+ unsigned int status;
+ unsigned int count;
+
+ status = twiPtr->TWI_SR;
+ status = twiPtr->TWI_RHR;
+
+ // Set the TWI Master Mode Register
+ twiPtr->TWI_MMR = (TWSI_EEPROM_ADDRESS << 16) |
+ AT91C_TWI_IADRSZ_2_BYTE | AT91C_TWI_MREAD;
+
+ // Set TWI Internal Address Register
+ twiPtr->TWI_IADR = ee_off;
+
+ // Start transfer
+ twiPtr->TWI_CR = AT91C_TWI_START;
+
+ status = twiPtr->TWI_SR;
+
+ while (size-- > 1){
+ // Wait RHR Holding register is full
+ count = 1000000;
+ while (!(twiPtr->TWI_SR & AT91C_TWI_RXRDY) && --count > 0)
+ continue;
+ if (count <= 0)
+ return -1;
+
+ // Read byte
+ *(data_addr++) = twiPtr->TWI_RHR;
+ }
+
+ twiPtr->TWI_CR = AT91C_TWI_STOP;
+
+ status = twiPtr->TWI_SR;
+
+ // Wait transfer is finished
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXCOMP))
+ continue;
+
+ // Read last byte
+ *data_addr = twiPtr->TWI_RHR;
+ return 0;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void WriteEEPROM(unsigned ee_off, char *data_addr, unsigned size)
+ * This global function writes data to the eeprom at ee_off using data
+ * from data_addr for size bytes. Assume the TWI has been initialized.
+ * This function does not utilize the page write mode as the write time is
+ * much greater than the time required to access the device for byte-write
+ * functionality. This allows the function to be much simpler.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+WriteEEPROM(unsigned ee_off, char *data_addr, unsigned size)
+{
+ const AT91PS_TWI twiPtr = AT91C_BASE_TWI;
+ unsigned status;
+ unsigned char test_data;
+
+ while (size--) {
+ if (!(ee_off & 0x3f))
+ putchar('.');
+
+ // Set the TWI Master Mode Register
+ twiPtr->TWI_MMR = ((TWSI_EEPROM_ADDRESS << 16) |
+ AT91C_TWI_IADRSZ_2_BYTE) & ~AT91C_TWI_MREAD;
+
+ // Set TWI Internal Address Register
+ twiPtr->TWI_IADR = ee_off++;
+
+ status = twiPtr->TWI_SR;
+
+ twiPtr->TWI_THR = *(data_addr++);
+
+ twiPtr->TWI_CR = AT91C_TWI_START;
+
+ // Wait transfer is finished
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXRDY))
+ continue;
+
+ twiPtr->TWI_CR = AT91C_TWI_STOP;
+
+ status = twiPtr->TWI_SR;
+
+ // Wait transfer is finished
+ while (!(twiPtr->TWI_SR & AT91C_TWI_TXCOMP))
+ continue;
+
+ // wait for write operation to complete
+ ReadEEPROM(ee_off, &test_data, 1);
+ }
+
+ putchar('\r');
+ putchar('\n');
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/eeprom.c
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Added: trunk/sys/boot/arm/at91/libat91/emac.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/emac.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/emac.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,574 @@
+/* $MidnightBSD$ */
+/*******************************************************************************
+ *
+ * Filename: emac.c
+ *
+ * Instantiation of routines for MAC/ethernet functions supporting tftp.
+ *
+ * Revision information:
+ *
+ * 28AUG2004 kb_admin initial creation
+ * 08JAN2005 kb_admin added tftp download
+ * also adapted from external sources
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ ******************************************************************************/
+
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+#include "emac.h"
+#include "lib.h"
+
+/* ****************************** GLOBALS *************************************/
+
+/* ********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+static receive_descriptor_t *p_rxBD;
+static unsigned short localPort;
+static unsigned short serverPort;
+static unsigned serverMACSet;
+static unsigned localIPSet, serverIPSet;
+static unsigned lastSize;
+static unsigned char serverMACAddr[6];
+static unsigned char localIPAddr[4], serverIPAddr[4];
+static int ackBlock;
+static char *dlAddress;
+
+static unsigned transmitBuffer[1024 / sizeof(unsigned)];
+static unsigned tftpSendPacket[256 / sizeof(unsigned)];
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned short IP_checksum(unsigned short *p, int len)
+ * This private function calculates the IP checksum for various headers.
+ * .KB_C_FN_DEFINITION_END
+ */
+static unsigned short
+IP_checksum(unsigned short *p, int len)
+{
+ unsigned i, t;
+
+ len &= ~1;
+
+ for (i=0,t=0; i<len; i+=2, ++p)
+ t += SWAP16(*p);
+
+ t = (t & 0xffff) + (t >> 16);
+ return (~t);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void GetServerAddress(void)
+ * This private function sends an ARP request to determine the server MAC.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+GetServerAddress(void)
+{
+ arp_header_t *p_ARP;
+
+ p_ARP = (arp_header_t*)transmitBuffer;
+
+ p_memset((char*)p_ARP->dest_mac, 0xFF, 6);
+
+ memcpy(p_ARP->src_mac, localMACAddr, 6);
+
+ p_ARP->frame_type = SWAP16(PROTOCOL_ARP);
+ p_ARP->hard_type = SWAP16(1);
+ p_ARP->prot_type = SWAP16(PROTOCOL_IP);
+ p_ARP->hard_size = 6;
+ p_ARP->prot_size = 4;
+ p_ARP->operation = SWAP16(ARP_REQUEST);
+
+ memcpy(p_ARP->sender_mac, localMACAddr, 6);
+ memcpy(p_ARP->sender_ip, localIPAddr, 4);
+ p_memset((char*)p_ARP->target_mac, 0, 6);
+ memcpy(p_ARP->target_ip, serverIPAddr, 4);
+
+ // wait until transmit is available
+ while (!(*AT91C_EMAC_TSR & AT91C_EMAC_BNQ)) ;
+
+ *AT91C_EMAC_TSR |= AT91C_EMAC_COMP;
+ *AT91C_EMAC_TAR = (unsigned)transmitBuffer;
+ *AT91C_EMAC_TCR = 0x40;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void Send_TFTP_Packet(char *tftpData, unsigned tftpLength)
+ * This private function initializes and send a TFTP packet.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+Send_TFTP_Packet(char *tftpData, unsigned tftpLength)
+{
+ transmit_header_t *macHdr = (transmit_header_t*)tftpSendPacket;
+ ip_header_t *ipHdr;
+ udp_header_t *udpHdr;
+ unsigned t_checksum;
+
+ memcpy(macHdr->dest_mac, serverMACAddr, 6);
+ memcpy(macHdr->src_mac, localMACAddr, 6);
+ macHdr->proto_mac = SWAP16(PROTOCOL_IP);
+
+ ipHdr = (ip_header_t*)&macHdr->packet_length;
+
+ ipHdr->ip_v_hl = 0x45;
+ ipHdr->ip_tos = 0;
+ ipHdr->ip_len = SWAP16(28 + tftpLength);
+ ipHdr->ip_id = 0;
+ ipHdr->ip_off = SWAP16(0x4000);
+ ipHdr->ip_ttl = 64;
+ ipHdr->ip_p = PROTOCOL_UDP;
+ ipHdr->ip_sum = 0;
+
+ memcpy(ipHdr->ip_src, localIPAddr, 4);
+ memcpy(ipHdr->ip_dst, serverIPAddr, 4);
+
+ ipHdr->ip_sum = SWAP16(IP_checksum((unsigned short*)ipHdr, 20));
+
+ udpHdr = (udp_header_t*)(ipHdr + 1);
+
+ udpHdr->src_port = localPort;
+ udpHdr->dst_port = serverPort;
+ udpHdr->udp_len = SWAP16(8 + tftpLength);
+ udpHdr->udp_cksum = 0;
+
+ memcpy((char *)udpHdr+8, tftpData, tftpLength);
+
+ t_checksum = IP_checksum((unsigned short*)ipHdr + 6, (16 + tftpLength));
+
+ t_checksum = (~t_checksum) & 0xFFFF;
+ t_checksum += 25 + tftpLength;
+
+ t_checksum = (t_checksum & 0xffff) + (t_checksum >> 16);
+ t_checksum = (~t_checksum) & 0xFFFF;
+
+ udpHdr->udp_cksum = SWAP16(t_checksum);
+
+ while (!(*AT91C_EMAC_TSR & AT91C_EMAC_BNQ)) ;
+
+ *AT91C_EMAC_TSR |= AT91C_EMAC_COMP;
+ *AT91C_EMAC_TAR = (unsigned)tftpSendPacket;
+ *AT91C_EMAC_TCR = 42 + tftpLength;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void TFTP_RequestFile(char *filename)
+ * This private function sends a RRQ packet to the server.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+TFTP_RequestFile(char *filename)
+{
+ tftp_header_t tftpHeader;
+ char *cPtr, *ePtr, *mPtr;
+ unsigned length;
+
+ tftpHeader.opcode = TFTP_RRQ_OPCODE;
+
+ cPtr = (char*)&(tftpHeader.block_num);
+
+ ePtr = strcpy(cPtr, filename);
+ mPtr = strcpy(ePtr, "octet");
+
+ length = mPtr - cPtr;
+ length += 2;
+
+ Send_TFTP_Packet((char*)&tftpHeader, length);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void TFTP_ACK_Data(char *data, unsigned short block_num, unsigned short len)
+ * This private function sends an ACK packet to the server.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+TFTP_ACK_Data(unsigned char *data, unsigned short block_num, unsigned short len)
+{
+ tftp_header_t tftpHeader;
+
+ if (block_num == (ackBlock + 1)) {
+ ++ackBlock;
+ memcpy(dlAddress, data, len);
+ dlAddress += len;
+ lastSize += len;
+ if (ackBlock % 128 == 0)
+ printf("tftp: %u kB\r", lastSize / 1024);
+ }
+ tftpHeader.opcode = TFTP_ACK_OPCODE;
+ tftpHeader.block_num = SWAP16(ackBlock);
+ Send_TFTP_Packet((char*)&tftpHeader, 4);
+ if (len < 512) {
+ ackBlock = -2;
+ printf("tftp: %u byte\n", lastSize);
+ }
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void CheckForNewPacket(ip_header_t *pHeader)
+ * This private function polls for received ethernet packets and handles
+ * any here.
+ * .KB_C_FN_DEFINITION_END
+ */
+static int
+CheckForNewPacket(ip_header_t *pHeader)
+{
+ unsigned short *pFrameType;
+ unsigned i;
+ char *pData;
+ ip_header_t *pIpHeader;
+ arp_header_t *p_ARP;
+ int process = 0;
+
+ process = 0;
+ for (i = 0; i < MAX_RX_PACKETS; ++i) {
+ if(p_rxBD[i].address & 0x1) {
+ process = 1;
+ (*AT91C_EMAC_RSR) |= (*AT91C_EMAC_RSR);
+ break;
+ }
+ }
+
+ if (!process)
+ return (0);
+ process = i;
+
+ pFrameType = (unsigned short *)((p_rxBD[i].address & 0xFFFFFFFC) + 12);
+ pData = (char *)(p_rxBD[i].address & 0xFFFFFFFC);
+
+ switch (*pFrameType) {
+
+ case SWAP16(PROTOCOL_ARP):
+ p_ARP = (arp_header_t*)pData;
+ if (p_ARP->operation == SWAP16(ARP_REPLY)) {
+ // check if new server info is available
+ if ((!serverMACSet) &&
+ (!(p_memcmp((char*)p_ARP->sender_ip,
+ (char*)serverIPAddr, 4)))) {
+
+ serverMACSet = 1;
+ memcpy(serverMACAddr, p_ARP->sender_mac, 6);
+ }
+ } else if (p_ARP->operation == SWAP16(ARP_REQUEST)) {
+ // ARP REPLY operation
+ p_ARP->operation = SWAP16(ARP_REPLY);
+
+ // Fill the dest address and src address
+ for (i = 0; i <6; i++) {
+ // swap ethernet dest address and ethernet src address
+ pData[i] = pData[i+6];
+ pData[i+6] = localMACAddr[i];
+ // swap sender ethernet address and target ethernet address
+ pData[i+22] = localMACAddr[i];
+ pData[i+32] = pData[i+6];
+ }
+
+ // swap sender IP address and target IP address
+ for (i = 0; i<4; i++) {
+ pData[i+38] = pData[i+28];
+ pData[i+28] = localIPAddr[i];
+ }
+
+ if (!(*AT91C_EMAC_TSR & AT91C_EMAC_BNQ)) break;
+
+ *AT91C_EMAC_TSR |= AT91C_EMAC_COMP;
+ *AT91C_EMAC_TAR = (unsigned)pData;
+ *AT91C_EMAC_TCR = 0x40;
+ }
+ break;
+ case SWAP16(PROTOCOL_IP):
+ pIpHeader = (ip_header_t*)(pData + 14);
+ memcpy(pHeader, pIpHeader, sizeof(ip_header_t));
+
+ if (pIpHeader->ip_p == PROTOCOL_UDP) {
+ udp_header_t *udpHdr;
+ tftp_header_t *tftpHdr;
+
+ udpHdr = (udp_header_t*)((char*)pIpHeader+20);
+ tftpHdr = (tftp_header_t*)((char*)udpHdr + 8);
+
+ if (udpHdr->dst_port != localPort)
+ break;
+
+ if (tftpHdr->opcode != TFTP_DATA_OPCODE)
+ break;
+
+ if (ackBlock == -1) {
+ if (tftpHdr->block_num != SWAP16(1))
+ break;
+ serverPort = udpHdr->src_port;
+ ackBlock = 0;
+ }
+
+ if (serverPort != udpHdr->src_port)
+ break;
+
+ TFTP_ACK_Data(tftpHdr->data,
+ SWAP16(tftpHdr->block_num),
+ SWAP16(udpHdr->udp_len) - 12);
+ }
+ }
+ p_rxBD[process].address &= ~0x01;
+ return (1);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned short AT91F_MII_ReadPhy (AT91PS_EMAC pEmac, unsigned char addr)
+ * This private function reads the PHY device.
+ * .KB_C_FN_DEFINITION_END
+ */
+#ifndef BOOT_BWCT
+static unsigned short
+AT91F_MII_ReadPhy (AT91PS_EMAC pEmac, unsigned char addr)
+{
+ unsigned value = 0x60020000 | (addr << 18);
+
+ pEmac->EMAC_CTL |= AT91C_EMAC_MPE;
+ pEmac->EMAC_MAN = value;
+ while(!((pEmac->EMAC_SR) & AT91C_EMAC_IDLE));
+ pEmac->EMAC_CTL &= ~AT91C_EMAC_MPE;
+ return (pEmac->EMAC_MAN & 0x0000ffff);
+}
+#endif
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned short AT91F_MII_WritePhy (AT91PS_EMAC pEmac, unsigned char addr, unsigned short s)
+ * This private function writes the PHY device.
+ * .KB_C_FN_DEFINITION_END
+ */
+#ifdef BOOT_TSC
+static unsigned short
+AT91F_MII_WritePhy (AT91PS_EMAC pEmac, unsigned char addr, unsigned short s)
+{
+ unsigned value = 0x50020000 | (addr << 18) | s;
+
+ pEmac->EMAC_CTL |= AT91C_EMAC_MPE;
+ pEmac->EMAC_MAN = value;
+ while(!((pEmac->EMAC_SR) & AT91C_EMAC_IDLE));
+ pEmac->EMAC_CTL &= ~AT91C_EMAC_MPE;
+ return (pEmac->EMAC_MAN & 0x0000ffff);
+}
+#endif
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void MII_GetLinkSpeed(AT91PS_EMAC pEmac)
+ * This private function determines the link speed set by the PHY.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+MII_GetLinkSpeed(AT91PS_EMAC pEmac)
+{
+#if defined(BOOT_TSC) || defined(BOOT_KB920X) || defined(BOOT_CENTIPAD)
+ unsigned short stat2;
+#endif
+ unsigned update;
+#ifdef BOOT_TSC
+ unsigned sec;
+ int i;
+#endif
+#ifdef BOOT_BWCT
+ /* hardcoded link speed since we connect a switch via MII */
+ update = pEmac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ update |= AT91C_EMAC_SPD;
+ update |= AT91C_EMAC_FD;
+#endif
+#if defined(BOOT_KB920X) || defined(BOOT_CENTIPAD)
+ stat2 = AT91F_MII_ReadPhy(pEmac, MII_STS2_REG);
+ if (!(stat2 & MII_STS2_LINK))
+ return ;
+ update = pEmac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ if (stat2 & MII_STS2_100TX)
+ update |= AT91C_EMAC_SPD;
+ if (stat2 & MII_STS2_FDX)
+ update |= AT91C_EMAC_FD;
+#endif
+#ifdef BOOT_TSC
+ while (1) {
+ for (i = 0; i < 10; i++) {
+ stat2 = AT91F_MII_ReadPhy(pEmac, MII_STS_REG);
+ if (stat2 & MII_STS_LINK_STAT)
+ break;
+ printf(".");
+ sec = GetSeconds();
+ while (GetSeconds() == sec)
+ continue;
+ }
+ if (stat2 & MII_STS_LINK_STAT)
+ break;
+ printf("Resetting MII...");
+ AT91F_MII_WritePhy(pEmac, 0x0, 0x8000);
+ while (AT91F_MII_ReadPhy(pEmac, 0x0) & 0x8000) continue;
+ }
+ printf("emac: link");
+ stat2 = AT91F_MII_ReadPhy(pEmac, MII_SPEC_STS_REG);
+ update = pEmac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
+ if (stat2 & (MII_SSTS_100FDX | MII_SSTS_100HDX)) {
+ printf(" 100TX");
+ update |= AT91C_EMAC_SPD;
+ }
+ if (stat2 & (MII_SSTS_100FDX | MII_SSTS_10FDX)) {
+ printf(" FDX");
+ update |= AT91C_EMAC_FD;
+ }
+ printf("\n");
+#endif
+ pEmac->EMAC_CFG = update;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void AT91F_EmacEntry(void)
+ * This private function initializes the EMAC on the chip.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+AT91F_EmacEntry(void)
+{
+ unsigned i;
+ char *pRxPacket = (char*)RX_DATA_START;
+ AT91PS_EMAC pEmac = AT91C_BASE_EMAC;
+
+ p_rxBD = (receive_descriptor_t*)RX_BUFFER_START;
+ localPort = SWAP16(0x8002);
+
+ for (i = 0; i < MAX_RX_PACKETS; ++i) {
+
+ p_rxBD[i].address = (unsigned)pRxPacket;
+ p_rxBD[i].size = 0;
+ pRxPacket += RX_PACKET_SIZE;
+ }
+
+ // Set the WRAP bit at the end of the list descriptor
+ p_rxBD[MAX_RX_PACKETS-1].address |= 0x02;
+
+ if (!(pEmac->EMAC_SR & AT91C_EMAC_LINK))
+ MII_GetLinkSpeed(pEmac);
+
+ pEmac->EMAC_RBQP = (unsigned) p_rxBD;
+ pEmac->EMAC_RSR |= (AT91C_EMAC_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
+ pEmac->EMAC_CTL = AT91C_EMAC_TE | AT91C_EMAC_RE;
+
+ pEmac->EMAC_TAR = (unsigned)transmitBuffer;
+}
+
+
+/* ************************** GLOBAL FUNCTIONS ********************************/
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SetServerIPAddress(unsigned address)
+ * This global function sets the IP of the TFTP download server.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SetServerIPAddress(unsigned address)
+{
+ // force update in case the IP has changed
+ serverMACSet = 0;
+
+ serverIPAddr[0] = (address >> 24) & 0xFF;
+ serverIPAddr[1] = (address >> 16) & 0xFF;
+ serverIPAddr[2] = (address >> 8) & 0xFF;
+ serverIPAddr[3] = (address >> 0) & 0xFF;
+
+ serverIPSet = 1;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SetLocalIPAddress(unsigned address)
+ * This global function sets the IP of this module.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SetLocalIPAddress(unsigned address)
+{
+ // force update in case the IP has changed
+ serverMACSet = 0;
+
+ localIPAddr[0] = (address >> 24) & 0xFF;
+ localIPAddr[1] = (address >> 16) & 0xFF;
+ localIPAddr[2] = (address >> 8) & 0xFF;
+ localIPAddr[3] = (address >> 0) & 0xFF;
+
+ localIPSet = 1;
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void TFTP_Download(unsigned address, char *filename)
+ * This global function initiates and processes a tftp download request.
+ * The server IP, local IP, local MAC must be set before this function is
+ * executed.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+TFTP_Download(unsigned address, char *filename)
+{
+ ip_header_t IpHeader;
+ unsigned thisSeconds;
+ int timeout;
+
+ if ((!localMACSet) || (!localIPSet) || (!serverIPSet))
+ return ;
+
+ AT91F_EmacEntry();
+ GetServerAddress();
+ dlAddress = (char*)address;
+ lastSize = 0;
+ timeout = 10;
+ thisSeconds = (GetSeconds() + 2) % 32;
+ serverPort = SWAP16(69);
+ ++localPort;
+ ackBlock = -1;
+
+ while (timeout) {
+ if (CheckForNewPacket(&IpHeader)) {
+ if (ackBlock == -2)
+ break;
+ timeout = 10;
+ thisSeconds = (GetSeconds() + 2) % 32;
+ } else if (GetSeconds() == thisSeconds) {
+ --timeout;
+ thisSeconds = (GetSeconds() + 2) % 32;
+ if (!serverMACSet)
+ GetServerAddress();
+ else if (ackBlock == -1)
+ TFTP_RequestFile(filename);
+ else {
+ // Be sure to send a NAK, which is done by
+ // ACKing the last block we got.
+ TFTP_ACK_Data(0, ackBlock, 512);
+ printf("\nNAK %u\n", ackBlock);
+ }
+ }
+ }
+ if (timeout == 0)
+ printf("TFTP TIMEOUT!\n");
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/emac.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/emac.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/emac.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/emac.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,136 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: emac.h
+ *
+ * Definition of routine to set the MAC address.
+ *
+ * Revision information:
+ *
+ * 28AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+
+#ifndef _EMAC_H_
+#define _EMAC_H_
+
+extern void EMAC_SetMACAddress(unsigned char addr[6]);
+extern void SetServerIPAddress(unsigned address);
+extern void SetLocalIPAddress(unsigned address);
+extern void EMAC_Init(void);
+extern void TFTP_Download(unsigned address, char *filename);
+
+#define MAX_RX_PACKETS 8
+#define RX_PACKET_SIZE 1536
+#define RX_BUFFER_START 0x21000000
+#define RX_DATA_START (RX_BUFFER_START + (8 * MAX_RX_PACKETS))
+
+#define ARP_REQUEST 0x0001
+#define ARP_REPLY 0x0002
+#define PROTOCOL_ARP 0x0806
+#define PROTOCOL_IP 0x0800
+#define PROTOCOL_UDP 0x11
+
+#define SWAP16(x) ((((x) & 0xff) << 8) | ((x) >> 8))
+
+typedef struct {
+ unsigned address;
+ unsigned size;
+} receive_descriptor_t;
+
+typedef struct {
+
+ unsigned char dest_mac[6];
+
+ unsigned char src_mac[6];
+
+ unsigned short frame_type;
+ unsigned short hard_type;
+ unsigned short prot_type;
+ unsigned char hard_size;
+ unsigned char prot_size;
+
+ unsigned short operation;
+
+ unsigned char sender_mac[6];
+ unsigned char sender_ip[4];
+
+ unsigned char target_mac[6];
+ unsigned char target_ip[4];
+
+} __attribute__((__packed__)) arp_header_t;
+
+typedef struct {
+ unsigned char ip_v_hl;
+ unsigned char ip_tos;
+ unsigned short ip_len;
+ unsigned short ip_id;
+ unsigned short ip_off;
+ unsigned char ip_ttl;
+ unsigned char ip_p;
+ unsigned short ip_sum;
+ unsigned char ip_src[4];
+ unsigned char ip_dst[4];
+} __attribute__((__packed__)) ip_header_t;
+
+typedef struct {
+ unsigned char dest_mac[6];
+ unsigned char src_mac[6];
+ unsigned short proto_mac;
+ unsigned short packet_length;
+ ip_header_t iphdr;
+} __attribute__((__packed__)) transmit_header_t;
+
+typedef struct {
+ unsigned short src_port;
+ unsigned short dst_port;
+ unsigned short udp_len;
+ unsigned short udp_cksum;
+} __attribute__((__packed__)) udp_header_t;
+
+typedef struct {
+ unsigned short opcode;
+ unsigned short block_num;
+ unsigned char data[512];
+} __attribute__((__packed__)) tftp_header_t;
+
+// Preswap bytes
+#define TFTP_RRQ_OPCODE 0x0100
+#define TFTP_WRQ_OPCODE 0x0200
+#define TFTP_DATA_OPCODE 0x0300
+#define TFTP_ACK_OPCODE 0x0400
+#define TFTP_ERROR_OPCODE 0x0500
+
+/* MII registers definition */
+#define MII_STS_REG 0x01
+#define MII_STS_LINK_STAT 0x04
+#if defined(BOOT_KB920X) || defined(BOOT_CENTIPAD)
+#define MII_STS2_REG 0x11
+#define MII_STS2_LINK 0x400
+#define MII_STS2_100TX 0x4000
+#define MII_STS2_FDX 0x200
+#else
+#define MII_SPEC_STS_REG 0x11
+#define MII_SSTS_100FDX 0x8000
+#define MII_SSTS_100HDX 0x4000
+#define MII_SSTS_10FDX 0x2000
+#define MII_SSTS_10HDX 0x1000
+#endif
+
+extern unsigned char localMACAddr[6];
+extern unsigned localMAClow, localMAChigh;
+extern unsigned localMACSet;
+#define EMAC_Init()
+
+#endif /* _EMAC_H_ */
Property changes on: trunk/sys/boot/arm/at91/libat91/emac.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/emac_init.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/emac_init.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/emac_init.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,118 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+/******************************************************************************
+ *
+ * Filename: emac.c
+ *
+ * Instantiation of routines for MAC/ethernet functions supporting tftp.
+ *
+ * Revision information:
+ *
+ * 28AUG2004 kb_admin initial creation
+ * 08JAN2005 kb_admin added tftp download
+ * also adapted from external sources
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ ******************************************************************************/
+
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+#include "emac.h"
+#include "lib.h"
+
+/* ****************************** GLOBALS *************************************/
+
+unsigned localMACSet;
+unsigned char localMACAddr[6];
+unsigned localMAClow, localMAChigh;
+
+/* ********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void EMAC_SetMACAddress(unsigned low_address, unsigned high_address)
+ * This global function sets the MAC address. low_address is the first
+ * four bytes while high_address is the last 2 bytes of the 48-bit value.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+EMAC_SetMACAddress(unsigned char mac[6])
+{
+ AT91PS_PMC pPMC = AT91C_BASE_PMC;
+ AT91PS_EMAC pEmac = AT91C_BASE_EMAC;
+
+ /* enable the peripheral clock before using EMAC */
+ pPMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_EMAC);
+
+ memcpy(localMACAddr, mac, 6);
+ localMAClow = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
+ localMAChigh = (mac[5] << 8) | mac[4];
+ localMACSet = 1;
+
+ AT91C_BASE_PMC->PMC_PCER = 1u << AT91C_ID_EMAC;
+ AT91C_BASE_PIOA->PIO_ASR =
+ AT91C_PA14_ERXER | AT91C_PA12_ERX0 | AT91C_PA13_ERX1 |
+ AT91C_PA8_ETXEN | AT91C_PA16_EMDIO | AT91C_PA9_ETX0 |
+ AT91C_PA10_ETX1 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA15_EMDC |
+ AT91C_PA7_ETXCK_EREFCK;
+ AT91C_BASE_PIOA->PIO_PDR =
+ AT91C_PA14_ERXER | AT91C_PA12_ERX0 | AT91C_PA13_ERX1 |
+ AT91C_PA8_ETXEN | AT91C_PA16_EMDIO | AT91C_PA9_ETX0 |
+ AT91C_PA10_ETX1 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA15_EMDC |
+ AT91C_PA7_ETXCK_EREFCK;
+#if defined(BOOT_KB920X) | defined(BOOT_BWCT) /* Really !RMII */
+ AT91C_BASE_PIOB->PIO_BSR =
+ AT91C_PB12_ETX2 | AT91C_PB13_ETX3 | AT91C_PB14_ETXER |
+ AT91C_PB15_ERX2 | AT91C_PB16_ERX3 | AT91C_PB17_ERXDV |
+ AT91C_PB18_ECOL | AT91C_PB19_ERXCK;
+ AT91C_BASE_PIOB->PIO_PDR =
+ AT91C_PB12_ETX2 | AT91C_PB13_ETX3 | AT91C_PB14_ETXER |
+ AT91C_PB15_ERX2 | AT91C_PB16_ERX3 | AT91C_PB17_ERXDV |
+ AT91C_PB18_ECOL | AT91C_PB19_ERXCK;
+#endif
+ pEmac->EMAC_CTL = 0;
+
+ pEmac->EMAC_CFG = (pEmac->EMAC_CFG & ~(AT91C_EMAC_CLK)) |
+#ifdef BOOT_TSC
+ AT91C_EMAC_RMII |
+#endif
+ AT91C_EMAC_CLK_HCLK_32 | AT91C_EMAC_CAF;
+ // the sequence write EMAC_SA1L and write EMAC_SA1H must be respected
+ pEmac->EMAC_SA1L = localMAClow;
+ pEmac->EMAC_SA1H = localMAChigh;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/emac_init.c
___________________________________________________________________
Added: svn:eol-style
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/boot/arm/at91/libat91/getc.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/getc.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/getc.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,65 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provided by kwikbyte without
+ * copyright as follows:
+ *
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+#include "lib.h"
+
+/*
+ * int getc(int seconds)
+ *
+ * Reads a character from the DBGU port, if one is available within about
+ * seconds seconds. It assumes that DBGU has already been initialized.
+ */
+int
+getc(int seconds)
+{
+ AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
+ unsigned thisSecond;
+
+ // Clamp to 20s
+ if (seconds > 20)
+ seconds = 20;
+ thisSecond = GetSeconds();
+ seconds = thisSecond + seconds;
+ do {
+ if ((pUSART->US_CSR & AT91C_US_RXRDY))
+ return (pUSART->US_RHR & 0xFF);
+ thisSecond = GetSeconds();
+ } while (thisSecond != seconds);
+ return (-1);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/getc.c
___________________________________________________________________
Added: svn:eol-style
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+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/lib.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/lib.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/lib.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,66 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef ARM_BOOT_LIB_H
+#define ARM_BOOT_LIB_H
+
+int getc(int);
+void putchar(int);
+void xputchar(int);
+void printf(const char *fmt,...);
+
+/* The following function write eeprom at ee_addr using data */
+/* from data_add for size bytes. */
+int ReadEEPROM(unsigned eeoff, unsigned char *data_addr, unsigned size);
+void WriteEEPROM(unsigned eeoff, char *data_addr, unsigned size);
+void InitEEPROM(void);
+
+/* XMODEM protocol */
+int xmodem_rx(char *dst);
+
+/* */
+void start_wdog(int n);
+void reset(void);
+
+/* Delay us */
+void Delay(int us);
+
+#define ToASCII(x) ((x > 9) ? (x + 'A' - 0xa) : (x + '0'))
+
+int p_IsWhiteSpace(char cValue);
+unsigned p_HexCharValue(char cValue);
+unsigned p_ASCIIToHex(const char *buf);
+unsigned p_ASCIIToDec(const char *buf);
+
+void p_memset(char *buffer, char value, int size);
+int p_strlen(const char *buffer);
+char *strcpy(char *to, const char *from);
+void memcpy(void *to, const void *from, unsigned size);
+int p_memcmp(const char *to, const char *from, unsigned size);
+int strcmp(const char *to, const char *from);
+
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/lib.h
___________________________________________________________________
Added: svn:eol-style
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+native
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## -0,0 +1 ##
+MidnightBSD=%H
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Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/lib_AT91RM9200.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/lib_AT91RM9200.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/lib_AT91RM9200.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,278 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __LIBAT91RM9200_H
+#define __LIBAT91RM9200_H
+
+#include "at91rm9200.h"
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PMC_EnablePeriphClock (
+ AT91PS_PMC pPMC, // \arg pointer to PMC controller
+ unsigned int periphIds) // \arg IDs of peripherals to enable
+{
+ pPMC->PMC_PCER = periphIds;
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR PIO
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+static inline
+void AT91F_PIO_CfgPeriph(
+ AT91PS_PIO pPio, // \arg pointer to a PIO controller
+ unsigned int periphAEnable, // \arg PERIPH A to enable
+ unsigned int periphBEnable) // \arg PERIPH B to enable
+
+{
+ if (periphAEnable)
+ pPio->PIO_ASR = periphAEnable;
+ if (periphBEnable)
+ pPio->PIO_BSR = periphBEnable;
+ pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+/* *****************************************************************************
+ SOFTWARE API FOR MCI
+ ***************************************************************************** */
+//* Classic MCI Data Timeout Register Configuration with 1048576 MCK cycles between 2 data transfer
+#define AT91C_MCI_DTOR_1MEGA_CYCLES (AT91C_MCI_DTOCYC | AT91C_MCI_DTOMUL)
+
+//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot A
+#define AT91C_MCI_MMC_SLOTA (AT91C_MCI_SCDSEL & 0x0)
+
+//* Classic MCI SDCard Register Configuration with 1-bit data bus on slot B
+#define AT91C_MCI_MMC_SLOTB (AT91C_MCI_SCDSEL)
+
+//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot A
+#define AT91C_MCI_SDCARD_4BITS_SLOTA ( (AT91C_MCI_SCDSEL & 0x0) | AT91C_MCI_SCDBUS )
+
+//* Classic MCI SDCard Register Configuration with 4-bit data bus on slot B
+#define AT91C_MCI_SDCARD_4BITS_SLOTB (AT91C_MCI_SCDSEL | AT91C_MCI_SCDBUS)
+
+
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MCI_Configure
+//* \brief Configure the MCI
+//*----------------------------------------------------------------------------
+static inline
+void AT91F_MCI_Configure(
+ AT91PS_MCI pMCI, // \arg pointer to a MCI controller
+ unsigned int DTOR_register, // \arg Data Timeout Register to be programmed
+ unsigned int MR_register, // \arg Mode Register to be programmed
+ unsigned int SDCR_register) // \arg SDCard Register to be programmed
+{
+ //* Reset the MCI
+ pMCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN;
+
+ //* Disable all the interrupts
+ pMCI->MCI_IDR = 0xFFFFFFFF;
+
+ //* Set the Data Timeout Register
+ pMCI->MCI_DTOR = DTOR_register;
+
+ //* Set the Mode Register
+ pMCI->MCI_MR = MR_register;
+
+ //* Set the SDCard Register
+ pMCI->MCI_SDCR = SDCR_register;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MCI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for MCI
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_MCI_CfgPMC(void)
+{
+ AT91F_PMC_EnablePeriphClock(
+ AT91C_BASE_PMC, // PIO controller base address
+ ((unsigned int) 1 << AT91C_ID_MCI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_MCI_CfgPIO
+//* \brief Configure PIO controllers to drive MCI signals
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_MCI_CfgPIO(void)
+{
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOA, // PIO controller base address
+ ((unsigned int) AT91C_PA28_MCCDA ) |
+ ((unsigned int) AT91C_PA29_MCDA0 ) |
+ ((unsigned int) AT91C_PA27_MCCK ), // Peripheral A
+ 0); // Peripheral B
+ // Configure PIO controllers to periph mode
+ AT91F_PIO_CfgPeriph(
+ AT91C_BASE_PIOB, // PIO controller base address
+ 0, // Peripheral A
+ ((unsigned int) AT91C_PB5_MCDA3 ) |
+ ((unsigned int) AT91C_PB3_MCDA1 ) |
+ ((unsigned int) AT91C_PB4_MCDA2 )); // Peripheral B
+}
+
+
+/* *****************************************************************************
+ SOFTWARE API FOR PDC
+ ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_SetNextRx (
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RNPR = (unsigned int) address;
+ pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_SetNextTx(
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TNPR = (unsigned int) address;
+ pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_SetRx(
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be received
+ unsigned int bytes) // \arg number of bytes to be received
+{
+ pPDC->PDC_RPR = (unsigned int) address;
+ pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_SetTx(
+ AT91PS_PDC pPDC, // \arg pointer to a PDC controller
+ char *address, // \arg address to the next bloc to be transmitted
+ unsigned int bytes) // \arg number of bytes to be transmitted
+{
+ pPDC->PDC_TPR = (unsigned int) address;
+ pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_EnableTx(
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_EnableRx(
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_DisableTx(
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_DisableRx(
+ AT91PS_PDC pPDC ) // \arg pointer to a PDC controller
+{
+ pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+static inline void
+AT91F_PDC_Open(
+ AT91PS_PDC pPDC) // \arg pointer to a PDC controller
+{
+ //* Disable the RX and TX PDC transfer requests
+ AT91F_PDC_DisableRx(pPDC);
+ AT91F_PDC_DisableTx(pPDC);
+
+ //* Reset all Counter register Next buffer first
+ AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+ AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+ //* Enable the RX and TX PDC transfer requests
+ AT91F_PDC_EnableRx(pPDC);
+ AT91F_PDC_EnableTx(pPDC);
+}
+
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/lib_AT91RM9200.h
___________________________________________________________________
Added: svn:eol-style
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Added: trunk/sys/boot/arm/at91/libat91/mci_device.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/mci_device.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/mci_device.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,430 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+//*---------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*---------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*---------------------------------------------------------------------------
+//* File Name : AT91C_MCI_Device.h
+//* Object : Data Flash Atmel Description File
+//* Translator :
+//*
+//* 1.0 26/11/02 FB : Creation
+//*---------------------------------------------------------------------------
+
+#ifndef __MCI_Device_h
+#define __MCI_Device_h
+
+#include <sys/types.h>
+
+typedef unsigned int AT91S_MCIDeviceStatus;
+
+///////////////////////////////////////////////////////////////////////////////
+
+#define AT91C_CARD_REMOVED 0
+#define AT91C_MMC_CARD_INSERTED 1
+#define AT91C_SD_CARD_INSERTED 2
+
+#define AT91C_NO_ARGUMENT 0x0
+
+#define AT91C_FIRST_RCA 0xCAFE
+#define AT91C_MAX_MCI_CARDS 10
+
+#define AT91C_BUS_WIDTH_1BIT 0x00
+#define AT91C_BUS_WIDTH_4BITS 0x02
+
+/* Driver State */
+#define AT91C_MCI_IDLE 0x0
+#define AT91C_MCI_TIMEOUT_ERROR 0x1
+#define AT91C_MCI_RX_SINGLE_BLOCK 0x2
+#define AT91C_MCI_RX_MULTIPLE_BLOCK 0x3
+#define AT91C_MCI_RX_STREAM 0x4
+#define AT91C_MCI_TX_SINGLE_BLOCK 0x5
+#define AT91C_MCI_TX_MULTIPLE_BLOCK 0x6
+#define AT91C_MCI_TX_STREAM 0x7
+
+/* TimeOut */
+#define AT91C_TIMEOUT_CMDRDY 30
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// MMC & SDCard Structures
+///////////////////////////////////////////////////////////////////////////////
+
+/*---------------------------------------------*/
+/* MCI Device Structure Definition */
+/*---------------------------------------------*/
+typedef struct _AT91S_MciDevice
+{
+ volatile unsigned char state;
+ unsigned char SDCard_bus_width;
+ unsigned int RCA; // RCA
+ unsigned int READ_BL_LEN;
+#ifdef REPORT_SIZE
+ unsigned int Memory_Capacity;
+#endif
+} AT91S_MciDevice;
+
+#include <dev/mmc/mmcreg.h>
+
+///////////////////////////////////////////////////////////////////////////////
+// Functions returnals
+///////////////////////////////////////////////////////////////////////////////
+#define AT91C_CMD_SEND_OK 0 // Command ok
+#define AT91C_CMD_SEND_ERROR -1 // Command failed
+#define AT91C_INIT_OK 2 // Init Successfull
+#define AT91C_INIT_ERROR 3 // Init Failed
+#define AT91C_READ_OK 4 // Read Successfull
+#define AT91C_READ_ERROR 5 // Read Failed
+#define AT91C_WRITE_OK 6 // Write Successfull
+#define AT91C_WRITE_ERROR 7 // Write Failed
+#define AT91C_ERASE_OK 8 // Erase Successfull
+#define AT91C_ERASE_ERROR 9 // Erase Failed
+#define AT91C_CARD_SELECTED_OK 10 // Card Selection Successfull
+#define AT91C_CARD_SELECTED_ERROR 11 // Card Selection Failed
+
+#define AT91C_MCI_SR_ERROR (AT91C_MCI_UNRE | AT91C_MCI_OVRE | AT91C_MCI_DTOE | \
+ AT91C_MCI_DCRCE | AT91C_MCI_RTOE | AT91C_MCI_RENDE | AT91C_MCI_RCRCE | \
+ AT91C_MCI_RDIRE | AT91C_MCI_RINDE)
+
+#define MMC_CMDNB (0x1Fu << 0) // Command Number
+#define MMC_RSPTYP (0x3u << 6) // Response Type
+#define MMC_RSPTYP_NO (0x0u << 6) // No response
+#define MMC_RSPTYP_48 (0x1u << 6) // 48-bit response
+#define MMC_RSPTYP_136 (0x2u << 6) // 136-bit response
+#define MMC_SPCMD (0x7u << 8) // Special CMD
+#define MMC_SPCMD_NONE (0x0u << 8) // Not a special CMD
+#define MMC_SPCMD_INIT (0x1u << 8) // Initialization CMD
+#define MMC_SPCMD_SYNC (0x2u << 8) // Synchronized CMD
+#define MMC_SPCMD_IT_CMD (0x4u << 8) // Interrupt command
+#define MMC_SPCMD_IT_REP (0x5u << 8) // Interrupt response
+#define MMC_OPDCMD (0x1u << 11) // Open Drain Command
+#define MMC_MAXLAT (0x1u << 12) // Maximum Latency for Command to respond
+#define MMC_TRCMD (0x3u << 16) // Transfer CMD
+#define MMC_TRCMD_NO (0x0u << 16) // No transfer
+#define MMC_TRCMD_START (0x1u << 16) // Start transfer
+#define MMC_TRCMD_STOP (0x2u << 16) // Stop transfer
+#define MMC_TRDIR (0x1u << 18) // Transfer Direction
+#define MMC_TRTYP (0x3u << 19) // Transfer Type
+#define MMC_TRTYP_BLOCK (0x0u << 19) // Block Transfer type
+#define MMC_TRTYP_MULTIPLE (0x1u << 19) // Multiple Block transfer type
+#define MMC_TRTYP_STREAM (0x2u << 19) // Stream transfer type
+
+///////////////////////////////////////////////////////////////////////////////
+// MCI_CMD Register Value
+///////////////////////////////////////////////////////////////////////////////
+#define POWER_ON_INIT \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_INIT | MMC_OPDCMD)
+
+/////////////////////////////////////////////////////////////////
+// Class 0 & 1 commands: Basic commands and Read Stream commands
+/////////////////////////////////////////////////////////////////
+
+#define GO_IDLE_STATE_CMD \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE )
+#define MMC_GO_IDLE_STATE_CMD \
+ (0 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_OPDCMD)
+#define MMC_SEND_OP_COND_CMD \
+ (1 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_OPDCMD)
+
+#define ALL_SEND_CID_CMD \
+ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136)
+#define MMC_ALL_SEND_CID_CMD \
+ (2 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_OPDCMD)
+
+#define SET_RELATIVE_ADDR_CMD \
+ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define MMC_SET_RELATIVE_ADDR_CMD \
+ (3 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT | MMC_OPDCMD)
+
+#define SET_DSR_CMD \
+ (4 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_NO | \
+ MMC_MAXLAT) // no tested
+
+#define SEL_DESEL_CARD_CMD \
+ (7 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define SEND_CSD_CMD \
+ (9 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_MAXLAT)
+#define SEND_CID_CMD \
+ (10 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_136 | \
+ MMC_MAXLAT)
+#define MMC_READ_DAT_UNTIL_STOP_CMD \
+ (11 | MMC_TRTYP_STREAM | MMC_SPCMD_NONE | \
+ MMC_RSPTYP_48 | MMC_TRDIR | MMC_TRCMD_START | \
+ MMC_MAXLAT)
+
+#define STOP_TRANSMISSION_CMD \
+ (12 | MMC_TRCMD_STOP | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define STOP_TRANSMISSION_SYNC_CMD \
+ (12 | MMC_TRCMD_STOP | MMC_SPCMD_SYNC | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define SEND_STATUS_CMD \
+ (13 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | \
+ MMC_MAXLAT)
+#define GO_INACTIVE_STATE_CMD \
+ (15 | MMC_RSPTYP_NO)
+
+//*------------------------------------------------
+//* Class 2 commands: Block oriented Read commands
+//*------------------------------------------------
+
+#define SET_BLOCKLEN_CMD (16 | MMC_TRCMD_NO | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT )
+#define READ_SINGLE_BLOCK_CMD (17 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_BLOCK | MMC_TRDIR | MMC_MAXLAT)
+#define READ_MULTIPLE_BLOCK_CMD (18 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | MMC_TRTYP_MULTIPLE | MMC_TRDIR | MMC_MAXLAT)
+
+//*--------------------------------------------
+//* Class 3 commands: Sequential write commands
+//*--------------------------------------------
+
+#define MMC_WRITE_DAT_UNTIL_STOP_CMD (20 | MMC_TRTYP_STREAM| MMC_SPCMD_NONE | MMC_RSPTYP_48 & ~(MMC_TRDIR) | MMC_TRCMD_START | MMC_MAXLAT ) // MMC
+
+//*------------------------------------------------
+//* Class 4 commands: Block oriented write commands
+//*------------------------------------------------
+
+#define WRITE_BLOCK_CMD (24 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_BLOCK & ~(MMC_TRDIR)) | MMC_MAXLAT)
+#define WRITE_MULTIPLE_BLOCK_CMD (25 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_START | (MMC_TRTYP_MULTIPLE & ~(MMC_TRDIR)) | MMC_MAXLAT)
+#define PROGRAM_CSD_CMD (27 | MMC_RSPTYP_48 )
+
+
+//*----------------------------------------
+//* Class 6 commands: Group Write protect
+//*----------------------------------------
+
+#define SET_WRITE_PROT_CMD (28 | MMC_RSPTYP_48 )
+#define CLR_WRITE_PROT_CMD (29 | MMC_RSPTYP_48 )
+#define SEND_WRITE_PROT_CMD (30 | MMC_RSPTYP_48 )
+
+
+//*----------------------------------------
+//* Class 5 commands: Erase commands
+//*----------------------------------------
+
+#define TAG_SECTOR_START_CMD (32 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define TAG_SECTOR_END_CMD (33 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define MMC_UNTAG_SECTOR_CMD (34 | MMC_RSPTYP_48 )
+#define MMC_TAG_ERASE_GROUP_START_CMD (35 | MMC_RSPTYP_48 )
+#define MMC_TAG_ERASE_GROUP_END_CMD (36 | MMC_RSPTYP_48 )
+#define MMC_UNTAG_ERASE_GROUP_CMD (37 | MMC_RSPTYP_48 )
+#define ERASE_CMD (38 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT )
+
+//*----------------------------------------
+//* Class 7 commands: Lock commands
+//*----------------------------------------
+
+#define LOCK_UNLOCK (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
+
+//*-----------------------------------------------
+// Class 8 commands: Application specific commands
+//*-----------------------------------------------
+
+#define APP_CMD (55 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define GEN_CMD (56 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT) // no tested
+
+#define SDCARD_SET_BUS_WIDTH_CMD (6 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define SDCARD_STATUS_CMD (13 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define SDCARD_SEND_NUM_WR_BLOCKS_CMD (22 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define SDCARD_SET_WR_BLK_ERASE_COUNT_CMD (23 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define SDCARD_APP_OP_COND_CMD (41 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO )
+#define SDCARD_SET_CLR_CARD_DETECT_CMD (42 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+#define SDCARD_SEND_SCR_CMD (51 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+
+#define SDCARD_APP_ALL_CMD (SDCARD_SET_BUS_WIDTH_CMD +\
+ SDCARD_STATUS_CMD +\
+ SDCARD_SEND_NUM_WR_BLOCKS_CMD +\
+ SDCARD_SET_WR_BLK_ERASE_COUNT_CMD +\
+ SDCARD_APP_OP_COND_CMD +\
+ SDCARD_SET_CLR_CARD_DETECT_CMD +\
+ SDCARD_SEND_SCR_CMD)
+
+//*----------------------------------------
+//* Class 9 commands: IO Mode commands
+//*----------------------------------------
+
+#define MMC_FAST_IO_CMD (39 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_MAXLAT)
+#define MMC_GO_IRQ_STATE_CMD (40 | MMC_SPCMD_NONE | MMC_RSPTYP_48 | MMC_TRCMD_NO | MMC_MAXLAT)
+
+///////////////////////////////////////////////////////////////////////////////
+// OCR Register
+///////////////////////////////////////////////////////////////////////////////
+#define AT91C_VDD_16_17 (1 << 4)
+#define AT91C_VDD_17_18 (1 << 5)
+#define AT91C_VDD_18_19 (1 << 6)
+#define AT91C_VDD_19_20 (1 << 7)
+#define AT91C_VDD_20_21 (1 << 8)
+#define AT91C_VDD_21_22 (1 << 9)
+#define AT91C_VDD_22_23 (1 << 10)
+#define AT91C_VDD_23_24 (1 << 11)
+#define AT91C_VDD_24_25 (1 << 12)
+#define AT91C_VDD_25_26 (1 << 13)
+#define AT91C_VDD_26_27 (1 << 14)
+#define AT91C_VDD_27_28 (1 << 15)
+#define AT91C_VDD_28_29 (1 << 16)
+#define AT91C_VDD_29_30 (1 << 17)
+#define AT91C_VDD_30_31 (1 << 18)
+#define AT91C_VDD_31_32 (1 << 19)
+#define AT91C_VDD_32_33 (1 << 20)
+#define AT91C_VDD_33_34 (1 << 21)
+#define AT91C_VDD_34_35 (1 << 22)
+#define AT91C_VDD_35_36 (1 << 23)
+#define AT91C_CARD_POWER_UP_BUSY (1 << 31)
+
+#define AT91C_MMC_HOST_VOLTAGE_RANGE (AT91C_VDD_27_28 | AT91C_VDD_28_29 | \
+ AT91C_VDD_29_30 | AT91C_VDD_30_31 | AT91C_VDD_31_32 | AT91C_VDD_32_33)
+
+///////////////////////////////////////////////////////////////////////////////
+// CURRENT_STATE & READY_FOR_DATA in SDCard Status Register definition (response type R1)
+///////////////////////////////////////////////////////////////////////////////
+#define AT91C_SR_READY_FOR_DATA (1 << 8) // corresponds to buffer empty signalling on the bus
+#define AT91C_SR_IDLE (0 << 9)
+#define AT91C_SR_READY (1 << 9)
+#define AT91C_SR_IDENT (2 << 9)
+#define AT91C_SR_STBY (3 << 9)
+#define AT91C_SR_TRAN (4 << 9)
+#define AT91C_SR_DATA (5 << 9)
+#define AT91C_SR_RCV (6 << 9)
+#define AT91C_SR_PRG (7 << 9)
+#define AT91C_SR_DIS (8 << 9)
+
+#define AT91C_SR_CARD_SELECTED (AT91C_SR_READY_FOR_DATA + AT91C_SR_TRAN)
+
+#define MMC_FIRST_RCA 0xCAFE
+
+///////////////////////////////////////////////////////////////////////////////
+// MMC CSD register header File
+// CSD_x_xxx_S for shift value for word x
+// CSD_x_xxx_M for mask value for word x
+///////////////////////////////////////////////////////////////////////////////
+
+// First Response INT <=> CSD[3] : bits 0 to 31
+#define CSD_3_BIT0_S 0 // [0:0]
+#define CSD_3_BIT0_M 0x01
+#define CSD_3_CRC_S 1 // [7:1]
+#define CSD_3_CRC_M 0x7F
+#define CSD_3_MMC_ECC_S 8 // [9:8] reserved for MMC compatibility
+#define CSD_3_MMC_ECC_M 0x03
+#define CSD_3_FILE_FMT_S 10 // [11:10]
+#define CSD_3_FILE_FMT_M 0x03
+#define CSD_3_TMP_WP_S 12 // [12:12]
+#define CSD_3_TMP_WP_M 0x01
+#define CSD_3_PERM_WP_S 13 // [13:13]
+#define CSD_3_PERM_WP_M 0x01
+#define CSD_3_COPY_S 14 // [14:14]
+#define CSD_3_COPY_M 0x01
+#define CSD_3_FILE_FMT_GRP_S 15 // [15:15]
+#define CSD_3_FILE_FMT_GRP_M 0x01
+// reserved 16 // [20:16]
+// reserved 0x1F
+#define CSD_3_WBLOCK_P_S 21 // [21:21]
+#define CSD_3_WBLOCK_P_M 0x01
+#define CSD_3_WBLEN_S 22 // [25:22]
+#define CSD_3_WBLEN_M 0x0F
+#define CSD_3_R2W_F_S 26 // [28:26]
+#define CSD_3_R2W_F_M 0x07
+#define CSD_3_MMC_DEF_ECC_S 29 // [30:29] reserved for MMC compatibility
+#define CSD_3_MMC_DEF_ECC_M 0x03
+#define CSD_3_WP_GRP_EN_S 31 // [31:31]
+#define CSD_3_WP_GRP_EN_M 0x01
+
+// Seconde Response INT <=> CSD[2] : bits 32 to 63
+#define CSD_2_v21_WP_GRP_SIZE_S 0 // [38:32]
+#define CSD_2_v21_WP_GRP_SIZE_M 0x7F
+#define CSD_2_v21_SECT_SIZE_S 7 // [45:39]
+#define CSD_2_v21_SECT_SIZE_M 0x7F
+#define CSD_2_v21_ER_BLEN_EN_S 14 // [46:46]
+#define CSD_2_v21_ER_BLEN_EN_M 0x01
+
+#define CSD_2_v22_WP_GRP_SIZE_S 0 // [36:32]
+#define CSD_2_v22_WP_GRP_SIZE_M 0x1F
+#define CSD_2_v22_ER_GRP_SIZE_S 5 // [41:37]
+#define CSD_2_v22_ER_GRP_SIZE_M 0x1F
+#define CSD_2_v22_SECT_SIZE_S 10 // [46:42]
+#define CSD_2_v22_SECT_SIZE_M 0x1F
+
+#define CSD_2_C_SIZE_M_S 15 // [49:47]
+#define CSD_2_C_SIZE_M_M 0x07
+#define CSD_2_VDD_WMAX_S 18 // [52:50]
+#define CSD_2_VDD_WMAX_M 0x07
+#define CSD_2_VDD_WMIN_S 21 // [55:53]
+#define CSD_2_VDD_WMIN_M 0x07
+#define CSD_2_RCUR_MAX_S 24 // [58:56]
+#define CSD_2_RCUR_MAX_M 0x07
+#define CSD_2_RCUR_MIN_S 27 // [61:59]
+#define CSD_2_RCUR_MIN_M 0x07
+#define CSD_2_CSIZE_L_S 30 // [63:62] <=> 2 LSB of CSIZE
+#define CSD_2_CSIZE_L_M 0x03
+
+// Third Response INT <=> CSD[1] : bits 64 to 95
+#define CSD_1_CSIZE_H_S 0 // [73:64] <=> 10 MSB of CSIZE
+#define CSD_1_CSIZE_H_M 0x03FF
+// reserved 10 // [75:74]
+// reserved 0x03
+#define CSD_1_DSR_I_S 12 // [76:76]
+#define CSD_1_DSR_I_M 0x01
+#define CSD_1_RD_B_MIS_S 13 // [77:77]
+#define CSD_1_RD_B_MIS_M 0x01
+#define CSD_1_WR_B_MIS_S 14 // [78:78]
+#define CSD_1_WR_B_MIS_M 0x01
+#define CSD_1_RD_B_PAR_S 15 // [79:79]
+#define CSD_1_RD_B_PAR_M 0x01
+#define CSD_1_RD_B_LEN_S 16 // [83:80]
+#define CSD_1_RD_B_LEN_M 0x0F
+#define CSD_1_CCC_S 20 // [95:84]
+#define CSD_1_CCC_M 0x0FFF
+
+// Fourth Response INT <=> CSD[0] : bits 96 to 127
+#define CSD_0_TRANS_SPEED_S 0 // [103:96]
+#define CSD_0_TRANS_SPEED_M 0xFF
+#define CSD_0_NSAC_S 8 // [111:104]
+#define CSD_0_NSAC_M 0xFF
+#define CSD_0_TAAC_S 16 // [119:112]
+#define CSD_0_TAAC_M 0xFF
+// reserved 24 // [121:120]
+// reserved 0x03
+#define CSD_0_MMC_SPEC_VERS_S 26 // [125:122] reserved for MMC compatibility
+#define CSD_0_MMC_SPEC_VERS_M 0x0F
+#define CSD_0_STRUCT_S 30 // [127:126]
+#define CSD_0_STRUCT_M 0x03
+
+///////////////////////////////////////////////////////////////////////////////
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/mci_device.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
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+MidnightBSD=%H
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+text/plain
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Added: trunk/sys/boot/arm/at91/libat91/memcmp.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/memcmp.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/memcmp.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,39 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "lib.h"
+
+int
+p_memcmp(const char *to, const char *from, unsigned size)
+{
+ while ((--size) && (*to++ == *from++))
+ continue;
+
+ return (size || (*to != *from));
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/memcmp.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
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Added: trunk/sys/boot/arm/at91/libat91/memcpy.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/memcpy.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/memcpy.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,40 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "lib.h"
+
+void
+memcpy(void *dst, const void *src, unsigned len)
+{
+ const char *s = src;
+ char *d = dst;
+
+ while (len--)
+ *d++ = *s++;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/memcpy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/memset.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/memset.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/memset.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "lib.h"
+
+void
+p_memset(char *buffer, char value, int size)
+{
+ while (size--)
+ *buffer++ = value;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/memset.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/p_string.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/p_string.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/p_string.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,58 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: p_string.c
+ *
+ * Instantiation of basic string operations to prevent inclusion of full
+ * string library. These are simple implementations not necessarily optimized
+ * for speed, but rather to show intent.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin minor updates
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "lib.h"
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void p_memset(char *buffer, char value, int size)
+ * This global function sets memory at the pointer for the specified
+ * number of bytes to value.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+p_memset(char *buffer, char value, int size)
+{
+ while (size--)
+ *buffer++ = value;
+}
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int p_memcmp(char *to, char *from, unsigned size)
+ * This global function compares data at to against data at from for
+ * size bytes. Returns 0 if the locations are equal. size must be
+ * greater than 0.
+ * .KB_C_FN_DEFINITION_END
+ */
+int
+p_memcmp(const char *to, const char *from, unsigned size)
+{
+ while ((--size) && (*to++ == *from++))
+ continue;
+
+ return (*to != *from);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/p_string.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/printf.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/printf.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/printf.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,71 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 1998 Robert Nordier
+ * All rights reserved.
+ * Copyright (c) 2006 M. Warner Losh
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ *
+ * $FreeBSD$
+ */
+
+#include <stdarg.h>
+#include "lib.h"
+
+void
+printf(const char *fmt,...)
+{
+ va_list ap;
+ const char *hex = "0123456789abcdef";
+ char buf[10];
+ char *s;
+ unsigned u;
+ int c;
+
+ va_start(ap, fmt);
+ while ((c = *fmt++)) {
+ if (c == '%') {
+ c = *fmt++;
+ switch (c) {
+ case 'c':
+ xputchar(va_arg(ap, int));
+ continue;
+ case 's':
+ for (s = va_arg(ap, char *); *s; s++)
+ xputchar(*s);
+ continue;
+ case 'd': /* A lie, always prints unsigned */
+ case 'u':
+ u = va_arg(ap, unsigned);
+ s = buf;
+ do
+ *s++ = '0' + u % 10U;
+ while (u /= 10U);
+ dumpbuf:;
+ while (--s >= buf)
+ xputchar(*s);
+ continue;
+ case 'x':
+ u = va_arg(ap, unsigned);
+ s = buf;
+ do
+ *s++ = hex[u & 0xfu];
+ while (u >>= 4);
+ goto dumpbuf;
+ }
+ }
+ xputchar(c);
+ }
+ va_end(ap);
+
+ return;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/printf.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/putchar.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/putchar.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/putchar.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,63 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provided by kwikbyte without
+ * copyright as follows:
+ *
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "at91rm9200_lowlevel.h"
+#include "lib.h"
+
+/*
+ * void putchar(int ch)
+ * Writes a character to the DBGU port. It assumes that DBGU has
+ * already been initialized.
+ */
+void
+putchar(int ch)
+{
+ AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
+
+ while (!(pUSART->US_CSR & AT91C_US_TXRDY))
+ continue;
+ pUSART->US_THR = (ch & 0xFF);
+}
+
+void
+xputchar(int ch)
+{
+ if (ch == '\n')
+ putchar('\r');
+ putchar(ch);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/putchar.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/reset.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/reset.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/reset.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,58 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include "at91rm9200.h"
+#include "lib.h"
+
+/*
+ * void reset()
+ *
+ * Forces a reset of the system. Uses watchdog timer of '1', which
+ * corresponds to 128 / SLCK seconds (SLCK is 32,768 Hz, so 128/32768 is
+ * 1 / 256 ~= 5.4ms
+ */
+void
+reset(void)
+{
+ // The following should effect a reset.
+ AT91C_BASE_ST->ST_WDMR = 1 | AT91C_ST_RSTEN;
+ AT91C_BASE_ST->ST_CR = AT91C_ST_WDRST;
+}
+
+/*
+ * void start_wdog()
+ *
+ * Starts a watchdog timer. We force the boot process to get to the point
+ * it can kick the watch dog part of the ST part for the OS's driver.
+ */
+void
+start_wdog(int n)
+{
+ // The following should effect a reset after N seconds.
+ AT91C_BASE_ST->ST_WDMR = (n * (32768 / 128)) | AT91C_ST_RSTEN;
+ AT91C_BASE_ST->ST_CR = AT91C_ST_WDRST;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/reset.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/sd-card.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/sd-card.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/sd-card.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,413 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+//*----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name : main.c
+//* Object : main application written in C
+//* Creation : FB 21/11/2002
+//*
+//*----------------------------------------------------------------------------
+#include "at91rm9200.h"
+#include "lib_AT91RM9200.h"
+#include "mci_device.h"
+#include "lib.h"
+#include "sd-card.h"
+
+#define AT91C_MCI_TIMEOUT 1000000 /* For AT91F_MCIDeviceWaitReady */
+#define BUFFER_SIZE_MCI_DEVICE 512
+#define MASTER_CLOCK 60000000
+
+//* Global Variables
+AT91S_MciDevice MCI_Device;
+char Buffer[BUFFER_SIZE_MCI_DEVICE];
+
+/******************************************************************************
+**Error return codes
+******************************************************************************/
+#define MCI_UNSUPP_SIZE_ERROR 5
+#define MCI_UNSUPP_OFFSET_ERROR 6
+
+//*----------------------------------------------------------------------------
+//* \fn MCIDeviceWaitReady
+//* \brief Wait for MCI Device ready
+//*----------------------------------------------------------------------------
+static void
+MCIDeviceWaitReady(unsigned int timeout)
+{
+ volatile int status;
+
+ do
+ {
+ status = AT91C_BASE_MCI->MCI_SR;
+ timeout--;
+ }
+ while( !(status & AT91C_MCI_NOTBUSY) && (timeout>0) );
+
+ status = AT91C_BASE_MCI->MCI_SR;
+
+ // If End of Tx Buffer Empty interrupt occurred
+ if (MCI_Device.state == AT91C_MCI_TX_SINGLE_BLOCK && status & AT91C_MCI_TXBUFE) {
+ AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_TXBUFE;
+ AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_TXTDIS;
+ MCI_Device.state = AT91C_MCI_IDLE;
+ } // End of if AT91C_MCI_TXBUFF
+
+ // If End of Rx Buffer Full interrupt occurred
+ if (MCI_Device.state == AT91C_MCI_RX_SINGLE_BLOCK && status & AT91C_MCI_RXBUFF) {
+ AT91C_BASE_MCI->MCI_IDR = AT91C_MCI_RXBUFF;
+ AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTDIS;
+ MCI_Device.state = AT91C_MCI_IDLE;
+ } // End of if AT91C_MCI_RXBUFF
+}
+
+inline static unsigned int
+swap(unsigned int a)
+{
+ return (((a & 0xff) << 24) | ((a & 0xff00) << 8) | ((a & 0xff0000) >> 8)
+ | ((a & 0xff000000) >> 24));
+}
+
+inline static void
+wait_ready()
+{
+ int status;
+
+ // wait for CMDRDY Status flag to read the response
+ do
+ {
+ status = AT91C_BASE_MCI->MCI_SR;
+ } while( !(status & AT91C_MCI_CMDRDY) );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_SendCommand
+//* \brief Generic function to send a command to the MMC or SDCard
+//*----------------------------------------------------------------------------
+static int
+MCI_SendCommand(
+ unsigned int Cmd,
+ unsigned int Arg)
+{
+ unsigned int error;
+
+ AT91C_BASE_MCI->MCI_ARGR = Arg;
+ AT91C_BASE_MCI->MCI_CMDR = Cmd;
+
+// printf("CMDR %x ARG %x\n", Cmd, Arg);
+ wait_ready();
+ // Test error ==> if crc error and response R3 ==> don't check error
+ error = (AT91C_BASE_MCI->MCI_SR) & AT91C_MCI_SR_ERROR;
+ if (error != 0) {
+ if (error != AT91C_MCI_RCRCE)
+ return (1);
+ }
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_GetStatus
+//* \brief Addressed card sends its status register
+//*----------------------------------------------------------------------------
+static unsigned int
+MCI_GetStatus()
+{
+ if (MCI_SendCommand(SEND_STATUS_CMD, MCI_Device.RCA << 16))
+ return AT91C_CMD_SEND_ERROR;
+ return (AT91C_BASE_MCI->MCI_RSPR[0]);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_ReadBlock
+//* \brief Read an ENTIRE block or PARTIAL block
+//*----------------------------------------------------------------------------
+static int
+MCI_ReadBlock(int src, unsigned int *dataBuffer, int sizeToRead)
+{
+// unsigned log2sl = MCI_Device.READ_BL_LEN;
+// unsigned sectorLength = 1 << log2sl;
+ unsigned sectorLength = 512;
+
+ ///////////////////////////////////////////////////////////////////////
+ if (MCI_Device.state != AT91C_MCI_IDLE)
+ return 1;
+
+ if ((MCI_GetStatus() & AT91C_SR_READY_FOR_DATA) == 0)
+ return 1;
+
+ ///////////////////////////////////////////////////////////////////////
+
+ // Init Mode Register
+ AT91C_BASE_MCI->MCI_MR |= ((sectorLength << 16) | AT91C_MCI_PDCMODE);
+
+ sizeToRead = sizeToRead / 4;
+
+ AT91C_BASE_PDC_MCI->PDC_PTCR = (AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS);
+ AT91C_BASE_PDC_MCI->PDC_RPR = (unsigned int)dataBuffer;
+ AT91C_BASE_PDC_MCI->PDC_RCR = sizeToRead;
+
+ // Send the Read single block command
+ if (MCI_SendCommand(READ_SINGLE_BLOCK_CMD, src))
+ return AT91C_READ_ERROR;
+ MCI_Device.state = AT91C_MCI_RX_SINGLE_BLOCK;
+
+ // Enable AT91C_MCI_RXBUFF Interrupt
+ AT91C_BASE_MCI->MCI_IER = AT91C_MCI_RXBUFF;
+
+ // (PDC) Receiver Transfer Enable
+ AT91C_BASE_PDC_MCI->PDC_PTCR = AT91C_PDC_RXTEN;
+
+ return 0;
+}
+
+int
+MCI_read(char* dest, unsigned source, unsigned length)
+{
+// unsigned log2sl = MCI_Device.READ_BL_LEN;
+// unsigned sectorLength = 1 << log2sl;
+ unsigned sectorLength = 512;
+ int sizeToRead;
+ unsigned int *walker;
+
+ //As long as there is data to read
+ while (length)
+ {
+ if (length > sectorLength)
+ sizeToRead = sectorLength;
+ else
+ sizeToRead = length;
+
+ MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);
+ //Do the reading
+ if (MCI_ReadBlock(source,
+ (unsigned int*)dest, sizeToRead))
+ return -1;
+
+ //* Wait MCI Device Ready
+ MCIDeviceWaitReady(AT91C_MCI_TIMEOUT);
+
+ // Fix erratum in MCI part
+ for (walker = (unsigned int *)dest;
+ walker < (unsigned int *)(dest + sizeToRead); walker++)
+ *walker = swap(*walker);
+
+ //Update counters & pointers
+ length -= sizeToRead;
+ dest += sizeToRead;
+ source += sizeToRead;
+ }
+
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_SDCard_SendAppCommand
+//* \brief Specific function to send a specific command to the SDCard
+//*----------------------------------------------------------------------------
+static int
+MCI_SDCard_SendAppCommand(
+ unsigned int Cmd_App,
+ unsigned int Arg)
+{
+ // Send the CMD55 for application specific command
+ AT91C_BASE_MCI->MCI_ARGR = (MCI_Device.RCA << 16 );
+ AT91C_BASE_MCI->MCI_CMDR = APP_CMD;
+
+ wait_ready();
+ // if an error occurs
+ if (AT91C_BASE_MCI->MCI_SR & AT91C_MCI_SR_ERROR)
+ return (1);
+ return (MCI_SendCommand(Cmd_App,Arg));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_GetCSD
+//* \brief Asks to the specified card to send its CSD
+//*----------------------------------------------------------------------------
+static int
+MCI_GetCSD(unsigned int rca, unsigned int *response)
+{
+
+ if (MCI_SendCommand(SEND_CSD_CMD, (rca << 16)))
+ return 1;
+
+ response[0] = AT91C_BASE_MCI->MCI_RSPR[0];
+ response[1] = AT91C_BASE_MCI->MCI_RSPR[1];
+ response[2] = AT91C_BASE_MCI->MCI_RSPR[2];
+ response[3] = AT91C_BASE_MCI->MCI_RSPR[3];
+
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_SDCard_GetOCR
+//* \brief Asks to all cards to send their operations conditions
+//*----------------------------------------------------------------------------
+static int
+MCI_SDCard_GetOCR()
+{
+ unsigned int response=0x0;
+
+ // The RCA to be used for CMD55 in Idle state shall be the card's default RCA=0x0000.
+ MCI_Device.RCA = 0x0;
+
+ while( (response & AT91C_CARD_POWER_UP_BUSY) != AT91C_CARD_POWER_UP_BUSY ) {
+ if (MCI_SDCard_SendAppCommand(SDCARD_APP_OP_COND_CMD,
+ AT91C_MMC_HOST_VOLTAGE_RANGE))
+ return 1;
+ response = AT91C_BASE_MCI->MCI_RSPR[0];
+ }
+ return (0);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_SDCard_GetCID
+//* \brief Asks to the SDCard on the chosen slot to send its CID
+//*----------------------------------------------------------------------------
+static int
+MCI_SDCard_GetCID(unsigned int *response)
+{
+ if (MCI_SendCommand(ALL_SEND_CID_CMD, AT91C_NO_ARGUMENT))
+ return 1;
+
+ response[0] = AT91C_BASE_MCI->MCI_RSPR[0];
+ response[1] = AT91C_BASE_MCI->MCI_RSPR[1];
+ response[2] = AT91C_BASE_MCI->MCI_RSPR[2];
+ response[3] = AT91C_BASE_MCI->MCI_RSPR[3];
+
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn MCI_SDCard_SetBusWidth
+//* \brief Set bus width for SDCard
+//*----------------------------------------------------------------------------
+static int
+MCI_SDCard_SetBusWidth()
+{
+ volatile int ret_value;
+ char bus_width;
+
+ do {
+ ret_value=MCI_GetStatus();
+ }
+ while((ret_value > 0) && ((ret_value & AT91C_SR_READY_FOR_DATA) == 0));
+
+ // Select Card
+ MCI_SendCommand(SEL_DESEL_CARD_CMD, (MCI_Device.RCA)<<16);
+
+ // Set bus width for Sdcard
+ if (MCI_Device.SDCard_bus_width == AT91C_MCI_SCDBUS)
+ bus_width = AT91C_BUS_WIDTH_4BITS;
+ else
+ bus_width = AT91C_BUS_WIDTH_1BIT;
+
+ if (MCI_SDCard_SendAppCommand(
+ SDCARD_SET_BUS_WIDTH_CMD,bus_width) != AT91C_CMD_SEND_OK)
+ return 1;
+
+ return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn main
+//* \brief main function
+//*----------------------------------------------------------------------------
+int
+sdcard_init(void)
+{
+ unsigned int tab_response[4];
+#ifdef REPORT_SIZE
+ unsigned int mult,blocknr;
+#endif
+ int i;
+
+ // Init MCI for MMC and SDCard interface
+ AT91F_MCI_CfgPIO();
+ AT91F_MCI_CfgPMC();
+ AT91F_PDC_Open(AT91C_BASE_PDC_MCI);
+
+ // Init Device Structure
+ MCI_Device.state = AT91C_MCI_IDLE;
+ MCI_Device.SDCard_bus_width = AT91C_MCI_SCDBUS;
+
+ //* Reset the MCI
+ AT91C_BASE_MCI->MCI_CR = AT91C_MCI_MCIEN | AT91C_MCI_PWSEN;
+ AT91C_BASE_MCI->MCI_IDR = 0xFFFFFFFF;
+ AT91C_BASE_MCI->MCI_DTOR = AT91C_MCI_DTOR_1MEGA_CYCLES;
+ AT91C_BASE_MCI->MCI_MR = AT91C_MCI_PDCMODE;
+ AT91C_BASE_MCI->MCI_SDCR = AT91C_MCI_SDCARD_4BITS_SLOTA;
+ MCI_SendCommand(GO_IDLE_STATE_CMD, AT91C_NO_ARGUMENT);
+
+ for (i = 0; i < 100; i++) {
+ if (!MCI_SDCard_GetOCR(&MCI_Device))
+ break;
+ printf(".");
+ }
+ if (i >= 100)
+ return 0;
+ if (MCI_SDCard_GetCID(tab_response))
+ return 0;
+ if (MCI_SendCommand(SET_RELATIVE_ADDR_CMD, 0))
+ return 0;
+
+ MCI_Device.RCA = (AT91C_BASE_MCI->MCI_RSPR[0] >> 16);
+ if (MCI_GetCSD(MCI_Device.RCA,tab_response))
+ return 0;
+ MCI_Device.READ_BL_LEN = (tab_response[1] >> CSD_1_RD_B_LEN_S) &
+ CSD_1_RD_B_LEN_M;
+#ifdef REPORT_SIZE
+ // compute MULT
+ mult = 1 << ( ((tab_response[2] >> CSD_2_C_SIZE_M_S) &
+ CSD_2_C_SIZE_M_M) + 2 );
+ // compute MSB of C_SIZE
+ blocknr = ((tab_response[1] >> CSD_1_CSIZE_H_S) &
+ CSD_1_CSIZE_H_M) << 2;
+ // compute MULT * (LSB of C-SIZE + MSB already computed + 1) = BLOCKNR
+ blocknr = mult * ((blocknr + ((tab_response[2] >> CSD_2_CSIZE_L_S) &
+ CSD_2_CSIZE_L_M)) + 1);
+ MCI_Device.Memory_Capacity = (1 << MCI_Device.READ_BL_LEN) * blocknr;
+#endif
+ if (MCI_SDCard_SetBusWidth())
+ return 0;
+ if (MCI_SendCommand(SET_BLOCKLEN_CMD, 1 << MCI_Device.READ_BL_LEN))
+ return 0;
+#ifdef REPORT_SIZE
+ printf("Found SD card %u bytes\n", MCI_Device.Memory_Capacity);
+#endif
+ return 1;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/sd-card.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/sd-card.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/sd-card.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/sd-card.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,39 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef __SD_CARD_H
+#define __SD_CARD_H
+
+int MCI_write (unsigned dest, char* source, unsigned length);
+int MCI_read (char* dest, unsigned source, unsigned length);
+int sdcard_init(void);
+
+#endif
+
Property changes on: trunk/sys/boot/arm/at91/libat91/sd-card.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/spi_flash.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/spi_flash.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/spi_flash.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,268 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: spi_flash.c
+ *
+ * Instantiation of SPI flash control routines supporting AT45DB161B
+ *
+ * Revision information:
+ *
+ * 17JAN2005 kb_admin initial creation
+ * adapted from external sources
+ * tested for basic operation only!!!
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+#include "at91rm9200.h"
+#include "spi_flash.h"
+#include "lib.h"
+
+/*********************** PRIVATE FUNCTIONS/DATA ******************************/
+
+
+static spiCommand_t spi_command;
+static char tx_commandBuffer[8], rx_commandBuffer[8];
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SendCommand(spiCommand_t *pCommand)
+ * Private function sends 8-bit value to the device and returns the 8-bit
+ * value in response.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+SendCommand(spiCommand_t *pCommand)
+{
+ AT91PS_SPI pSPI = AT91C_BASE_SPI;
+
+ pSPI->SPI_PTCR = AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS;
+
+ pSPI->SPI_RPR = (unsigned)pCommand->rx_cmd;
+ pSPI->SPI_RCR = pCommand->rx_cmd_size;
+ pSPI->SPI_TPR = (unsigned)pCommand->tx_cmd;
+ pSPI->SPI_TCR = pCommand->tx_cmd_size;
+
+ pSPI->SPI_TNPR = (unsigned)pCommand->tx_data;
+ pSPI->SPI_TNCR = pCommand->tx_data_size;
+ pSPI->SPI_RNPR = (unsigned)pCommand->rx_data;
+ pSPI->SPI_RNCR = pCommand->rx_data_size;
+
+ pSPI->SPI_PTCR = AT91C_PDC_TXTEN | AT91C_PDC_RXTEN;
+
+ // wait for completion
+ while (!(pSPI->SPI_SR & AT91C_SPI_SPENDRX))
+ Delay(700);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * char GetFlashStatus(void)
+ * Private function to return device status.
+ * .KB_C_FN_DEFINITION_END
+ */
+static char
+GetFlashStatus(void)
+{
+ p_memset((char *)&spi_command, 0, sizeof(spi_command));
+ p_memset(tx_commandBuffer, 0, 8);
+ tx_commandBuffer[0] = STATUS_REGISTER_READ;
+ p_memset(rx_commandBuffer, 0, 8);
+ spi_command.tx_cmd = tx_commandBuffer;
+ spi_command.rx_cmd = rx_commandBuffer;
+ spi_command.rx_cmd_size = 2;
+ spi_command.tx_cmd_size = 2;
+ SendCommand(&spi_command);
+ return (rx_commandBuffer[1]);
+}
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void WaitForDeviceReady(void)
+ * Private function to poll until the device is ready for next operation.
+ * .KB_C_FN_DEFINITION_END
+ */
+static void
+WaitForDeviceReady(void)
+{
+ while (!(GetFlashStatus() & 0x80)) ;
+}
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SPI_ReadFlash(unsigned flash_addr, unsigned dest_addr, unsigned size)
+ * Global function to read the SPI flash device using the continuous read
+ * array command.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SPI_ReadFlash(unsigned flash_addr, char *dest_addr, unsigned size)
+{
+ unsigned pageAddress, byteAddress;
+
+ // determine page address
+ pageAddress = flash_addr / FLASH_PAGE_SIZE;
+
+ // determine byte address
+ byteAddress = flash_addr % FLASH_PAGE_SIZE;
+
+ p_memset(tx_commandBuffer, 0, 8);
+#ifdef BOOT_BWCT
+ tx_commandBuffer[0] = 0xd2;
+ tx_commandBuffer[1] = ((pageAddress >> 6) & 0xFF);
+ tx_commandBuffer[2] = ((pageAddress << 2) & 0xFC) |
+ ((byteAddress >> 8) & 0x3);
+ tx_commandBuffer[3] = byteAddress & 0xFF;
+ spi_command.tx_cmd = tx_commandBuffer;
+ spi_command.tx_cmd_size = 8;
+ spi_command.tx_data_size = size;
+ spi_command.tx_data = dest_addr;
+
+ p_memset(rx_commandBuffer, 0, 8);
+ spi_command.rx_cmd = rx_commandBuffer;
+ spi_command.rx_cmd_size = 8;
+ spi_command.rx_data_size = size;
+ spi_command.rx_data = dest_addr;
+#else
+ tx_commandBuffer[0] = CONTINUOUS_ARRAY_READ_HF;
+ tx_commandBuffer[1] = ((pageAddress >> 5) & 0xFF);
+ tx_commandBuffer[2] = ((pageAddress << 3) & 0xF8) |
+ ((byteAddress >> 8) & 0x7);
+ tx_commandBuffer[3] = byteAddress & 0xFF;
+ spi_command.tx_cmd = tx_commandBuffer;
+ spi_command.tx_cmd_size = 5;
+ spi_command.tx_data_size = size;
+ spi_command.tx_data = dest_addr;
+
+ p_memset(rx_commandBuffer, 0, 8);
+ spi_command.rx_cmd = rx_commandBuffer;
+ spi_command.rx_cmd_size = 5;
+ spi_command.rx_data_size = size;
+ spi_command.rx_data = dest_addr;
+#endif
+
+ SendCommand(&spi_command);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SPI_WriteFlash(unsigned flash_addr, unsigned src_addr, unsigned size)
+ * Global function to program the SPI flash device. Notice the warning
+ * provided in lower-level functions regarding corruption of data in non-
+ * page aligned write operations.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SPI_WriteFlash(unsigned flash_addr, char *src_addr, unsigned size)
+{
+ unsigned pageAddress, byteAddress;
+
+ // determine page address
+ pageAddress = flash_addr / FLASH_PAGE_SIZE;
+
+ // determine byte address
+ byteAddress = flash_addr % FLASH_PAGE_SIZE;
+
+ p_memset(tx_commandBuffer, 0, 8);
+#ifdef BOOT_BWCT
+ tx_commandBuffer[0] = 0x82;
+ tx_commandBuffer[1] = ((pageAddress >> 6) & 0xFF);
+ tx_commandBuffer[2] = ((pageAddress << 2) & 0xFC) |
+ ((byteAddress >> 8) & 0x3);
+ tx_commandBuffer[3] = (byteAddress & 0xFF);
+#else
+ tx_commandBuffer[0] = PROGRAM_THROUGH_BUFFER;
+ tx_commandBuffer[1] = ((pageAddress >> 5) & 0xFF);
+ tx_commandBuffer[2] = ((pageAddress << 3) & 0xF8) |
+ ((byteAddress >> 8) & 0x7);
+ tx_commandBuffer[3] = (byteAddress & 0xFF);
+#endif
+
+ p_memset(rx_commandBuffer, 0, 8);
+
+ spi_command.tx_cmd = tx_commandBuffer;
+ spi_command.rx_cmd = rx_commandBuffer;
+ spi_command.rx_cmd_size = 4;
+ spi_command.tx_cmd_size = 4;
+
+ spi_command.tx_data_size = size;
+ spi_command.tx_data = src_addr;
+ spi_command.rx_data_size = size;
+ spi_command.rx_data = src_addr;
+
+ SendCommand(&spi_command);
+
+ WaitForDeviceReady();
+}
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void SPI_InitFlash(void)
+ * Global function to initialize the SPI flash device/accessor functions.
+ * .KB_C_FN_DEFINITION_END
+ */
+void
+SPI_InitFlash(void)
+{
+ AT91PS_PIO pPio;
+ AT91PS_SPI pSPI = AT91C_BASE_SPI;
+ unsigned value;
+
+ // enable CS0, CLK, MOSI, MISO
+ pPio = (AT91PS_PIO)AT91C_BASE_PIOA;
+ pPio->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA1_MOSI | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+ pPio->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA1_MOSI | AT91C_PA0_MISO |
+ AT91C_PA2_SPCK;
+
+ // enable clocks to SPI
+ AT91C_BASE_PMC->PMC_PCER = 1u << AT91C_ID_SPI;
+
+ // reset the SPI
+ pSPI->SPI_CR = AT91C_SPI_SWRST;
+
+ pSPI->SPI_MR = (0xf << 24) | AT91C_SPI_MSTR | AT91C_SPI_MODFDIS |
+ (0xE << 16);
+
+ pSPI->SPI_CSR[0] = AT91C_SPI_CPOL | (4 << 16) | (2 << 8);
+ pSPI->SPI_CR = AT91C_SPI_SPIEN;
+
+ pSPI->SPI_PTCR = AT91C_PDC_TXTDIS;
+ pSPI->SPI_PTCR = AT91C_PDC_RXTDIS;
+ pSPI->SPI_RNPR = 0;
+ pSPI->SPI_RNCR = 0;
+ pSPI->SPI_TNPR = 0;
+ pSPI->SPI_TNCR = 0;
+ pSPI->SPI_RPR = 0;
+ pSPI->SPI_RCR = 0;
+ pSPI->SPI_TPR = 0;
+ pSPI->SPI_TCR = 0;
+ pSPI->SPI_PTCR = AT91C_PDC_RXTEN;
+ pSPI->SPI_PTCR = AT91C_PDC_TXTEN;
+
+ value = pSPI->SPI_RDR;
+ value = pSPI->SPI_SR;
+
+ value = GetFlashStatus() & 0xFC;
+#ifdef BOOT_BWCT
+ if (value != 0xB4 && value != 0xAC)
+ printf(" Bad SPI status: 0x%x\n", value);
+#else
+ if (value != 0xBC)
+ printf(" Bad SPI status: 0x%x\n", value);
+#endif
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/spi_flash.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/spi_flash.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/spi_flash.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/spi_flash.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,59 @@
+/* $MidnightBSD$ */
+/*******************************************************************************
+ *
+ * Filename: spi_flash.h
+ *
+ * Definition of flash control routines supporting AT45DB161B
+ *
+ * Revision information:
+ *
+ * 17JAN2005 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ ******************************************************************************/
+
+#ifndef _SPI_FLASH_H_
+#define _SPI_FLASH_H_
+
+typedef struct {
+ char *tx_cmd;
+ unsigned tx_cmd_size;
+ char *rx_cmd;
+ unsigned rx_cmd_size;
+ char *tx_data;
+ unsigned tx_data_size;
+ char *rx_data;
+ unsigned rx_data_size;
+} spiCommand_t;
+
+void SPI_ReadFlash(unsigned flash_addr, char *dest_addr, unsigned size);
+void SPI_WriteFlash(unsigned flash_addr, char *dest_addr, unsigned size);
+void SPI_InitFlash(void);
+
+void SPI_GetId(unsigned *id);
+
+#ifdef BOOT_BWCT
+#define FLASH_PAGE_SIZE 528
+#else
+#define FLASH_PAGE_SIZE 1056
+#endif
+
+// Flash commands
+
+#define CONTINUOUS_ARRAY_READ 0xE8
+#define CONTINUOUS_ARRAY_READ_HF 0x0B
+#define CONTINUOUS_ARRAY_READ_LF 0x03
+#define STATUS_REGISTER_READ 0xD7
+#define PROGRAM_THROUGH_BUFFER 0x82
+#define MANUFACTURER_ID 0x9F
+
+#endif
Property changes on: trunk/sys/boot/arm/at91/libat91/spi_flash.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
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## -0,0 +1 ##
+MidnightBSD=%H
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## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/strcmp.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/strcmp.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/strcmp.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,37 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "lib.h"
+
+int
+strcmp(const char *s1, const char *s2)
+{
+ for (; *s1 == *s2 && *s1; s1++, s2++);
+ return (unsigned char)*s1 - (unsigned char)*s2;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/strcmp.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/strcpy.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/strcpy.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/strcpy.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,39 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include "lib.h"
+
+char *
+strcpy(char *to, const char *from)
+{
+ while (*from)
+ *to++ = *from++;
+ *to++ = '\0';
+ return (to);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/strcpy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/strcvt.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/strcvt.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/strcvt.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,133 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/******************************************************************************
+ *
+ * Filename: p_string.c
+ *
+ * Instantiation of basic string operations to prevent inclusion of full
+ * string library. These are simple implementations not necessarily optimized
+ * for speed, but rather to show intent.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin minor updates
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *****************************************************************************/
+
+#include "lib.h"
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int p_IsWhiteSpace(char)
+ * This global function returns true if the character is not considered
+ * a non-space character.
+ * .KB_C_FN_DEFINITION_END
+ */
+int
+p_IsWhiteSpace(char cValue)
+{
+ return ((cValue == ' ') ||
+ (cValue == '\t') ||
+ (cValue == 0) ||
+ (cValue == '\r') ||
+ (cValue == '\n'));
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned p_HexCharValue(char)
+ * This global function returns the decimal value of the validated hex char.
+ * .KB_C_FN_DEFINITION_END
+ */
+unsigned
+p_HexCharValue(char cValue)
+{
+ if (cValue < ('9' + 1))
+ return (cValue - '0');
+ if (cValue < ('F' + 1))
+ return (cValue - 'A' + 10);
+ return (cValue - 'a' + 10);
+}
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned p_ASCIIToHex(char *)
+ * This global function set the unsigned value equal to the converted
+ * hex number passed as a string. No error checking is performed; the
+ * string must be valid hex value, point at the start of string, and be
+ * NULL-terminated.
+ * .KB_C_FN_DEFINITION_END
+ */
+unsigned
+p_ASCIIToHex(const char *buf)
+{
+ unsigned lValue = 0;
+
+ if ((*buf == '0') && ((buf[1] == 'x') || (buf[1] == 'X')))
+ buf += 2;
+
+ while (*buf) {
+ lValue <<= 4;
+ lValue += p_HexCharValue(*buf++);
+ }
+ return (lValue);
+}
+
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * unsigned p_ASCIIToDec(char *)
+ * This global function set the unsigned value equal to the converted
+ * decimal number passed as a string. No error checking is performed; the
+ * string must be valid decimal value, point at the start of string, and be
+ * NULL-terminated.
+ * .KB_C_FN_DEFINITION_END
+ */
+unsigned
+p_ASCIIToDec(const char *buf)
+{
+ unsigned v = 0;
+
+ while (*buf) {
+ v *= 10;
+ v += (*buf++) - '0';
+ }
+ return (v);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/strcvt.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/strlen.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/strlen.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/strlen.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,69 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/******************************************************************************
+ *
+ * Filename: p_string.c
+ *
+ * Instantiation of basic string operations to prevent inclusion of full
+ * string library. These are simple implementations not necessarily optimized
+ * for speed, but rather to show intent.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin minor updates
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *****************************************************************************/
+
+#include "lib.h"
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * int p_strlen(char *)
+ * This global function returns the number of bytes starting at the pointer
+ * before (not including) the string termination character ('/0').
+ * .KB_C_FN_DEFINITION_END
+ */
+int
+p_strlen(const char *buffer)
+{
+ const char *ptr = buffer;
+ while (*ptr++)
+ continue;
+ return (ptr - buffer - 1);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/strlen.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/tag_list.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/tag_list.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/tag_list.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,82 @@
+/* $MidnightBSD$ */
+/******************************************************************************
+ *
+ * Filename: tag_list.c
+ *
+ * Instantiation of basic routines that create linux-boot tag list.
+ *
+ * Revision information:
+ *
+ * 22AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ *****************************************************************************/
+
+/******************************* GLOBALS *************************************/
+
+/********************** PRIVATE FUNCTIONS/DATA/DEFINES ***********************/
+
+#define u32 unsigned
+#define u16 unsigned short
+#define u8 unsigned char
+
+// #include "/usr/src/arm/linux/include/asm/setup.h"
+#include <linux/asm/setup.h>
+#include "tag_list.h"
+
+#define PAGE_SIZE 0x1000
+#define MEM_SIZE 0x2000000
+#define PHYS_OFFSET 0x20000000
+
+/*************************** GLOBAL FUNCTIONS ********************************/
+
+/*
+ * .KB_C_FN_DEFINITION_START
+ * void InitTagList(char*, void *)
+ * This global function populates a linux-boot style tag list from the
+ * string passed in the pointer at the location specified.
+ * .KB_C_FN_DEFINITION_END
+ */
+void InitTagList(char *parms, void *output) {
+
+ char *src, *dst;
+ struct tag *tagList = (struct tag*)output;
+
+ tagList->hdr.size = tag_size(tag_core);
+ tagList->hdr.tag = ATAG_CORE;
+ tagList->u.core.flags = 1;
+ tagList->u.core.pagesize = PAGE_SIZE;
+ tagList->u.core.rootdev = 0xff;
+ tagList = tag_next(tagList);
+
+ tagList->hdr.size = tag_size(tag_mem32);
+ tagList->hdr.tag = ATAG_MEM;
+ tagList->u.mem.size = MEM_SIZE;
+ tagList->u.mem.start = PHYS_OFFSET;
+ tagList = tag_next(tagList);
+
+ tagList->hdr.size = tag_size(tag_cmdline);
+ tagList->hdr.tag = ATAG_CMDLINE;
+
+ src = parms;
+ dst = tagList->u.cmdline.cmdline;
+ while (*src) {
+ *dst++ = *src++;
+ }
+ *dst = 0;
+
+ tagList->hdr.size += ((unsigned)(src - parms) + 1) / sizeof(unsigned);
+ tagList = tag_next(tagList);
+
+ tagList->hdr.size = 0;
+ tagList->hdr.tag = ATAG_NONE;
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/tag_list.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/tag_list.h
===================================================================
--- trunk/sys/boot/arm/at91/libat91/tag_list.h (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/tag_list.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,29 @@
+/* $MidnightBSD$ */
+/*****************************************************************************
+ *
+ * Filename: tag_list.h
+ *
+ * Definition of basic routines that create linux-boot tag list.
+ *
+ * Revision information:
+ *
+ * 22AUG2004 kb_admin initial creation
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $FreeBSD$
+ ****************************************************************************/
+
+#ifndef _TAG_LIST_H_
+#define _TAG_LIST_H_
+
+extern void InitTagList(char *parms, void*);
+
+#endif /* _TAG_LIST_H_ */
Property changes on: trunk/sys/boot/arm/at91/libat91/tag_list.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/libat91/xmodem.c
===================================================================
--- trunk/sys/boot/arm/at91/libat91/xmodem.c (rev 0)
+++ trunk/sys/boot/arm/at91/libat91/xmodem.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,129 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2006 M. Warner Losh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This software is derived from software provide by Kwikbyte who specifically
+ * disclaimed copyright on the code. This version of xmodem has been nearly
+ * completely rewritten, but the CRC is from the original.
+ *
+ * $FreeBSD$
+ */
+
+#include "lib.h"
+
+#define PACKET_SIZE 128
+
+/* Line control codes */
+#define SOH 0x01 /* start of header */
+#define ACK 0x06 /* Acknowledge */
+#define NAK 0x15 /* Negative acknowledge */
+#define CAN 0x18 /* Cancel */
+#define EOT 0x04 /* end of text */
+
+#define TO 10
+/*
+ * int GetRecord(char , char *)
+ * This private function receives a x-modem record to the pointer and
+ * returns non-zero on success.
+ */
+static int
+GetRecord(char blocknum, char *dest)
+{
+ int size;
+ int ch;
+ unsigned chk, j;
+
+ chk = 0;
+
+ if ((ch = getc(TO)) == -1)
+ goto err;
+ if (ch != blocknum)
+ goto err;
+ if ((ch = getc(TO)) == -1)
+ goto err;
+ if (ch != (~blocknum & 0xff))
+ goto err;
+
+ for (size = 0; size < PACKET_SIZE; ++size) {
+ if ((ch = getc(TO)) == -1)
+ goto err;
+ chk = chk ^ ch << 8;
+ for (j = 0; j < 8; ++j) {
+ if (chk & 0x8000)
+ chk = chk << 1 ^ 0x1021;
+ else
+ chk = chk << 1;
+ }
+ *dest++ = ch;
+ }
+
+ chk &= 0xFFFF;
+
+ if (((ch = getc(TO)) == -1) || ((ch & 0xff) != ((chk >> 8) & 0xFF)))
+ goto err;
+ if (((ch = getc(TO)) == -1) || ((ch & 0xff) != (chk & 0xFF)))
+ goto err;
+ putchar(ACK);
+
+ return (1);
+err:;
+ putchar(CAN);
+ // We should allow for resend, but we don't.
+ return (0);
+}
+
+/*
+ * int xmodem_rx(char *)
+ * This global function receives a x-modem transmission consisting of
+ * (potentially) several blocks. Returns the number of bytes received or
+ * -1 on error.
+ */
+int
+xmodem_rx(char *dest)
+{
+ int starting, ch;
+ char packetNumber, *startAddress = dest;
+
+ packetNumber = 1;
+ starting = 1;
+
+ while (1) {
+ if (starting)
+ putchar('C');
+ if (((ch = getc(1)) == -1) || (ch != SOH && ch != EOT))
+ continue;
+ if (ch == EOT) {
+ putchar(ACK);
+ return (dest - startAddress);
+ }
+ starting = 0;
+ // Xmodem packets: SOH PKT# ~PKT# 128-bytes CRC16
+ if (!GetRecord(packetNumber, dest))
+ return (-1);
+ dest += PACKET_SIZE;
+ packetNumber++;
+ }
+
+ // the loop above should return in all cases
+ return (-1);
+}
Property changes on: trunk/sys/boot/arm/at91/libat91/xmodem.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/at91/linker.cfg
===================================================================
--- trunk/sys/boot/arm/at91/linker.cfg (rev 0)
+++ trunk/sys/boot/arm/at91/linker.cfg 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,288 @@
+/*******************************************************************************
+ *
+ * Filename: linker.cfg
+ *
+ * linker config file used for internal RAM or eeprom images at address 0.
+ *
+ * Revision information:
+ *
+ * 20AUG2004 kb_admin initial creation
+ * 12JAN2005 kb_admin move data to SDRAM
+ *
+ * BEGIN_KBDD_BLOCK
+ * No warranty, expressed or implied, is included with this software. It is
+ * provided "AS IS" and no warranty of any kind including statutory or aspects
+ * relating to merchantability or fitness for any purpose is provided. All
+ * intellectual property rights of others is maintained with the respective
+ * owners. This software is not copyrighted and is intended for reference
+ * only.
+ * END_BLOCK
+ *
+ * $MidnightBSD$
+ ******************************************************************************/
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+ "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(start)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = 0;
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ *(.stub)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7t) *(.glue_7)
+ }
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.text :
+ {
+ *(.rel.text)
+ *(.rel.text.*)
+ *(.rel.gnu.linkonce.t.*)
+ }
+ .rela.text :
+ {
+ *(.rela.text)
+ *(.rela.text.*)
+ *(.rela.gnu.linkonce.t.*)
+ }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.rodata :
+ {
+ *(.rel.rodata)
+ *(.rel.rodata.*)
+ *(.rel.gnu.linkonce.r.*)
+ }
+ .rela.rodata :
+ {
+ *(.rela.rodata)
+ *(.rela.rodata.*)
+ *(.rela.gnu.linkonce.r.*)
+ }
+ .rel.data :
+ {
+ *(.rel.data)
+ *(.rel.data.*)
+ *(.rel.gnu.linkonce.d.*)
+ }
+ .rela.data :
+ {
+ *(.rela.data)
+ *(.rela.data.*)
+ *(.rela.gnu.linkonce.d.*)
+ }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.sdata :
+ {
+ *(.rel.sdata)
+ *(.rel.sdata.*)
+ *(.rel.gnu.linkonce.s.*)
+ }
+ .rela.sdata :
+ {
+ *(.rela.sdata)
+ *(.rela.sdata.*)
+ *(.rela.gnu.linkonce.s.*)
+ }
+ .rel.sbss :
+ {
+ *(.rel.sbss)
+ *(.rel.sbss.*)
+ *(.rel.gnu.linkonce.sb.*)
+ }
+ .rela.sbss :
+ {
+ *(.rela.sbss)
+ *(.rela.sbss.*)
+ *(.rel.gnu.linkonce.sb.*)
+ }
+ .rel.sdata2 :
+ {
+ *(.rel.sdata2)
+ *(.rel.sdata2.*)
+ *(.rel.gnu.linkonce.s2.*)
+ }
+ .rela.sdata2 :
+ {
+ *(.rela.sdata2)
+ *(.rela.sdata2.*)
+ *(.rela.gnu.linkonce.s2.*)
+ }
+ .rel.sbss2 :
+ {
+ *(.rel.sbss2)
+ *(.rel.sbss2.*)
+ *(.rel.gnu.linkonce.sb2.*)
+ }
+ .rela.sbss2 :
+ {
+ *(.rela.sbss2)
+ *(.rela.sbss2.*)
+ *(.rela.gnu.linkonce.sb2.*)
+ }
+ .rel.bss :
+ {
+ *(.rel.bss)
+ *(.rel.bss.*)
+ *(.rel.gnu.linkonce.b.*)
+ }
+ .rela.bss :
+ {
+ *(.rela.bss)
+ *(.rela.bss.*)
+ *(.rela.gnu.linkonce.b.*)
+ }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init :
+ {
+ KEEP (*(.init))
+ } =0
+ .plt : { *(.plt) }
+ .fini :
+ {
+ KEEP (*(.fini))
+ } =0
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) }
+ .rodata1 : { *(.rodata1) }
+ .sdata2 : { *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) }
+ .sbss2 : { *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) }
+ .data :
+ {
+ __data_start = . ;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ }
+ .data1 : { *(.data1) }
+ . = 0x21200000;
+ .eh_frame : { KEEP (*(.eh_frame)) }
+ .gcc_except_table : { *(.gcc_except_table) }
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ }
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ }
+ .got : { *(.got.plt) *(.got) }
+ .dynamic : { *(.dynamic) }
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata :
+ {
+ *(.sdata)
+ *(.sdata.*)
+ *(.gnu.linkonce.s.*)
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ __bss_start__ = .;
+ .sbss :
+ {
+ PROVIDE (__sbss_start = .);
+ PROVIDE (___sbss_start = .);
+ *(.dynsbss)
+ *(.sbss)
+ *(.sbss.*)
+ *(.gnu.linkonce.sb.*)
+ *(.scommon)
+ PROVIDE (__sbss_end = .);
+ PROVIDE (___sbss_end = .);
+ }
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections. */
+ . = ALIGN(32 / 8);
+ }
+ . = ALIGN(32 / 8);
+ _end = .;
+ _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+ PROVIDE (end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* These must appear regardless of . */
+}
Property changes on: trunk/sys/boot/arm/at91/linker.cfg
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/Makefile.inc
===================================================================
--- trunk/sys/boot/arm/ixp425/Makefile.inc (rev 0)
+++ trunk/sys/boot/arm/ixp425/Makefile.inc 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,42 @@
+# $MidnightBSD$
+
+.if !target(__ixp425_boot_Makefile.inc__)
+.PATH: ${.CURDIR}/../../../../libkern ${.CURDIR}/../../../../libkern/arm
+
+__ixp425_boot_Makefile.inc__:
+
+# Both Avila and Pronghorn Metro are supported by ixp425
+BOOT_FLAVOR=ixp425
+
+CFLAGS+=-Os -ffreestanding \
+ -I${.CURDIR}/../../../.. \
+ -I${.CURDIR}/../../../../arm \
+ -DCPU_XSCALE_IXP425 \
+ -Wall -Waggregate-return \
+ -Werror \
+ -Wnested-externs \
+ -Wpointer-arith -Wshadow -Wwrite-strings \
+ -Wmissing-prototypes \
+ -Wmissing-declarations
+
+# -Wstrict-prototypes
+
+CFLAGS+=-DBOOT_${BOOT_FLAVOR:U}
+
+LD ?= ld
+OBJCOPY ?= objcopy
+
+.if defined(P)
+${P}: ${OBJS}
+ ${LD} ${LDFLAGS} -o ${.TARGET} ${OBJS}
+
+CLEANFILES+= ${P}
+.endif
+
+.if defined(WITH_TAG_LIST)
+MK_TAG_LIST:=yes
+.else
+MK_TAG_LIST:=no
+.endif
+
+.endif
Property changes on: trunk/sys/boot/arm/ixp425/Makefile.inc
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/Makefile
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/Makefile (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,75 @@
+# $MidnightBSD$
+
+# We get a lot of the std lib functions from here.
+.PATH: ${.CURDIR}/../../at91/libat91
+
+# Enable to get debug msgs
+#DEBUG=yes
+
+# Hack to search through the kernel for ufs:ad0s1a and replace it with
+# the correct one for the active slice/partition.
+FIXUP_BOOT_DRV=yes
+
+P=boot2
+FILES=${P}
+SRCS=arm_init.S boot2.c ${BOOT_FLAVOR:L}_board.c
+SRCS+=memchr.c memcmp.c memcpy.c memmem.c memset.c printf.c strcmp.c strcpy.c
+SRCS+=strlen.c ashldi3.c divsi3.S muldi3.c
+NO_MAN=
+
+KERNPHYSADDR=0x180000
+KERNVIRTADDR=${KERNPHYSADDR}
+BOOT_STACK=0x200000-4
+M=${MACHINE}
+LDFLAGS=-e ${KERNPHYSADDR} -EB -T ldscript.${M}
+OBJS+= ${SRCS:N*.h:R:S/$/.o/g}
+S=${.CURDIR}/../../../..
+
+CFLAGS+= \
+ -DBOOT_STACK=${BOOT_STACK} \
+ -I${.CURDIR}/../../../common \
+ -I${.CURDIR}
+
+.if defined(FIXUP_BOOT_DRV)
+CFLAGS+=-DFIXUP_BOOT_DRV
+.endif
+.if defined(DEBUG)
+CFLAGS+=-DDEBUG
+.endif
+
+ldscript.$M: $S/conf/ldscript.$M
+ cat $S/conf/ldscript.$M|sed s/KERNPHYSADDR/${KERNPHYSADDR}/g| \
+ sed s/KERNVIRTADDR/${KERNVIRTADDR}/g | \
+ sed s/" + SIZEOF_HEADERS"// > ldscript.$M
+
+${P}: ldscript.$M
+
+CLEANFILES+=ldscript.$M
+
+memchr.c: $S/../lib/libc/string/memchr.c
+ sed -e 's/string\.h/lib.h/' < $S/../lib/libc/string/memchr.c > \
+ ${.TARGET}
+
+memmem.c: $S/../lib/libc/string/memmem.c
+ sed -e 's/string\.h/lib.h/' < $S/../lib/libc/string/memmem.c > \
+ ${.TARGET}
+
+CLEANFILES+=memchr.c memmem.c
+
+ashldi3.o: $S/libkern/ashldi3.c
+ ${CC} -c ${CFLAGS} -D_KERNEL -o ${.TARGET} ${.IMPSRC}
+
+divsi3.o: $S/libkern/${M}/divsi3.S
+ ${CC} -c ${CFLAGS} -D_KERNEL -o ${.TARGET} ${.IMPSRC}
+
+muldi3.o: $S/libkern/${M}/muldi3.c
+ ${CC} -c ${CFLAGS} -D_KERNEL -o ${.TARGET} ${.IMPSRC}
+
+inflate.c: $S/kern/inflate.c
+ sed -e 's/extern void putstr (char/extern void putstr (const char/' < \
+ $S/kern/inflate.c > ${.TARGET}
+
+CLEANFILES+=inflate.c
+
+.include <bsd.prog.mk>
+
Property changes on: trunk/sys/boot/arm/ixp425/boot2/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/arm_init.S
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/arm_init.S (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/arm_init.S 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,56 @@
+/*-
+ * Copyright (c) 2008 John Hay. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $MidnightBSD$
+ */
+
+#include <machine/asm.h>
+
+ASENTRY_NP(start)
+/* Initialise bss and sp */
+ nop
+ adr r1, .Lstart
+ ldmia r1, {r1, r2, sp} /* Set initial stack and */
+ sub r2, r2, r1 /* get zero init data */
+ mov r3, #0
+.L1:
+ str r3, [r1], #0x0004 /* get zero init data */
+ subs r2, r2, #4
+ bgt .L1
+
+ .extern main
+ bl main
+/* main should not return. If it does, spin forever */
+infiniteLoop:
+ b infiniteLoop
+
+.Lstart:
+ .word _edata
+ .word _end
+ .word BOOT_STACK
+
+ENTRY(cpu_id)
+ mrc p15, 0, r0, c0, c0, 0
+ RET
+
+/* End */
Property changes on: trunk/sys/boot/arm/ixp425/boot2/arm_init.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/boot2.c
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/boot2.c (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/boot2.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,486 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 John Hay
+ * Copyright (c) 1998 Robert Nordier
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/disklabel.h>
+#include <sys/diskmbr.h>
+#include <sys/dirent.h>
+#include <sys/reboot.h>
+
+#include <machine/elf.h>
+
+#include <stdarg.h>
+
+#include "lib.h"
+
+#define RBX_ASKNAME 0x0 /* -a */
+#define RBX_SINGLE 0x1 /* -s */
+/* 0x2 is reserved for log2(RB_NOSYNC). */
+/* 0x3 is reserved for log2(RB_HALT). */
+/* 0x4 is reserved for log2(RB_INITNAME). */
+#define RBX_DFLTROOT 0x5 /* -r */
+/* #define RBX_KDB 0x6 -d */
+/* 0x7 is reserved for log2(RB_RDONLY). */
+/* 0x8 is reserved for log2(RB_DUMP). */
+/* 0x9 is reserved for log2(RB_MINIROOT). */
+#define RBX_CONFIG 0xa /* -c */
+#define RBX_VERBOSE 0xb /* -v */
+/* #define RBX_SERIAL 0xc -h */
+/* #define RBX_CDROM 0xd -C */
+/* 0xe is reserved for log2(RB_POWEROFF). */
+#define RBX_GDB 0xf /* -g */
+/* #define RBX_MUTE 0x10 -m */
+/* 0x11 is reserved for log2(RB_SELFTEST). */
+/* 0x12 is reserved for boot programs. */
+/* 0x13 is reserved for boot programs. */
+/* #define RBX_PAUSE 0x14 -p */
+/* #define RBX_QUIET 0x15 -q */
+#define RBX_NOINTR 0x1c /* -n */
+/* 0x1d is reserved for log2(RB_MULTIPLE) and is just misnamed here. */
+/* #define RBX_DUAL 0x1d -D */
+/* 0x1f is reserved for log2(RB_BOOTINFO). */
+
+/* pass: -a, -s, -r, -v, -g */
+#define RBX_MASK (OPT_SET(RBX_ASKNAME) | OPT_SET(RBX_SINGLE) | \
+ OPT_SET(RBX_DFLTROOT) | \
+ OPT_SET(RBX_VERBOSE) | \
+ OPT_SET(RBX_GDB))
+
+#define PATH_DOTCONFIG "/boot.config"
+#define PATH_CONFIG "/boot/config"
+#define PATH_KERNEL "/boot/kernel/kernel"
+
+extern uint32_t _end;
+
+#define NOPT 6
+
+#define OPT_SET(opt) (1 << (opt))
+#define OPT_CHECK(opt) ((opts) & OPT_SET(opt))
+
+static const char optstr[NOPT] = "agnrsv";
+static const unsigned char flags[NOPT] = {
+ RBX_ASKNAME,
+ RBX_GDB,
+ RBX_NOINTR,
+ RBX_DFLTROOT,
+ RBX_SINGLE,
+ RBX_VERBOSE
+};
+
+static unsigned dsk_start;
+static char cmd[512];
+static char kname[1024];
+static uint32_t opts;
+static uint8_t dsk_meta;
+static int bootslice;
+static int bootpart;
+static int disk_layout;
+#define DL_UNKNOWN 0
+#define DL_RAW 1 /* Dangerously dedicated */
+#define DL_SLICE 2 /* Use only slices (DOS partitions) */
+#define DL_SLICEPART 3 /* Use slices and partitions */
+
+static void load(void);
+static int parse(void);
+static int xfsread(ino_t, void *, size_t);
+static int dskread(void *, unsigned, unsigned);
+static int drvread(void *, unsigned, unsigned);
+#ifdef FIXUP_BOOT_DRV
+static void fixup_boot_drv(caddr_t, int, int, int);
+#endif
+
+#include "ufsread.c"
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) printf(fmt, __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+static inline int
+xfsread(ino_t inode, void *buf, size_t nbyte)
+{
+ if ((size_t)fsread(inode, buf, nbyte) != nbyte)
+ return -1;
+ return 0;
+}
+
+static inline void
+getstr(int c)
+{
+ char *s;
+
+ s = cmd;
+ if (c == 0)
+ c = getc(10000);
+ for (;;) {
+ switch (c) {
+ case 0:
+ break;
+ case '\177':
+ case '\b':
+ if (s > cmd) {
+ s--;
+ printf("\b \b");
+ }
+ break;
+ case '\n':
+ case '\r':
+ *s = 0;
+ return;
+ default:
+ if (s - cmd < sizeof(cmd) - 1)
+ *s++ = c;
+ xputchar(c);
+ }
+ c = getc(10000);
+ }
+}
+
+int
+main(void)
+{
+ const char *bt;
+ int autoboot, c = 0;
+ ino_t ino;
+
+ dmadat = (void *)(0x1c0000);
+ p_memset((char *)dmadat, 0, 32 * 1024);
+ bt = board_init();
+
+ printf("FreeBSD ARM (%s) boot2 v%d.%d\n", bt, 0, 4);
+
+ autoboot = 1;
+
+ /* Process configuration file */
+ if ((ino = lookup(PATH_CONFIG)) ||
+ (ino = lookup(PATH_DOTCONFIG)))
+ fsread(ino, cmd, sizeof(cmd));
+
+ if (*cmd) {
+ if (parse())
+ autoboot = 0;
+ printf("%s: %s\n", PATH_CONFIG, cmd);
+ /* Do not process this command twice */
+ *cmd = 0;
+ }
+
+ if (*kname == '\0')
+ strcpy(kname, PATH_KERNEL);
+
+ /* Present the user with the boot2 prompt. */
+ for (;;) {
+ printf("\nDefault: %s\nboot: ", kname);
+ if (!autoboot ||
+ (OPT_CHECK(RBX_NOINTR) == 0 && (c = getc(2)) != 0))
+ getstr(c);
+ xputchar('\n');
+ autoboot = 0;
+ c = 0;
+ DPRINTF("cmd is '%s'\n", cmd);
+ if (parse())
+ xputchar('\a');
+ else
+ load();
+ }
+}
+
+static void
+load(void)
+{
+ Elf32_Ehdr eh;
+ static Elf32_Phdr ep[2];
+ caddr_t p;
+ ino_t ino;
+ uint32_t addr;
+ int i, j;
+#ifdef FIXUP_BOOT_DRV
+ caddr_t staddr;
+ int klen;
+
+ staddr = (caddr_t)0xffffffff;
+ klen = 0;
+#endif
+ if (!(ino = lookup(kname))) {
+ if (!ls)
+ printf("No %s\n", kname);
+ return;
+ }
+ DPRINTF("Found %s\n", kname);
+ if (xfsread(ino, &eh, sizeof(eh)))
+ return;
+ if (!IS_ELF(eh)) {
+ printf("Invalid %s\n", "format");
+ return;
+ }
+ fs_off = eh.e_phoff;
+ for (j = i = 0; i < eh.e_phnum && j < 2; i++) {
+ if (xfsread(ino, ep + j, sizeof(ep[0])))
+ return;
+ if (ep[j].p_type == PT_LOAD)
+ j++;
+ }
+ for (i = 0; i < 2; i++) {
+ p = (caddr_t)(ep[i].p_paddr & 0x0fffffff);
+ fs_off = ep[i].p_offset;
+#ifdef FIXUP_BOOT_DRV
+ if (staddr == (caddr_t)0xffffffff)
+ staddr = p;
+ klen += ep[i].p_filesz;
+#endif
+ if (xfsread(ino, p, ep[i].p_filesz))
+ return;
+ }
+ addr = eh.e_entry & 0x0fffffff;
+ DPRINTF("Entry point %x for %s\n", addr, kname);
+ clr_board();
+#ifdef FIXUP_BOOT_DRV
+ fixup_boot_drv(staddr, klen, bootslice, bootpart);
+#endif
+ ((void(*)(int))addr)(RB_BOOTINFO /* XXX | (opts & RBX_MASK) */);
+}
+
+static int
+parse()
+{
+ char *arg = cmd;
+ char *ep, *p;
+ int c, i;
+
+ while ((c = *arg++)) {
+ if (c == ' ' || c == '\t' || c == '\n')
+ continue;
+ for (p = arg; *p && *p != '\n' && *p != ' ' && *p != '\t'; p++);
+ ep = p;
+ if (*p)
+ *p++ = 0;
+ if (c == '-') {
+ while ((c = *arg++)) {
+ for (i = 0; c != optstr[i]; i++)
+ if (i == NOPT - 1)
+ return -1;
+ opts ^= OPT_SET(flags[i]);
+ }
+ } else {
+ arg--;
+ /* look for ad0s1a:... | ad0s1:... */
+ if (strlen(arg) > 6 && arg[0] == 'a' &&
+ arg[1] == 'd' && arg[3] == 's' &&
+ (arg[5] == ':' || arg[6] == ':')) {
+ /* XXX Should also handle disk. */
+ bootslice = arg[4] - '0';
+ if (bootslice < 1 || bootslice > 4)
+ return (-1);
+ bootpart = 0;
+ if (arg[5] != ':')
+ bootpart = arg[5] - 'a';
+ if (bootpart < 0 || bootpart > 7)
+ return (-1);
+ dsk_meta = 0;
+ if (arg[5] == ':')
+ arg += 6;
+ else
+ arg += 7;
+ /* look for ad0a:... */
+ } else if (strlen(arg) > 4 && arg[0] == 'a' &&
+ arg[1] == 'd' && arg[2] == '0' && arg[4] == ':') {
+ bootslice = 0;
+ bootpart = arg[3] - 'a';
+ if (bootpart < 0 || bootpart > 7)
+ return (-1);
+ dsk_meta = 0;
+ arg += 5;
+ }
+ if ((i = ep - arg)) {
+ if ((size_t)i >= sizeof(kname))
+ return -1;
+ memcpy(kname, arg, i + 1);
+ }
+ }
+ arg = p;
+ }
+ return 0;
+}
+
+/*
+ * dskread() will try to handle the disk layouts that are typically
+ * encountered.
+ * - raw or "Dangerously Dedicated" mode. No real slice table, just the
+ * default one that is included with bsdlabel -B. Typically this is
+ * used with ROOTDEVNAME=\"ufs:ad0a\".
+ * - slice only. Only a slice table is installed with no bsd label or
+ * bsd partition table. This is typically used with
+ * ROOTDEVNAME=\"ufs:ad0s1\".
+ * - slice + bsd label + partition table. This is typically done with
+ * with fdisk + bsdlabel and is used with ROOTDEVNAME=\"ufs:ad0s1a\".
+ */
+static int
+dskread(void *buf, unsigned lba, unsigned nblk)
+{
+ struct dos_partition *dp;
+ struct disklabel *d;
+ char *sec;
+ int i;
+
+ if (!dsk_meta) {
+ sec = dmadat->secbuf;
+ dsk_start = 0;
+ if (drvread(sec, DOSBBSECTOR, 1))
+ return -1;
+ dp = (void *)(sec + DOSPARTOFF);
+ if (bootslice != 0) {
+ i = bootslice - 1;
+ if (dp[i].dp_typ != DOSPTYP_386BSD)
+ return -1;
+ } else {
+ for (i = 0; i < NDOSPART; i++) {
+ if ((dp[i].dp_typ == DOSPTYP_386BSD) &&
+ (dp[i].dp_flag == 0x80))
+ break;
+ }
+ }
+ if (i != NDOSPART) {
+ bootslice = i + 1;
+ DPRINTF("Found an active fbsd slice. (%d)\n", i + 1);
+ /*
+ * Although dp_start is aligned within the disk
+ * partition structure, DOSPARTOFF is 446, which
+ * is only word (2) aligned, not longword (4)
+ * aligned. Cope by using memcpy to fetch the
+ * start of this partition.
+ */
+ memcpy(&dsk_start, &dp[i].dp_start, 4);
+ dsk_start = swap32(dsk_start);
+ DPRINTF("dsk_start %x\n", dsk_start);
+ if ((bootslice == 4) && (dsk_start == 0)) {
+ disk_layout = DL_RAW;
+ bootslice = 0;
+ }
+ }
+ if (drvread(sec, dsk_start + LABELSECTOR, 1))
+ return -1;
+ d = (void *)(sec + LABELOFFSET);
+ if ((d->d_magic == DISKMAGIC && d->d_magic2 == DISKMAGIC) ||
+ (swap32(d->d_magic) == DISKMAGIC &&
+ swap32(d->d_magic2) == DISKMAGIC)) {
+ DPRINTF("p_size = %x\n",
+ !d->d_partitions[bootpart].p_size);
+ if (!d->d_partitions[bootpart].p_size) {
+ printf("Invalid partition\n");
+ return -1;
+ }
+ DPRINTF("p_offset %x, RAW %x\n",
+ swap32(d->d_partitions[bootpart].p_offset),
+ swap32(d->d_partitions[RAW_PART].p_offset));
+ dsk_start += swap32(d->d_partitions[bootpart].p_offset);
+ dsk_start -= swap32(d->d_partitions[RAW_PART].p_offset);
+ if ((disk_layout == DL_UNKNOWN) && (bootslice == 0))
+ disk_layout = DL_RAW;
+ else if (disk_layout == DL_UNKNOWN)
+ disk_layout = DL_SLICEPART;
+ } else {
+ disk_layout = DL_SLICE;
+ DPRINTF("Invalid %s\n", "label");
+ }
+ DPRINTF("bootslice %d, bootpart %d, dsk_start %u\n", bootslice,
+ bootpart, dsk_start);
+ dsk_meta++;
+ }
+ return drvread(buf, dsk_start + lba, nblk);
+}
+
+static int
+drvread(void *buf, unsigned lba, unsigned nblk)
+{
+ static unsigned c = 0x2d5c7c2f;
+
+ printf("%c\b", c = c << 8 | c >> 24);
+ return (avila_read((char *)buf, lba, nblk));
+}
+
+#ifdef FIXUP_BOOT_DRV
+/*
+ * fixup_boot_drv() will try to find the ROOTDEVNAME spec in the kernel
+ * and change it to what was specified on the comandline or /boot.conf
+ * file or to what was encountered on the disk. It will try to handle 3
+ * different disk layouts, raw (dangerously dedicated), slice only and
+ * slice + partition. It will look for the following strings in the
+ * kernel, but if it is one of the first three, the string in the kernel
+ * must use the correct form to match the actual disk layout:
+ * - ufs:ad0a
+ * - ufs:ad0s1
+ * - ufs:ad0s1a
+ * - ufs:ROOTDEVNAME
+ * In the case of the first three strings, only the "a" at the end and
+ * the "1" after the "s" will be modified, if they exist. The string
+ * length will not be changed. In the case of the last string, the
+ * whole string will be built up and nul, '\0' terminated.
+ */
+static void
+fixup_boot_drv(caddr_t addr, int klen, int bs, int bp)
+{
+ const u_int8_t op[] = "ufs:ROOTDEVNAME";
+ const u_int8_t op2[] = "ufs:ad0";
+ u_int8_t *p, *ps;
+
+ DPRINTF("fixup_boot_drv: 0x%x, %d, slice %d, partition %d\n",
+ (int)addr, klen, bs, bp);
+ if (bs > 4)
+ return;
+ if (bp > 7)
+ return;
+ ps = memmem(addr, klen, op, sizeof(op));
+ if (ps != NULL) {
+ p = ps + 4; /* past ufs: */
+ DPRINTF("Found it at 0x%x\n", (int)ps);
+ p[0] = 'a'; p[1] = 'd'; p[2] = '0'; /* ad0 */
+ p += 3;
+ if (bs > 0) {
+ /* append slice */
+ *p++ = 's';
+ *p++ = bs + '0';
+ }
+ if (disk_layout != DL_SLICE) {
+ /* append partition */
+ *p++ = bp + 'a';
+ }
+ *p = '\0';
+ } else {
+ ps = memmem(addr, klen, op2, sizeof(op2) - 1);
+ if (ps != NULL) {
+ p = ps + sizeof(op2) - 1;
+ DPRINTF("Found it at 0x%x\n", (int)ps);
+ if (*p == 's') {
+ /* fix slice */
+ p++;
+ *p++ = bs + '0';
+ }
+ if (*p == 'a')
+ *p = bp + 'a';
+ }
+ }
+ if (ps == NULL) {
+ printf("Could not locate \"%s\" to fix kernel boot device, "
+ "check ROOTDEVNAME is set\n", op);
+ return;
+ }
+ DPRINTF("Changed boot device to %s\n", ps);
+}
+#endif
Property changes on: trunk/sys/boot/arm/ixp425/boot2/boot2.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/cf_ata.h
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/cf_ata.h (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/cf_ata.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,63 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 John Hay. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef ARM_BOOT_CF_ATA_H
+#define ARM_BOOT_CF_ATA_H
+
+#define CF_DATA 0x00
+#define CF_ERROR 0x01
+#define CF_FEATURE 0x01
+#define CF_SECT_CNT 0x02
+#define CF_SECT_NUM 0x03
+#define CF_CYL_L 0x04
+#define CF_CYL_H 0x05
+#define CF_DRV_HEAD 0x06
+#define CF_D_MASTER 0x00
+#define CF_D_LBA 0x40
+#define CF_D_IBM 0xa0
+#define CF_STATUS 0x07
+#define CF_S_ERROR 0x01
+#define CF_S_INDEX 0x02
+#define CF_S_CORR 0x04
+#define CF_S_DRQ 0x08
+#define CF_S_DSC 0x10
+#define CF_S_DWF 0x20
+#define CF_S_READY 0x40
+#define CF_S_BUSY 0x80
+#define CF_COMMAND 0x07
+
+/* This is according to the appnote, but Sam use 0x1e in avila_ata.c */
+#define CF_ALT_STATUS 0x16
+#define CF_ALT_DEV_CTR 0x16
+#define CF_ALT_DEV_CTR2 0x1e
+#define CF_A_IDS 0x02
+#define CF_A_RESET 0x04
+#define CF_A_4BIT 0x08
+
+#define AVILA_IDE_GPIN 12
+
+#endif /* !ARM_BOOT_CF_ATA_H */
Property changes on: trunk/sys/boot/arm/ixp425/boot2/cf_ata.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/ixp425_board.c
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/ixp425_board.c (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/ixp425_board.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,772 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 John Hay. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <sys/param.h>
+#include <sys/ata.h>
+#include <sys/linker_set.h>
+
+#include <stdarg.h>
+
+#include "lib.h"
+#include "cf_ata.h"
+
+#include <machine/armreg.h>
+#include <arm/xscale/ixp425/ixp425reg.h>
+#include <dev/ic/ns16550.h>
+
+struct board_config {
+ const char *desc;
+ int (*probe)(int boardtype_hint);
+ void (*init)(void);
+};
+/* set of registered boards */
+SET_DECLARE(boards, struct board_config);
+#define BOARD_CONFIG(name, _desc) \
+static struct board_config name##config = { \
+ .desc = _desc, \
+ .probe = name##_probe, \
+ .init = name##_init, \
+}; \
+DATA_SET(boards, name##config)
+
+static u_int cputype;
+#define cpu_is_ixp43x() (cputype == CPU_ID_IXP435)
+static u_int8_t *ubase;
+
+static u_int8_t uart_getreg(u_int8_t *, int);
+static void uart_setreg(u_int8_t *, int, u_int8_t);
+
+static void cf_init(void);
+static void cf_clr(void);
+
+#ifdef DEBUG
+#define DPRINTF(fmt, ...) printf(fmt, __VA_ARGS__)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+const char *
+board_init(void)
+{
+ struct board_config **pbp;
+
+ cputype = cpu_id() & CPU_ID_CPU_MASK;
+
+ SET_FOREACH(pbp, boards)
+ /* XXX pass down redboot board type */
+ if ((*pbp)->probe(0)) {
+ (*pbp)->init();
+ return (*pbp)->desc;
+ }
+ /* XXX panic, unknown board type */
+ return "???";
+}
+
+/*
+ * This should be called just before starting the kernel. This is so
+ * that one can undo incompatible hardware settings.
+ */
+void
+clr_board(void)
+{
+ cf_clr();
+}
+
+/*
+ * General support functions.
+ */
+
+/*
+ * DELAY should delay for the number of microseconds.
+ * The idea is that the inner loop should take 1us, so val is the
+ * number of usecs to delay.
+ */
+void
+DELAY(int val)
+{
+ volatile int sub;
+ volatile int subsub;
+
+ sub = val;
+ while(sub) {
+ subsub = 3;
+ while(subsub)
+ subsub--;
+ sub--;
+ }
+}
+
+u_int32_t
+swap32(u_int32_t a)
+{
+ return (((a & 0xff) << 24) | ((a & 0xff00) << 8) |
+ ((a & 0xff0000) >> 8) | ((a & 0xff000000) >> 24));
+}
+
+u_int16_t
+swap16(u_int16_t val)
+{
+ return (val << 8) | (val >> 8);
+}
+
+/*
+ * uart related funcs
+ */
+static u_int8_t
+uart_getreg(u_int8_t *bas, int off)
+{
+ return *((volatile u_int32_t *)(bas + (off << 2))) & 0xff;
+}
+
+static void
+uart_setreg(u_int8_t *bas, int off, u_int8_t val)
+{
+ *((volatile u_int32_t *)(bas + (off << 2))) = (u_int32_t)val;
+}
+
+int
+getc(int seconds)
+{
+ int c, delay, limit;
+
+ c = 0;
+ delay = 10000;
+ limit = seconds * 1000000/10000;
+ while ((uart_getreg(ubase, REG_LSR) & LSR_RXRDY) == 0 && --limit)
+ DELAY(delay);
+
+ if ((uart_getreg(ubase, REG_LSR) & LSR_RXRDY) == LSR_RXRDY)
+ c = uart_getreg(ubase, REG_DATA);
+
+ return c;
+}
+
+void
+putchar(int ch)
+{
+ int delay, limit;
+
+ delay = 500;
+ limit = 20;
+ while ((uart_getreg(ubase, REG_LSR) & LSR_THRE) == 0 && --limit)
+ DELAY(delay);
+ uart_setreg(ubase, REG_DATA, ch);
+
+ limit = 40;
+ while ((uart_getreg(ubase, REG_LSR) & LSR_TEMT) == 0 && --limit)
+ DELAY(delay);
+}
+
+void
+xputchar(int ch)
+{
+ if (ch == '\n')
+ putchar('\r');
+ putchar(ch);
+}
+
+void
+putstr(const char *str)
+{
+ while(*str)
+ xputchar(*str++);
+}
+
+void
+puthex8(u_int8_t ch)
+{
+ const char *hex = "0123456789abcdef";
+
+ putchar(hex[ch >> 4]);
+ putchar(hex[ch & 0xf]);
+}
+
+void
+puthexlist(const u_int8_t *str, int length)
+{
+ while(length) {
+ puthex8(*str);
+ putchar(' ');
+ str++;
+ length--;
+ }
+}
+
+/*
+ *
+ * CF/IDE functions.
+ *
+ */
+
+struct {
+ u_int64_t dsize;
+ u_int64_t total_secs;
+ u_int8_t heads;
+ u_int8_t sectors;
+ u_int32_t cylinders;
+
+ u_int32_t *cs1to;
+ u_int32_t *cs2to;
+
+ u_int8_t *cs1;
+ u_int8_t *cs2;
+
+ u_int32_t use_lba;
+ u_int32_t use_stream8;
+ u_int32_t debug;
+
+ u_int8_t status;
+ u_int8_t error;
+} dskinf;
+
+static void cfenable16(void);
+static void cfdisable16(void);
+static u_int8_t cfread8(u_int32_t off);
+static u_int16_t cfread16(u_int32_t off);
+static void cfreadstream8(void *buf, int length);
+static void cfreadstream16(void *buf, int length);
+static void cfwrite8(u_int32_t off, u_int8_t val);
+static u_int8_t cfaltread8(u_int32_t off);
+static void cfaltwrite8(u_int32_t off, u_int8_t val);
+static int cfwait(u_int8_t mask);
+static int cfaltwait(u_int8_t mask);
+static int cfcmd(u_int32_t cmd, u_int32_t cylinder, u_int32_t head,
+ u_int32_t sector, u_int32_t count, u_int32_t feature);
+static void cfreset(void);
+#ifdef DEBUG
+static int cfgetparams(void);
+#endif
+static void cfprintregs(void);
+
+static void
+cf_init(void)
+{
+ u_int8_t status;
+#ifdef DEBUG
+ int rval;
+#endif
+
+ /* NB: board init routines setup other parts of dskinf */
+ dskinf.use_stream8 = 0;
+ dskinf.use_lba = 0;
+ dskinf.debug = 1;
+
+ DPRINTF("cs1 %x, cs2 %x\n", dskinf.cs1, dskinf.cs2);
+
+ /* Setup the CF window */
+ *dskinf.cs1to |= (EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
+ DPRINTF("t1 %x, ", *dskinf.cs1to);
+
+ *dskinf.cs2to |= (EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
+ DPRINTF("t2 %x\n", *dskinf.cs2to);
+
+ /* Detect if there is a disk. */
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1000);
+ status = cfread8(CF_STATUS);
+ if (status != 0x50)
+ printf("cf-ata0 %x\n", (u_int32_t)status);
+ if (status == 0xff) {
+ printf("cf_ata0: No disk!\n");
+ return;
+ }
+
+ cfreset();
+
+ if (dskinf.use_stream8) {
+ DPRINTF("setting %d bit mode.\n", 8);
+ cfwrite8(CF_FEATURE, 0x01); /* Enable 8 bit transfers */
+ cfwrite8(CF_COMMAND, ATA_SETFEATURES);
+ cfaltwait(CF_S_READY);
+ }
+
+#ifdef DEBUG
+ rval = cfgetparams();
+ if (rval)
+ return;
+#endif
+ dskinf.use_lba = 1;
+ dskinf.debug = 0;
+}
+
+static void
+cf_clr(void)
+{
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ cfaltwait(CF_S_READY);
+ cfwrite8(CF_FEATURE, 0x81); /* Enable 8 bit transfers */
+ cfwrite8(CF_COMMAND, ATA_SETFEATURES);
+ cfaltwait(CF_S_READY);
+}
+
+static void
+cfenable16(void)
+{
+ u_int32_t val;
+
+ val = *dskinf.cs1to;
+ *dskinf.cs1to = val &~ EXP_BYTE_EN;
+ DELAY(100);
+#if 0
+ DPRINTF("%s: cs1 timing reg %x\n", *dskinf.cs1to, __func__);
+#endif
+}
+
+static void
+cfdisable16(void)
+{
+ u_int32_t val;
+
+ DELAY(100);
+ val = *dskinf.cs1to;
+ *dskinf.cs1to = val | EXP_BYTE_EN;
+#if 0
+ DPRINTF("%s: cs1 timing reg %x\n", *dskinf.cs1to, __func__);
+#endif
+}
+
+static u_int8_t
+cfread8(u_int32_t off)
+{
+ volatile u_int8_t *vp;
+
+ vp = (volatile u_int8_t *)(dskinf.cs1 + off);
+ return *vp;
+}
+
+static void
+cfreadstream8(void *buf, int length)
+{
+ u_int8_t *lbuf;
+ u_int8_t tmp;
+
+ lbuf = buf;
+ while (length) {
+ tmp = cfread8(CF_DATA);
+ *lbuf = tmp;
+#ifdef DEBUG
+ if (dskinf.debug && (length > (512 - 32))) {
+ if ((length % 16) == 0)
+ xputchar('\n');
+ puthex8(tmp);
+ putchar(' ');
+ }
+#endif
+ lbuf++;
+ length--;
+ }
+#ifdef DEBUG
+ if (dskinf.debug)
+ xputchar('\n');
+#endif
+}
+
+static u_int16_t
+cfread16(u_int32_t off)
+{
+ volatile u_int16_t *vp;
+
+ vp = (volatile u_int16_t *)(dskinf.cs1 + off);
+ return swap16(*vp);
+}
+
+static void
+cfreadstream16(void *buf, int length)
+{
+ u_int16_t *lbuf;
+
+ length = length / 2;
+ cfenable16();
+ lbuf = buf;
+ while (length--) {
+ *lbuf = cfread16(CF_DATA);
+ lbuf++;
+ }
+ cfdisable16();
+}
+
+static void
+cfwrite8(u_int32_t off, u_int8_t val)
+{
+ volatile u_int8_t *vp;
+
+ vp = (volatile u_int8_t *)(dskinf.cs1 + off);
+ *vp = val;
+}
+
+#if 0
+static void
+cfwrite16(u_int32_t off, u_int16_t val)
+{
+ volatile u_int16_t *vp;
+
+ vp = (volatile u_int16_t *)(dskinf.cs1 + off);
+ *vp = val;
+}
+#endif
+
+static u_int8_t
+cfaltread8(u_int32_t off)
+{
+ volatile u_int8_t *vp;
+
+ off &= 0x0f;
+ vp = (volatile u_int8_t *)(dskinf.cs2 + off);
+ return *vp;
+}
+
+static void
+cfaltwrite8(u_int32_t off, u_int8_t val)
+{
+ volatile u_int8_t *vp;
+
+ /*
+ * This is documented in the Intel appnote 302456.
+ */
+ off &= 0x0f;
+ vp = (volatile u_int8_t *)(dskinf.cs2 + off);
+ *vp = val;
+}
+
+static int
+cfwait(u_int8_t mask)
+{
+ u_int8_t status;
+ u_int32_t tout;
+
+ tout = 0;
+ while (tout <= 5000000) {
+ status = cfread8(CF_STATUS);
+ if (status == 0xff) {
+ printf("%s: master: no status, reselecting\n",
+ __func__);
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1);
+ status = cfread8(CF_STATUS);
+ }
+ if (status == 0xff)
+ return -1;
+ dskinf.status = status;
+ if (!(status & CF_S_BUSY)) {
+ if (status & CF_S_ERROR) {
+ dskinf.error = cfread8(CF_ERROR);
+ printf("%s: error, status 0x%x error 0x%x\n",
+ __func__, status, dskinf.error);
+ }
+ if ((status & mask) == mask) {
+ DPRINTF("%s: status 0x%x mask 0x%x tout %u\n",
+ __func__, status, mask, tout);
+ return (status & CF_S_ERROR);
+ }
+ }
+ if (tout > 1000) {
+ tout += 1000;
+ DELAY(1000);
+ } else {
+ tout += 10;
+ DELAY(10);
+ }
+ }
+ return -1;
+}
+
+static int
+cfaltwait(u_int8_t mask)
+{
+ u_int8_t status;
+ u_int32_t tout;
+
+ tout = 0;
+ while (tout <= 5000000) {
+ status = cfaltread8(CF_ALT_STATUS);
+ if (status == 0xff) {
+ printf("cfaltwait: master: no status, reselecting\n");
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1);
+ status = cfread8(CF_STATUS);
+ }
+ if (status == 0xff)
+ return -1;
+ dskinf.status = status;
+ if (!(status & CF_S_BUSY)) {
+ if (status & CF_S_ERROR)
+ dskinf.error = cfread8(CF_ERROR);
+ if ((status & mask) == mask) {
+ DPRINTF("cfaltwait: tout %u\n", tout);
+ return (status & CF_S_ERROR);
+ }
+ }
+ if (tout > 1000) {
+ tout += 1000;
+ DELAY(1000);
+ } else {
+ tout += 10;
+ DELAY(10);
+ }
+ }
+ return -1;
+}
+
+static int
+cfcmd(u_int32_t cmd, u_int32_t cylinder, u_int32_t head, u_int32_t sector,
+ u_int32_t count, u_int32_t feature)
+{
+ if (cfwait(0) < 0) {
+ printf("cfcmd: timeout\n");
+ return -1;
+ }
+ cfwrite8(CF_FEATURE, feature);
+ cfwrite8(CF_CYL_L, cylinder);
+ cfwrite8(CF_CYL_H, cylinder >> 8);
+ if (dskinf.use_lba)
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM | CF_D_LBA | head);
+ else
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM | head);
+ cfwrite8(CF_SECT_NUM, sector);
+ cfwrite8(CF_SECT_CNT, count);
+ cfwrite8(CF_COMMAND, cmd);
+ return 0;
+}
+
+static void
+cfreset(void)
+{
+ u_int8_t status;
+ u_int32_t tout;
+
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1);
+#ifdef DEBUG
+ cfprintregs();
+#endif
+ cfread8(CF_STATUS);
+ cfaltwrite8(CF_ALT_DEV_CTR, CF_A_IDS | CF_A_RESET);
+ DELAY(10000);
+ cfaltwrite8(CF_ALT_DEV_CTR, CF_A_IDS);
+ DELAY(10000);
+ cfread8(CF_ERROR);
+ DELAY(3000);
+
+ for (tout = 0; tout < 310000; tout++) {
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1);
+ status = cfread8(CF_STATUS);
+ if (!(status & CF_S_BUSY))
+ break;
+ DELAY(100);
+ }
+ DELAY(1);
+ if (status & CF_S_BUSY) {
+ cfprintregs();
+ printf("cfreset: Status stayed busy after reset.\n");
+ }
+ DPRINTF("cfreset: finished, tout %u\n", tout);
+}
+
+#ifdef DEBUG
+static int
+cfgetparams(void)
+{
+ u_int8_t *buf;
+
+ buf = (u_int8_t *)(0x170000);
+ p_memset((char *)buf, 0, 1024);
+ /* Select the drive. */
+ cfwrite8(CF_DRV_HEAD, CF_D_IBM);
+ DELAY(1);
+ cfcmd(ATA_ATA_IDENTIFY, 0, 0, 0, 0, 0);
+ if (cfaltwait(CF_S_READY | CF_S_DSC | CF_S_DRQ)) {
+ printf("cfgetparams: ATA_IDENTIFY failed.\n");
+ return -1;
+ }
+ if (dskinf.use_stream8)
+ cfreadstream8(buf, 512);
+ else
+ cfreadstream16(buf, 512);
+ if (dskinf.debug)
+ cfprintregs();
+#if 0
+ memcpy(&dskinf.ata_params, buf, sizeof(struct ata_params));
+ dskinf.cylinders = dskinf.ata_params.cylinders;
+ dskinf.heads = dskinf.ata_params.heads;
+ dskinf.sectors = dskinf.ata_params.sectors;
+ printf("dsk0: sec %x, hd %x, cyl %x, stat %x, err %x\n",
+ (u_int32_t)dskinf.ata_params.sectors,
+ (u_int32_t)dskinf.ata_params.heads,
+ (u_int32_t)dskinf.ata_params.cylinders,
+ (u_int32_t)dskinf.status,
+ (u_int32_t)dskinf.error);
+#endif
+ dskinf.status = cfread8(CF_STATUS);
+ if (dskinf.debug)
+ printf("cfgetparams: ata_params * %x, stat %x\n",
+ (u_int32_t)buf, (u_int32_t)dskinf.status);
+ return 0;
+}
+#endif /* DEBUG */
+
+static void
+cfprintregs(void)
+{
+ u_int8_t rv;
+
+ putstr("cfprintregs: regs error ");
+ rv = cfread8(CF_ERROR);
+ puthex8(rv);
+ putstr(", count ");
+ rv = cfread8(CF_SECT_CNT);
+ puthex8(rv);
+ putstr(", sect ");
+ rv = cfread8(CF_SECT_NUM);
+ puthex8(rv);
+ putstr(", cyl low ");
+ rv = cfread8(CF_CYL_L);
+ puthex8(rv);
+ putstr(", cyl high ");
+ rv = cfread8(CF_CYL_H);
+ puthex8(rv);
+ putstr(", drv head ");
+ rv = cfread8(CF_DRV_HEAD);
+ puthex8(rv);
+ putstr(", status ");
+ rv = cfread8(CF_STATUS);
+ puthex8(rv);
+ putstr("\n");
+}
+
+int
+avila_read(char *dest, unsigned source, unsigned length)
+{
+ if (dskinf.use_lba == 0 && source == 0)
+ source++;
+ if (dskinf.debug)
+ printf("avila_read: 0x%x, sect %d num secs %d\n",
+ (u_int32_t)dest, source, length);
+ while (length) {
+ cfwait(CF_S_READY);
+ /* cmd, cyl, head, sect, count, feature */
+ cfcmd(ATA_READ, (source >> 8) & 0xffff, source >> 24,
+ source & 0xff, 1, 0);
+
+ cfwait(CF_S_READY | CF_S_DRQ | CF_S_DSC);
+ if (dskinf.use_stream8)
+ cfreadstream8(dest, 512);
+ else
+ cfreadstream16(dest, 512);
+ length--;
+ source++;
+ dest += 512;
+ }
+ return 0;
+}
+
+/*
+ * Gateworks Avila Support.
+ */
+static int
+avila_probe(int boardtype_hint)
+{
+ volatile u_int32_t *cs;
+ /*
+ * Redboot only configure the chip selects that are needed, so
+ * use that to figure out if it is an Avila or ADI board. The
+ * Avila boards use CS2 and ADI does not.
+ */
+ cs = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS2_OFFSET);
+ return (*cs != 0);
+}
+
+static void
+avila_init(void)
+{
+ /* Config the serial port. RedBoot should do the rest. */
+ ubase = (u_int8_t *)(IXP425_UART0_HWBASE);
+
+ dskinf.cs1to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS1_OFFSET);
+ dskinf.cs2to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS2_OFFSET);
+ dskinf.cs1 = (u_int8_t *)IXP425_EXP_BUS_CS1_HWBASE;
+ dskinf.cs2 = (u_int8_t *)IXP425_EXP_BUS_CS2_HWBASE;
+
+ cf_init();
+}
+BOARD_CONFIG(avila, "Gateworks Avila");
+
+/*
+ * Gateworks Cambria Support.
+ */
+static int
+cambria_probe(int boardtype_hint)
+{
+ return cpu_is_ixp43x();
+}
+
+static void
+cambria_init(void)
+{
+ /* Config the serial port. RedBoot should do the rest. */
+ ubase = (u_int8_t *)(IXP425_UART0_HWBASE);
+
+ dskinf.cs1to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS3_OFFSET);
+ dskinf.cs2to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS4_OFFSET);
+ dskinf.cs1 = (u_int8_t *)CAMBRIA_CFSEL0_HWBASE;
+ dskinf.cs2 = (u_int8_t *)CAMBRIA_CFSEL1_HWBASE;
+
+ cf_init();
+}
+BOARD_CONFIG(cambria, "Gateworks Cambria");
+
+/*
+ * Pronghorn Metro Support.
+ */
+static int
+pronghorn_probe(int boardtype_hint)
+{
+ volatile u_int32_t *cs;
+ /*
+ * Redboot only configure the chip selects that are needed, so
+ * use that to figure out if it is an Avila or ADI board. The
+ * Avila boards use CS2 and ADI does not.
+ */
+ cs = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS2_OFFSET);
+ return (*cs == 0);
+}
+
+static void
+pronghorn_init(void)
+{
+ /* Config the serial port. RedBoot should do the rest. */
+ ubase = (u_int8_t *)(IXP425_UART1_HWBASE);
+
+ dskinf.cs1to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS3_OFFSET);
+ dskinf.cs2to = (u_int32_t *)(IXP425_EXP_HWBASE + EXP_TIMING_CS4_OFFSET);
+ dskinf.cs1 = (u_int8_t *)IXP425_EXP_BUS_CS3_HWBASE;
+ dskinf.cs2 = (u_int8_t *)IXP425_EXP_BUS_CS4_HWBASE;
+
+ cf_init();
+}
+BOARD_CONFIG(pronghorn, "Pronghorn Metro");
Property changes on: trunk/sys/boot/arm/ixp425/boot2/ixp425_board.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/ixp425/boot2/lib.h
===================================================================
--- trunk/sys/boot/arm/ixp425/boot2/lib.h (rev 0)
+++ trunk/sys/boot/arm/ixp425/boot2/lib.h 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,66 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 John Hay. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef ARM_BOOT_LIB_H
+#define ARM_BOOT_LIB_H
+
+#include <sys/cdefs.h>
+#include <sys/param.h>
+
+void DELAY(int);
+
+int getc(int);
+void putchar(int);
+void xputchar(int);
+void putstr(const char *);
+void puthex8(u_int8_t);
+void puthexlist(const u_int8_t *, int);
+void printf(const char *fmt,...);
+
+void bzero(void *, size_t);
+char *strcpy(char *to, const char *from);
+int strcmp(const char *to, const char *from);
+int p_strlen(const char *);
+int p_memcmp(const char *, const char *, unsigned);
+void *memchr(const void *, int, size_t);
+void memcpy(void *to, const void *from, unsigned size);
+void *memmem(const void *, size_t, const void *, size_t);
+void p_memset(char *buffer, char value, int size);
+
+#define strlen p_strlen
+#define memcmp p_memcmp
+#define memset p_memset
+
+u_int16_t swap16(u_int16_t);
+u_int32_t swap32(u_int32_t);
+
+const char *board_init(void);
+void clr_board(void);
+int avila_read(char*, unsigned, unsigned);
+u_int cpu_id(void);
+
+#endif /* !ARM_BOOT_LIB_H */
Property changes on: trunk/sys/boot/arm/ixp425/boot2/lib.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/Makefile
===================================================================
--- trunk/sys/boot/arm/uboot/Makefile (rev 0)
+++ trunk/sys/boot/arm/uboot/Makefile 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,113 @@
+# $MidnightBSD$
+# $FreeBSD$
+
+.include <bsd.own.mk>
+
+PROG= ubldr
+NEWVERSWHAT= "U-Boot loader" ${MACHINE_ARCH}
+BINDIR?= /boot
+INSTALLFLAGS= -b
+WARNS?= 1
+
+# Architecture-specific loader code
+SRCS= start.S conf.c vers.c
+
+.if !defined(LOADER_NO_DISK_SUPPORT)
+LOADER_DISK_SUPPORT?= yes
+.else
+LOADER_DISK_SUPPORT= no
+.endif
+LOADER_UFS_SUPPORT?= yes
+LOADER_CD9660_SUPPORT?= no
+LOADER_EXT2FS_SUPPORT?= no
+LOADER_NET_SUPPORT?= yes
+LOADER_NFS_SUPPORT?= yes
+LOADER_TFTP_SUPPORT?= no
+LOADER_GZIP_SUPPORT?= no
+LOADER_BZIP2_SUPPORT?= no
+.if ${MK_FDT} != "no"
+LOADER_FDT_SUPPORT= yes
+.else
+LOADER_FDT_SUPPORT= no
+.endif
+
+.if ${LOADER_DISK_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_DISK_SUPPORT
+.endif
+.if ${LOADER_UFS_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_UFS_SUPPORT
+.endif
+.if ${LOADER_CD9660_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_CD9660_SUPPORT
+.endif
+.if ${LOADER_EXT2FS_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_EXT2FS_SUPPORT
+.endif
+.if ${LOADER_GZIP_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_GZIP_SUPPORT
+.endif
+.if ${LOADER_BZIP2_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_BZIP2_SUPPORT
+.endif
+.if ${LOADER_NET_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_NET_SUPPORT
+.endif
+.if ${LOADER_NFS_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_NFS_SUPPORT
+.endif
+.if ${LOADER_TFTP_SUPPORT} == "yes"
+CFLAGS+= -DLOADER_TFTP_SUPPORT
+.endif
+.if ${LOADER_FDT_SUPPORT} == "yes"
+CFLAGS+= -I${.CURDIR}/../../fdt
+CFLAGS+= -I${.OBJDIR}/../../fdt
+CFLAGS+= -DLOADER_FDT_SUPPORT
+LIBFDT= ${.OBJDIR}/../../fdt/libfdt.a
+.endif
+
+.if !defined(NO_FORTH)
+# Enable BootForth
+BOOT_FORTH= yes
+CFLAGS+= -DBOOT_FORTH -I${.CURDIR}/../../ficl -I${.CURDIR}/../../ficl/arm
+LIBFICL= ${.OBJDIR}/../../ficl/libficl.a
+.endif
+
+# Always add MI sources
+.PATH: ${.CURDIR}/../../common
+.include "${.CURDIR}/../../common/Makefile.inc"
+CFLAGS+= -I${.CURDIR}/../../common
+CFLAGS+= -I.
+
+CLEANFILES+= vers.c loader.help
+
+CFLAGS+= -ffreestanding
+
+LDFLAGS= -nostdlib -static -T ${.CURDIR}/ldscript.${MACHINE_CPUARCH}
+
+# Pull in common loader code
+.PATH: ${.CURDIR}/../../uboot/common
+.include "${.CURDIR}/../../uboot/common/Makefile.inc"
+CFLAGS+= -I${.CURDIR}/../../uboot/common
+
+# U-Boot standalone support library
+LIBUBOOT= ${.OBJDIR}/../../uboot/lib/libuboot.a
+CFLAGS+= -I${.CURDIR}/../../uboot/lib
+CFLAGS+= -I${.OBJDIR}/../../uboot/lib
+
+# where to get libstand from
+CFLAGS+= -I${.CURDIR}/../../../../lib/libstand/
+
+DPADD= ${LIBFICL} ${LIBUBOOT} ${LIBFDT} ${LIBSTAND}
+LDADD= ${LIBFICL} ${LIBUBOOT} ${LIBFDT} -lstand
+
+vers.c: ${.CURDIR}/../../common/newvers.sh ${.CURDIR}/version
+ sh ${.CURDIR}/../../common/newvers.sh ${.CURDIR}/version ${NEWVERSWHAT}
+
+loader.help: help.common help.uboot
+ cat ${.ALLSRC} | \
+ awk -f ${.CURDIR}/../../common/merge_help.awk > ${.TARGET}
+
+.PATH: ${.CURDIR}/../../forth
+FILES= loader.help
+
+.include <bsd.prog.mk>
Property changes on: trunk/sys/boot/arm/uboot/Makefile
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/conf.c
===================================================================
--- trunk/sys/boot/arm/uboot/conf.c (rev 0)
+++ trunk/sys/boot/arm/uboot/conf.c 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,92 @@
+/* $MidnightBSD$ */
+/*-
+ * Copyright (c) 2008 Semihalf, Rafal Jaworowski
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <stand.h>
+#include "bootstrap.h"
+#include "libuboot.h"
+
+#if defined(LOADER_NET_SUPPORT)
+#include "dev_net.h"
+#endif
+
+struct devsw *devsw[] = {
+#if defined(LOADER_DISK_SUPPORT) || defined(LOADER_CD9660_SUPPORT)
+ &uboot_storage,
+#endif
+#if defined(LOADER_NET_SUPPORT)
+ &netdev,
+#endif
+ NULL
+};
+
+struct fs_ops *file_system[] = {
+#if defined(LOADER_UFS_SUPPORT)
+ &ufs_fsops,
+#endif
+#if defined(LOADER_CD9660_SUPPORT)
+ &cd9660_fsops,
+#endif
+#if defined(LOADER_EXT2FS_SUPPORT)
+ &ext2fs_fsops,
+#endif
+#if defined(LOADER_NFS_SUPPORT)
+ &nfs_fsops,
+#endif
+#if defined(LOADER_TFTP_SUPPORT)
+ &tftp_fsops,
+#endif
+#if defined(LOADER_GZIP_SUPPORT)
+ &gzipfs_fsops,
+#endif
+#if defined(LOADER_BZIP2_SUPPORT)
+ &bzipfs_fsops,
+#endif
+ NULL
+};
+
+struct netif_driver *netif_drivers[] = {
+#if defined(LOADER_NET_SUPPORT)
+ &uboot_net,
+#endif
+ NULL,
+};
+
+struct file_format *file_formats[] = {
+ &uboot_elf,
+ NULL
+};
+
+extern struct console uboot_console;
+
+struct console *consoles[] = {
+ &uboot_console,
+ NULL
+};
Property changes on: trunk/sys/boot/arm/uboot/conf.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/help.uboot
===================================================================
--- trunk/sys/boot/arm/uboot/help.uboot (rev 0)
+++ trunk/sys/boot/arm/uboot/help.uboot 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1 @@
+$MidnightBSD$
Property changes on: trunk/sys/boot/arm/uboot/help.uboot
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/ldscript.arm
===================================================================
--- trunk/sys/boot/arm/uboot/ldscript.arm (rev 0)
+++ trunk/sys/boot/arm/uboot/ldscript.arm 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,133 @@
+/* $MidnightBSD$ */
+
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = 0x1000000 + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rela.text :
+ { *(.rela.text) *(.rela.gnu.linkonce.t*) }
+ .rela.data :
+ { *(.rela.data) *(.rela.gnu.linkonce.d*) }
+ .rela.rodata :
+ { *(.rela.rodata) *(.rela.gnu.linkonce.r*) }
+ .rela.got : { *(.rela.got) }
+ .rela.got1 : { *(.rela.got1) }
+ .rela.got2 : { *(.rela.got2) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rela.init : { *(.rela.init) }
+ .rela.fini : { *(.rela.fini) }
+ .rela.bss : { *(.rela.bss) }
+ .rela.plt : { *(.rela.plt) }
+ .rela.sdata : { *(.rela.sdata) }
+ .rela.sbss : { *(.rela.sbss) }
+ .rela.sdata2 : { *(.rela.sdata2) }
+ .rela.sbss2 : { *(.rela.sbss2) }
+ .text :
+ {
+ *(.text)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } =0
+ _etext = .;
+ PROVIDE (etext = .);
+ .init : { *(.init) } =0
+ .fini : { *(.fini) } =0
+ .rodata : { *(.rodata) *(.gnu.linkonce.r*) }
+ .rodata1 : { *(.rodata1) }
+ .sdata2 : { *(.sdata2) }
+ .sbss2 : { *(.sbss2) }
+ /* Adjust the address for the data segment to the next page up. */
+ . = ((. + 0x1000) & ~(0x1000 - 1));
+ .data :
+ {
+ *(.data)
+ *(.gnu.linkonce.d*)
+ CONSTRUCTORS
+ }
+ .data1 : { *(.data1) }
+ .got1 : { *(.got1) }
+ .dynamic : { *(.dynamic) }
+ /* Put .ctors and .dtors next to the .got2 section, so that the pointers
+ get relocated with -mrelocatable. Also put in the .fixup pointers.
+ The current compiler no longer needs this, but keep it around for 2.7.2 */
+ PROVIDE (_GOT2_START_ = .);
+ .got2 : { *(.got2) }
+ PROVIDE (__CTOR_LIST__ = .);
+ .ctors : { *(.ctors) }
+ PROVIDE (__CTOR_END__ = .);
+ PROVIDE (__DTOR_LIST__ = .);
+ .dtors : { *(.dtors) }
+ PROVIDE (__DTOR_END__ = .);
+ PROVIDE (_FIXUP_START_ = .);
+ .fixup : { *(.fixup) }
+ PROVIDE (_FIXUP_END_ = .);
+ PROVIDE (_GOT2_END_ = .);
+ PROVIDE (_GOT_START_ = .);
+ .got : { *(.got) }
+ .got.plt : { *(.got.plt) }
+ PROVIDE (_GOT_END_ = .);
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata : { *(.sdata) }
+ _edata = .;
+ PROVIDE (edata = .);
+ .sbss :
+ {
+ PROVIDE (__sbss_start = .);
+ *(.sbss)
+ *(.scommon)
+ *(.dynsbss)
+ PROVIDE (__sbss_end = .);
+ }
+ .plt : { *(.plt) }
+ .bss :
+ {
+ PROVIDE (__bss_start = .);
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* These must appear regardless of . */
+}
Property changes on: trunk/sys/boot/arm/uboot/ldscript.arm
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/start.S
===================================================================
--- trunk/sys/boot/arm/uboot/start.S (rev 0)
+++ trunk/sys/boot/arm/uboot/start.S 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,93 @@
+/*-
+ * Copyright (c) 2008 Semihalf, Rafal Czubak
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $MidnightBSD$
+ */
+
+#include <machine/asm.h>
+
+/*
+ * Entry point to the loader that U-Boot passes control to.
+ */
+ .text
+ .globl _start
+_start:
+ /* Hint where to look for the API signature */
+ ldr ip, =uboot_address
+ str sp, [ip]
+
+ /* Save U-Boot's r8 */
+ ldr ip, =saved_regs
+ str r8, [ip, #0]
+
+ /* Start loader */
+ b main
+
+/*
+ * syscall()
+ */
+ENTRY(syscall)
+ /* Save caller's lr */
+ ldr ip, =saved_regs
+ str lr, [ip, #4]
+ /* Save loader's r8 */
+ ldr ip, =saved_regs
+ str r8, [ip, #8]
+
+ /* Restore U-Boot's r8 */
+ ldr ip, =saved_regs
+ ldr r8, [ip, #0]
+ /* Call into U-Boot */
+ ldr lr, =return_from_syscall
+ ldr ip, =syscall_ptr
+ ldr pc, [ip]
+
+return_from_syscall:
+ /* Restore loader's r8 */
+ ldr ip, =saved_regs
+ ldr r8, [ip, #8]
+ /* Restore caller's lr */
+ ldr ip, =saved_regs
+ ldr lr, [ip, #4]
+ /* Return to caller */
+ mov pc, lr
+
+/*
+ * Data section
+ */
+ .data
+ .align 4
+ .globl syscall_ptr
+syscall_ptr:
+ .long 0
+
+ .globl uboot_address
+uboot_address:
+ .long 0
+
+saved_regs:
+ .long 0 /* U-Boot's r8 */
+ .long 0 /* Loader's r8 */
+ .long 0 /* Loader's lr */
Property changes on: trunk/sys/boot/arm/uboot/start.S
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Added: trunk/sys/boot/arm/uboot/version
===================================================================
--- trunk/sys/boot/arm/uboot/version (rev 0)
+++ trunk/sys/boot/arm/uboot/version 2018-05-24 11:40:01 UTC (rev 9885)
@@ -0,0 +1,8 @@
+$MidnightBSD$
+
+NOTE ANY CHANGES YOU MAKE TO THE BOOTBLOCKS HERE. The format of this
+file is important. Make sure the current version number is on line 6.
+
+1.1: Flattened Device Tree blob support.
+1.0: Added storage support. Booting from HDD, USB, etc. is now possible.
+0.5: Initial U-Boot/arm version (netbooting only).
Property changes on: trunk/sys/boot/arm/uboot/version
___________________________________________________________________
Added: svn:keywords
## -0,0 +1 ##
+MidnightBSD=%H
\ No newline at end of property
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