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Searched refs:DAG (Results 1 – 25 of 135) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp593 SDLoc DL, SelectionDAG &DAG) const { in LowerReturn()
594 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
604 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
606 const Function &Fn = *DAG.getMachineFunction().getFunction(); in LowerCall()
616 DAG.getContext()->diagnose(NoCalls); in LowerCall()
621 SelectionDAG &DAG) const { in LowerOperation()
628 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
629 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
630 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
631 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
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HDSIISelLowering.cpp435 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, in LowerParameter() argument
438 const DataLayout &DL = DAG.getDataLayout(); in LowerParameter()
439 MachineFunction &MF = DAG.getMachineFunction(); in LowerParameter()
444 Type *Ty = VT.getTypeForEVT(*DAG.getContext()); in LowerParameter()
446 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); in LowerParameter()
449 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL, in LowerParameter()
451 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr, in LowerParameter()
452 DAG.getConstant(Offset, SL, PtrVT)); in LowerParameter()
453 SDValue PtrOffset = DAG.getUNDEF(PtrVT); in LowerParameter()
467 SDValue Load = DAG.getLoad(ISD::UNINDEXED, ISD::ZEXTLOAD, in LowerParameter()
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HDR600ISelLowering.cpp577 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
578 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
581 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
582 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
583 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
584 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG); in LowerOperation()
586 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG); in LowerOperation()
587 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
588 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
590 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
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HDAMDGPUISelLowering.h35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZSelectionDAGInfo.cpp26 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem() argument
42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
43 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
44 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
46 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
50 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy() argument
59 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
67 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore() argument
74 return DAG.getStore(Chain, DL, in memsetStore()
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HDSystemZISelLowering.h392 SelectionDAG &DAG) const override;
415 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
421 SDLoc DL, SelectionDAG &DAG,
433 SDLoc DL, SelectionDAG &DAG) const override;
435 SelectionDAG &DAG) const override;
442 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
443 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
444 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
446 SelectionDAG &DAG) const;
448 SelectionDAG &DAG, unsigned Opcode,
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeDAG.cpp58 SelectionDAG &DAG; member in __anona7c12fdd0111::SelectionDAGLegalize
68 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
74 SelectionDAGLegalize(SelectionDAG &DAG, in SelectionDAGLegalize() argument
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
164 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
169 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i)); in ReplaceNode()
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
178 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
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HDSelectionDAGBuilder.cpp101 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
110 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL, in getCopyFromParts() argument
116 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, in getCopyFromParts()
120 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in getCopyFromParts()
134 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
137 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts()
140 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, in getCopyFromParts()
142 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, in getCopyFromParts()
145 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
146 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
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HDLegalizeIntegerTypes.cpp38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); in PromoteIntegerResult()
49 N->dump(&DAG); dbgs() << "\n"; in PromoteIntegerResult()
165 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
172 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
177 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0()
178 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic0()
191 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic1()
207 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); in PromoteIntRes_AtomicCmpSwap()
214 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); in PromoteIntRes_AtomicCmpSwap()
215 SDValue Res = DAG.getAtomicCmpSwap( in PromoteIntRes_AtomicCmpSwap()
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HDLegalizeTypesGeneric.cpp43 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
59 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
60 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
64 auto &DL = DAG.getDataLayout(); in ExpandRes_BITCAST()
70 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
71 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
76 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
78 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
79 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
84 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
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HDLegalizeVectorTypes.cpp37 N->dump(&DAG); in ScalarizeVectorResult()
45 N->dump(&DAG); in ScalarizeVectorResult()
141 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_BinOp()
149 return DAG.getNode(N->getOpcode(), SDLoc(N), in ScalarizeVecRes_TernaryOp()
161 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp); in ScalarizeVecRes_BUILD_VECTOR()
178 return DAG.getConvertRndSat(NewVT, SDLoc(N), in ScalarizeVecRes_CONVERT_RNDSAT()
179 Op0, DAG.getValueType(NewVT), in ScalarizeVecRes_CONVERT_RNDSAT()
180 DAG.getValueType(Op0.getValueType()), in ScalarizeVecRes_CONVERT_RNDSAT()
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
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HDLegalizeVectorOps.cpp36 SelectionDAG& DAG; member in __anonb13307360111::VectorLegalizer
130 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} in VectorLegalizer()
136 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), in Run()
137 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) { in Run()
159 DAG.AssignTopologicalOrder(); in Run()
160 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), in Run()
161 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) in Run()
165 SDValue OldRoot = DAG.getRoot(); in Run()
167 DAG.setRoot(LegalizedNodes[OldRoot]); in Run()
172 DAG.RemoveDeadNodes(); in Run()
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HDTargetLowering.cpp48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, in isInTailCallPosition() argument
50 const Function *F = DAG.getMachineFunction().getFunction(); in isInTailCallPosition()
86 TargetLowering::makeLibCall(SelectionDAG &DAG, in makeLibCall() argument
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); in makeLibCall()
105 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), in makeLibCall()
106 getPointerTy(DAG.getDataLayout())); in makeLibCall()
108 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeLibCall()
109 TargetLowering::CallLoweringInfo CLI(DAG); in makeLibCall()
111 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) in makeLibCall()
121 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp209 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
212 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); in LowerOperation()
213 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
214 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
215 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
216 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
217 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
218 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
219 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
220 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
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HDXCoreISelLowering.h109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
115 SelectionDAG &DAG) const override;
137 SDLoc dl, SelectionDAG &DAG,
145 SDLoc dl, SelectionDAG &DAG,
147 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
149 SelectionDAG &DAG) const;
152 SelectionDAG &DAG) const;
155 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
156 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
157 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp175 SDLoc DL, SelectionDAG &DAG) const { in LowerReturn()
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
186 SDLoc DL, SelectionDAG &DAG) const { in LowerReturn_32()
187 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn_32()
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
194 *DAG.getContext()); in LowerReturn_32()
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
224 auto PtrVT = getPointerTy(DAG.getDataLayout()); in LowerReturn_32()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.h236 SelectionDAG &DAG) const override;
239 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
245 SelectionDAG &DAG) const override;
270 SelectionDAG &DAG) const override;
281 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
288 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal() argument
291 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
292 getTargetNode(N, Ty, DAG, GOTFlag)); in getAddrLocal()
293 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
297 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
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HDMipsSEISelLowering.cpp361 SelectionDAG &DAG) const { in LowerOperation()
363 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
364 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); in LowerOperation()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
372 DAG); in LowerOperation()
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
1900 SelectionDAG &DAG) const { in getPICJumpTableRelocBase()
1904 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), in getPICJumpTableRelocBase()
1905 getPointerTy(DAG.getDataLayout())); in getPICJumpTableRelocBase()
2000 SDLoc dl, SelectionDAG &DAG) const { in LowerReturn()
2001 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn()
2005 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); in LowerReturn()
2012 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl, in LowerReturn()
2024 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2026 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
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HDX86SelectionDAGInfo.cpp28 SelectionDAG &DAG, ArrayRef<unsigned> ClobberSet) const { in isBaseRegConflictPossible() argument
34 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); in isBaseRegConflictPossible()
39 DAG.getSubtarget().getRegisterInfo()); in isBaseRegConflictPossible()
48 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, in EmitTargetCodeForMemset() argument
56 DAG.getMachineFunction().getSubtarget<X86Subtarget>(); in EmitTargetCodeForMemset()
62 assert(!isBaseRegConflictPossible(DAG, ClobberSet)); in EmitTargetCodeForMemset()
80 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); in EmitTargetCodeForMemset()
81 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext()); in EmitTargetCodeForMemset()
90 TargetLowering::CallLoweringInfo CLI(DAG); in EmitTargetCodeForMemset()
92 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), in EmitTargetCodeForMemset()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.h363 SelectionDAG &DAG);
368 SelectionDAG &DAG);
373 SelectionDAG &DAG);
378 unsigned ShuffleKind, SelectionDAG &DAG);
383 unsigned ShuffleKind, SelectionDAG &DAG);
388 unsigned ShuffleKind, SelectionDAG &DAG);
393 SelectionDAG &DAG);
402 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
408 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
453 SelectionDAG &DAG) const override;
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HDPPCISelLowering.cpp1108 SelectionDAG &DAG) { in isVPKUHUMShuffleMask() argument
1109 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUHUMShuffleMask()
1139 SelectionDAG &DAG) { in isVPKUWUMShuffleMask() argument
1140 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUWUMShuffleMask()
1176 SelectionDAG &DAG) { in isVPKUDUMShuffleMask() argument
1178 static_cast<const PPCSubtarget&>(DAG.getSubtarget()); in isVPKUDUMShuffleMask()
1182 bool IsLE = DAG.getDataLayout().isLittleEndian(); in isVPKUDUMShuffleMask()
1244 unsigned ShuffleKind, SelectionDAG &DAG) { in isVMRGLShuffleMask() argument
1245 if (DAG.getDataLayout().isLittleEndian()) { in isVMRGLShuffleMask()
1269 unsigned ShuffleKind, SelectionDAG &DAG) { in isVMRGHShuffleMask() argument
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp720 const SelectionDAG &DAG, unsigned Depth) const { in computeKnownBitsForTargetNode() argument
726 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); in computeKnownBitsForTargetNode()
727 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); in computeKnownBitsForTargetNode()
1132 SDLoc dl, SelectionDAG &DAG) { in emitComparison() argument
1136 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
1170 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS) in emitComparison()
1175 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) { in getAArch64Cmp() argument
1194 RHS = DAG.getConstant(C, dl, VT); in getAArch64Cmp()
1204 RHS = DAG.getConstant(C, dl, VT); in getAArch64Cmp()
1215 RHS = DAG.getConstant(C, dl, VT); in getAArch64Cmp()
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HDAArch64ISelLowering.h233 APInt &KnownOne, const SelectionDAG &DAG,
252 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
284 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
383 SelectionDAG &DAG,
392 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
400 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
405 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
412 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
423 SelectionDAG &DAG) const override;
425 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1360 SDLoc dl, SelectionDAG &DAG, in LowerCallResult() argument
1366 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, in LowerCallResult()
1367 *DAG.getContext(), Call); in LowerCallResult()
1388 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1393 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1399 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); in LowerCallResult()
1402 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); in LowerCallResult()
1403 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1404 DAG.getConstant(0, dl, MVT::i32)); in LowerCallResult()
1407 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
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