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Searched refs:TII (Results 1 – 25 of 225) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIShrinkInstructions.cpp86 static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII, in canShrink() argument
90 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); in canShrink()
103 TII->hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers)) in canShrink()
112 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink()
114 TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in canShrink()
121 if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers)) in canShrink()
125 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in canShrink()
128 if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp)) in canShrink()
138 static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, in foldImmediates() argument
144 assert(TII->isVOP1(MI.getOpcode()) || TII->isVOP2(MI.getOpcode()) || in foldImmediates()
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HDR600ExpandSpecialInstrs.cpp35 const R600InstrInfo *TII; member in __anonbea608ee0111::R600ExpandSpecialInstrsPass
42 TII(nullptr) { } in R600ExpandSpecialInstrsPass()
61 int OpIdx = TII->getOperandIdx(*OldMI, Op); in SetFlagInNewMI()
64 TII->setImmOperand(NewMI, Op, Val); in SetFlagInNewMI()
69 TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
82 if (TII->isLDSRetInstr(MI.getOpcode())) { in runOnMachineFunction()
83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction()
86 MachineInstr *Mov = TII->buildMovInstr(&MBB, I, in runOnMachineFunction()
89 int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(), in runOnMachineFunction()
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HDR600Packetizer.cpp61 const R600InstrInfo *TII; member in __anon656cdc9c0111::R600PacketizerList
76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
88 if (TII->isPredicated(BI)) in getPreviousVector()
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
98 if (isTrans || TII->isTransOnly(BI)) { in getPreviousVector()
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
153 TII(static_cast<const R600InstrInfo *>( in R600PacketizerList()
155 TRI(TII->getRegisterInfo()) { in R600PacketizerList()
173 if (TII->isVector(*MI)) in isSoloInstruction()
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HDSILowerControlFlow.cpp73 const SIInstrInfo *TII; member in __anon937aa4600111::SILowerControlFlowPass
98 MachineFunctionPass(ID), TRI(nullptr), TII(nullptr) { } in SILowerControlFlowPass()
142 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
166 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
178 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
187 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
190 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
206 TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst) in Else()
209 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC) in Else()
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HDR600EmitClauseMarkers.cpp38 const R600InstrInfo *TII; member in __anon499fa60b0111::R600EmitClauseMarkers
56 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
59 if(TII->isVector(*MI) || in OccupiedDwords()
60 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
61 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
75 if (TII->isALUInstr(MI->getOpcode())) in isALU()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
126 TII->getSrcs(MI); in SubstituteKCacheBank()
127 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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HDR600ClauseMergePass.cpp48 const R600InstrInfo *TII; member in __anon3e6c546e0111::R600ClauseMergePass
77 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); in getCFAluSize()
83 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm(); in isCFAluEnabled()
88 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in cleanPotentialDisabledCFAlu()
107 int CntIdx = TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::COUNT); in mergeIfPossible()
111 if (CumuledInsts >= TII->getMaxAlusPerClause()) { in mergeIfPossible()
119 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE0); in mergeIfPossible()
121 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_BANK0); in mergeIfPossible()
123 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_ADDR0); in mergeIfPossible()
135 TII->getOperandIdx(AMDGPU::CF_ALU, AMDGPU::OpName::KCACHE_MODE1); in mergeIfPossible()
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HDSIFoldOperands.cpp141 const SIInstrInfo *TII) { in tryAddToFoldList() argument
142 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) { in tryAddToFoldList()
150 MI->setDesc(TII->get(AMDGPU::V_MAD_F32)); in tryAddToFoldList()
151 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII); in tryAddToFoldList()
156 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
169 bool CanCommute = TII->findCommutedOpIndices(MI, CommuteIdx0, CommuteIdx1); in tryAddToFoldList()
178 if (!CanCommute || !TII->commuteInstruction(MI)) in tryAddToFoldList()
181 if (!TII->isOperandLegal(MI, OpNo, OpToFold)) in tryAddToFoldList()
191 const SIInstrInfo *TII = in runOnMachineFunction() local
193 const SIRegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
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/NextBSD/contrib/llvm/lib/Target/ARM/
HDThumb1FrameLowering.cpp43 const TargetInstrInfo &TII, DebugLoc dl, in emitSPUpdate() argument
46 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII, in emitSPUpdate()
54 const Thumb1InstrInfo &TII = in eliminateCallFramePseudoInstr() local
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
95 const Thumb1InstrInfo &TII = in emitPrologue() local
118 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
130 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize), in emitPrologue()
135 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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HDARMFrameLowering.cpp101 const ARMBaseInstrInfo &TII, in isCSRestore() argument
124 const ARMBaseInstrInfo &TII, unsigned DestReg, in emitRegPlusImmediate() argument
131 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
134 Pred, PredReg, TII, MIFlags); in emitRegPlusImmediate()
139 const ARMBaseInstrInfo &TII, int NumBytes, in emitSPUpdate() argument
143 emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes, in emitSPUpdate()
208 DebugLoc dl, const ARMBaseInstrInfo &TII, bool HasFP) { in emitDefCFAOffsets()
218 TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitDefCFAOffsets()
234 const TargetInstrInfo &TII, in emitAligningInstructions() argument
257 AddDefaultPred(BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg) in emitAligningInstructions()
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HDThumbRegisterInfo.cpp70 const TargetInstrInfo &TII = *STI.getInstrInfo(); in emitThumb1LoadConstPool() local
76 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci)) in emitThumb1LoadConstPool()
89 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in emitThumb2LoadConstPool() local
95 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci)) in emitThumb2LoadConstPool()
129 const TargetInstrInfo &TII, in emitThumbRegPlusImmInReg() argument
151 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
154 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)) in emitThumbRegPlusImmInReg()
156 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)) in emitThumbRegPlusImmInReg()
166 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
184 int NumBytes, const TargetInstrInfo &TII, in emitThumbRegPlusImmediate() argument
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreFrameLowering.cpp64 const TargetInstrInfo &TII, in EmitDefCfaRegister() argument
68 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaRegister()
74 const TargetInstrInfo &TII, in EmitDefCfaOffset() argument
78 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitDefCfaOffset()
84 const TargetInstrInfo &TII, MachineModuleInfo *MMI, in EmitCfiOffset() argument
88 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in EmitCfiOffset()
100 const TargetInstrInfo &TII, MachineModuleInfo *MMI, in IfNeededExtSP() argument
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm); in IfNeededExtSP()
111 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4); in IfNeededExtSP()
124 const TargetInstrInfo &TII, int OffsetFromTop, in IfNeededLDAWSP() argument
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HDXCoreRegisterInfo.cpp63 const XCoreInstrInfo &TII, in InsertFPImmInst() argument
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst()
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) in InsertFPImmInst()
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) in InsertFPImmInst()
94 const XCoreInstrInfo &TII, in InsertFPConstInst() argument
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset); in InsertFPConstInst()
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) in InsertFPConstInst()
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r)) in InsertFPConstInst()
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) in InsertFPConstInst()
130 const XCoreInstrInfo &TII, in InsertSPImmInst() argument
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonExpandPredSpillCode.cpp72 const HexagonInstrInfo *TII = QST.getInstrInfo(); in runOnMachineFunction() local
107 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
111 TII->get(Opcode)); in runOnMachineFunction()
150 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
154 TII->get(Opcode)); in runOnMachineFunction()
191 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
195 TII->get(Opcode)); in runOnMachineFunction()
228 BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::A2_tfrrcr), in runOnMachineFunction()
232 TII->get(Opcode)); in runOnMachineFunction()
252 if (!TII->isValidOffset(Hexagon::S2_storeri_io, Offset)) { in runOnMachineFunction()
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HDHexagonCopyToCombine.cpp60 const HexagonInstrInfo *TII; member in __anon68ddb2730111::HexagonCopyToCombine
115 const HexagonInstrInfo *TII, in isCombinableInstType() argument
348 if(TII->mayBeNewStore(MI)) { in findPotentialNewifiableTFRs()
363 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs()
406 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); in runOnMachineFunction()
429 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively)) in runOnMachineFunction()
462 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively)) in findPairable()
551 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
558 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg) in emitCombineII()
567 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg) in emitCombineII()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsLongBranch.cpp170 const MipsInstrInfo *TII = in initMBBInfo() local
178 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI); in initMBBInfo()
217 const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>( in replaceBranch() local
219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); in replaceBranch()
220 const MCInstrDesc &NewDesc = TII->get(NewOpc); in replaceBranch()
261 const MipsInstrInfo *TII = in expandToLongBranch() local
296 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
317 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
320 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
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HDMipsSEFrameLowering.cpp75 const MipsSEInstrInfo &TII; member in __anon54efea600111::ExpandPseudo
83 TII(*static_cast<const MipsSEInstrInfo *>(Subtarget.getInstrInfo())), in ExpandPseudo()
159 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
160 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
174 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
176 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
195 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); in expandLoadACC()
197 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
199 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
220 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
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/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430FrameLowering.cpp47 const MSP430InstrInfo &TII = in emitPrologue() local
68 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
72 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) in emitPrologue()
100 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) in emitPrologue()
112 const MSP430InstrInfo &TII = in emitEpilogue() local
137 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); in emitEpilogue()
159 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); in emitEpilogue()
163 TII.get(MSP430::SUB16ri), MSP430::SP) in emitEpilogue()
172 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) in emitEpilogue()
193 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); in spillCalleeSavedRegisters() local
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64A53Fix835769.cpp82 const TargetInstrInfo *TII; member in __anonc958dd8c0111::AArch64A53Fix835769
112 TII = F.getSubtarget().getInstrInfo(); in runOnMachineFunction()
123 const TargetInstrInfo *TII) { in getBBFallenThrough() argument
136 if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) && in getBBFallenThrough()
148 const TargetInstrInfo *TII) { in getLastNonPseudo() argument
153 while ((FMBB = getBBFallenThrough(FMBB, TII))) { in getLastNonPseudo()
165 const TargetInstrInfo *TII) { in insertNopBeforeInstruction() argument
169 MachineInstr *I = getLastNonPseudo(MBB, TII); in insertNopBeforeInstruction()
172 BuildMI(I->getParent(), DL, TII->get(AArch64::HINT)).addImm(0); in insertNopBeforeInstruction()
176 BuildMI(MBB, MI, DL, TII->get(AArch64::HINT)).addImm(0); in insertNopBeforeInstruction()
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HDAArch64ExpandPseudoInsts.cpp31 const AArch64InstrInfo *TII; member in __anon1cc64d770111::AArch64ExpandPseudo
91 const AArch64InstrInfo *TII, unsigned ChunkIdx) { in tryOrrMovk() argument
99 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryOrrMovk()
109 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryOrrMovk()
142 const AArch64InstrInfo *TII) { in tryToreplicateChunks() argument
166 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in tryToreplicateChunks()
186 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
211 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi)) in tryToreplicateChunks()
276 const AArch64InstrInfo *TII) { in trySequenceOfOnes() argument
349 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri)) in trySequenceOfOnes()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.cpp331 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in lowerDynamicAlloc() local
359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) in lowerDynamicAlloc()
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) in lowerDynamicAlloc()
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in lowerDynamicAlloc()
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in lowerDynamicAlloc()
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) in lowerDynamicAlloc()
414 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) in lowerDynamicAlloc()
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HDPPCBranchSelector.cpp67 const PPCInstrInfo *TII = in runOnMachineFunction() local
74 [TII](MachineBasicBlock &MBB, unsigned Offset) -> unsigned { in runOnMachineFunction()
107 BlockSize += TII->GetInstSizeInBytes(MBBI); in runOnMachineFunction()
154 MBBStartOffset += TII->GetInstSizeInBytes(I); in runOnMachineFunction()
197 BuildMI(MBB, I, dl, TII->get(PPC::BCC)) in runOnMachineFunction()
201 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2); in runOnMachineFunction()
204 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2); in runOnMachineFunction()
206 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2); in runOnMachineFunction()
208 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2); in runOnMachineFunction()
210 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2); in runOnMachineFunction()
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HDPPCFrameLowering.cpp304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { in HandleVRSaveUpdate() argument
352 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
356 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
361 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
365 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
370 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
374 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
378 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
563 const PPCInstrInfo &TII = in emitPrologue() local
587 HandleVRSaveUpdate(MBBI, TII); in emitPrologue()
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86FrameLowering.cpp44 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) { in X86FrameLowering()
264 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
269 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
288 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
334 TII.get(getLEArOpcode(Uses64BitFramePtr)), in BuildStackAdjustment()
342 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
410 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
487 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11) in emitStackProbeCall()
489 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11); in emitStackProbeCall()
491 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol); in emitStackProbeCall()
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/NextBSD/contrib/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp111 const TargetInstrInfo *TII; member in __anonc2f739380111::PeepholeOptimizer
212 const TargetInstrInfo *TII; member in __anonc2f739380111::ValueTracker
250 const TargetInstrInfo *TII = nullptr) in ValueTracker() argument
252 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
269 const TargetInstrInfo *TII = nullptr) in ValueTracker() argument
271 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { in ValueTracker()
319 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
445 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
471 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
477 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { in optimizeCmpInstr()
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcFrameLowering.cpp48 const SparcInstrInfo &TII = in emitSPAdjustment() local
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
91 const SparcInstrInfo &TII = in emitPrologue() local
117 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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