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Searched refs:VT (Results 1 – 25 of 199) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelDAGToDAG.cpp963 EVT VT = N->getValueType(0); in SelectTable() local
978 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in SelectTable()
985 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
997 if (VT == MVT::i64) in SelectIndexedLoad()
999 else if (VT == MVT::i32) { in SelectIndexedLoad()
1011 } else if (VT == MVT::i16) { in SelectIndexedLoad()
1024 } else if (VT == MVT::i8) { in SelectIndexedLoad()
1037 } else if (VT == MVT::f32) { in SelectIndexedLoad()
1039 } else if (VT == MVT::f64 || VT.is64BitVector()) { in SelectIndexedLoad()
1041 } else if (VT.is128BitVector()) { in SelectIndexedLoad()
[all …]
HDAArch64ISelLowering.cpp430 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
434 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
436 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
437 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand); in AArch64TargetLowering()
589 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
590 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in AArch64TargetLowering()
592 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
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HDAArch64FastISel.cpp140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
145 bool simplifyAddress(Address &Addr, MVT VT);
185 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
187 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
231 unsigned materializeInt(const ConstantInt *CI, MVT VT);
232 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
286 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor() argument
287 switch (VT.SimpleTy) { in getImplicitScaleFactor()
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h204 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction() argument
206 if (VT.getVectorNumElements() == 1) in getPreferredVectorAction()
325 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion() argument
331 EVT VT) const;
376 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() argument
377 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in getRegClassFor()
389 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor() argument
390 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
396 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor() argument
397 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp79 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
81 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
86 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
729 EVT VT = N->getValueType(0); in VerifySDNode() local
731 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
736 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
738 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
803 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
804 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
805 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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HDDAGCombiner.cpp330 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
339 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
453 bool isTypeLegal(const EVT &VT) { in isTypeLegal() argument
455 return TLI.isTypeLegal(VT); in isTypeLegal()
459 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
460 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
791 EVT VT = N0.getValueType(); in ReassociateOps() local
796 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R)) in ReassociateOps()
797 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
803 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1); in ReassociateOps()
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HDTargetLowering.cpp121 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
125 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) in softenSetCCOperands()
133 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
134 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; in softenSetCCOperands()
138 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
139 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; in softenSetCCOperands()
143 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
144 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; in softenSetCCOperands()
148 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
149 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; in softenSetCCOperands()
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HDLegalizeVectorOps.cpp393 MVT VT = Op.getSimpleValueType(); in Promote() local
396 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); in Promote()
415 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
416 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
418 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); in Promote()
420 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
426 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
438 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteINT_TO_FP()
462 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
467 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteFP_TO_INT()
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HDLegalizeDAG.cpp67 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
68 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType() argument
211 unsigned NumMaskElts = VT.getVectorNumElements(); in ShuffleWithNarrowerEltType()
248 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); in ExpandConstantFP()
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32); in ExpandConstantFP()
256 EVT OrigVT = VT; in ExpandConstantFP()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
88 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType() argument
98 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentLoadRegType()
221 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
227 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
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HDSIISelLowering.cpp130 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering() local
131 if (VT == MVT::i64) in SITargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
[all …]
HDR600ISelLowering.cpp133 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering() local
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
142 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
143 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
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/NextBSD/contrib/llvm/lib/CodeGen/
HDCallingConvLower.cpp74 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
92 MVT VT = Outs[i].VT; in CheckReturn() local
94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
111 << EVT(VT).getEVTString() << '\n'; in AnalyzeReturn()
124 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
159 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
161 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
164 << EVT(VT).getEVTString() << '\n'; in AnalyzeCallResult()
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HDTargetLoweringBase.cpp680 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { in getATOMIC() argument
683 switch (VT.SimpleTy) { \ in getATOMIC()
801 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
805 setIndexedLoadAction(IM, VT, Expand); in initActions()
806 setIndexedStoreAction(IM, VT, Expand); in initActions()
810 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
813 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
814 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
815 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
816 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h56 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
57 FastID(ID), VTs(VT), NumVTs(Num) {
420 SDVTList getVTList(EVT VT);
429 SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false,
431 SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false,
433 SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
436 SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,
438 return getConstant(Val, DL, VT, true, isOpaque);
440 SDValue getTargetConstant(const APInt &Val, SDLoc DL, EVT VT,
442 return getConstant(Val, DL, VT, true, isOpaque);
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HDValueTypes.h41 bool operator==(EVT VT) const {
42 return !(*this != VT);
44 bool operator!=(EVT VT) const {
45 if (V.SimpleTy != VT.V.SimpleTy)
48 return LLVMTy != VT.LLVMTy;
70 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) { in getVectorVT()
71 MVT M = MVT::getVectorVT(VT.V, NumElements); in getVectorVT()
74 return getExtendedVectorVT(Context, VT, NumElements); in getVectorVT()
171 bool bitsEq(EVT VT) const { in bitsEq()
172 if (EVT::operator==(VT)) return true; in bitsEq()
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HDMachineValueType.h470 bool bitsGT(MVT VT) const { in bitsGT() argument
471 return getSizeInBits() > VT.getSizeInBits(); in bitsGT()
475 bool bitsGE(MVT VT) const { in bitsGE() argument
476 return getSizeInBits() >= VT.getSizeInBits(); in bitsGE()
480 bool bitsLT(MVT VT) const { in bitsLT() argument
481 return getSizeInBits() < VT.getSizeInBits(); in bitsLT()
485 bool bitsLE(MVT VT) const { in bitsLE() argument
486 return getSizeInBits() <= VT.getSizeInBits(); in bitsLE()
526 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT() argument
527 switch (VT.SimpleTy) { in getVectorVT()
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/NextBSD/contrib/llvm/lib/Target/X86/Utils/
HDX86ShuffleDecode.cpp66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask() argument
67 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSLDUPMask()
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask() argument
75 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSHDUPMask()
82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask() argument
83 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodeMOVDDUPMask()
84 unsigned ScalarSizeInBits = VT.getScalarSizeInBits(); in DecodeMOVDDUPMask()
85 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVDDUPMask()
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask() argument
97 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSLLDQMask()
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HDX86ShuffleDecode.h39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
60 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
65 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
150 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
278 MVT VT = IntVTs[i]; in X86TargetLowering() local
279 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
280 setOperationAction(ISD::MULHU, VT, Expand); in X86TargetLowering()
281 setOperationAction(ISD::SDIV, VT, Expand); in X86TargetLowering()
282 setOperationAction(ISD::UDIV, VT, Expand); in X86TargetLowering()
283 setOperationAction(ISD::SREM, VT, Expand); in X86TargetLowering()
284 setOperationAction(ISD::UREM, VT, Expand); in X86TargetLowering()
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/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON() argument
90 if (VT != PromotedLdStVT) { in addTypeForNEON()
91 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
94 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
98 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
100 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCFastISel.cpp145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
156 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
161 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
165 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
166 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
167 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
172 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
174 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZISelLowering.cpp65 static bool is32Bit(EVT VT) { in is32Bit() argument
66 switch (VT.getSimpleVT().SimpleTy) { in is32Bit()
138 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
139 if (isTypeLegal(VT)) { in SystemZTargetLowering()
141 setOperationAction(ISD::SETCC, VT, Custom); in SystemZTargetLowering()
144 setOperationAction(ISD::SELECT, VT, Expand); in SystemZTargetLowering()
147 setOperationAction(ISD::SELECT_CC, VT, Custom); in SystemZTargetLowering()
148 setOperationAction(ISD::BR_CC, VT, Custom); in SystemZTargetLowering()
163 MVT VT = MVT::SimpleValueType(I); in SystemZTargetLowering() local
164 if (isTypeLegal(VT)) { in SystemZTargetLowering()
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HDSystemZISelDAGToDAG.cpp156 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
158 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
282 SDValue getUNDEF(SDLoc DL, EVT VT) const;
285 SDValue convertTo(SDLoc DL, EVT VT, SDValue N) const;
594 EVT VT, SDValue &Base, in getAddressOperands() argument
599 Base = CurDAG->getRegister(0, VT); in getAddressOperands()
603 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT); in getAddressOperands()
604 } else if (Base.getValueType() != VT) { in getAddressOperands()
606 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 && in getAddressOperands()
609 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base); in getAddressOperands()
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp664 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, in getIndexedAddressParts() argument
671 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { in getIndexedAddressParts()
708 EVT VT; in getPostIndexedAddressParts() local
713 VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
716 VT = ST->getMemoryVT(); in getPostIndexedAddressParts()
725 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
728 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts()
978 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) { in createSplat() argument
979 if (VT.getSimpleVT() == MVT::v4i8) in createSplat()
980 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val); in createSplat()
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